JPS5487147A - Control system for input and output unit by multiplex processor - Google Patents
Control system for input and output unit by multiplex processorInfo
- Publication number
- JPS5487147A JPS5487147A JP15528877A JP15528877A JPS5487147A JP S5487147 A JPS5487147 A JP S5487147A JP 15528877 A JP15528877 A JP 15528877A JP 15528877 A JP15528877 A JP 15528877A JP S5487147 A JPS5487147 A JP S5487147A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- input
- output unit
- output
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
PURPOSE: To increase the usage efficiency of hardware, by assigning the processor and the input and output unit dynamically, and making easy the alteration and addition such as disconnection of failed processor, with the multiplex processor and microprogram system.
CONSTITUTION: FF1 displaying the operation condition of M sets of processors PC is provided and if it is in set state, the corresponded processor represents the state requested by CPU for the input and output control operation. Further, the input and output unit number is stored to the register 2 through the line 21 from CPU and the node corresponding to the matrix switches 18, 19 is controlled with the output of the decoder 3. In this case, only FF set for FF1 can output from the decoder corresponded. Thus, the vacant processor 17 is selected from the instruction from CPU and the switches 18, 19 are controlled so that the input and output unit 15 and its control memory unit 16 required for the processor 17 can be connected.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15528877A JPS5487147A (en) | 1977-12-23 | 1977-12-23 | Control system for input and output unit by multiplex processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15528877A JPS5487147A (en) | 1977-12-23 | 1977-12-23 | Control system for input and output unit by multiplex processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5487147A true JPS5487147A (en) | 1979-07-11 |
Family
ID=15602613
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15528877A Pending JPS5487147A (en) | 1977-12-23 | 1977-12-23 | Control system for input and output unit by multiplex processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5487147A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6041387A (en) * | 1983-08-17 | 1985-03-05 | Nec Corp | Signal processing device |
JPS6358562A (en) * | 1986-08-29 | 1988-03-14 | Pfu Ltd | Input/output channel device |
JPH0713917A (en) * | 1993-06-29 | 1995-01-17 | Nec Corp | Configuration change system |
-
1977
- 1977-12-23 JP JP15528877A patent/JPS5487147A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6041387A (en) * | 1983-08-17 | 1985-03-05 | Nec Corp | Signal processing device |
JPS6358562A (en) * | 1986-08-29 | 1988-03-14 | Pfu Ltd | Input/output channel device |
JPH0713917A (en) * | 1993-06-29 | 1995-01-17 | Nec Corp | Configuration change system |
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