JPS61150060A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a multiprocessor system for ensuring a high processing speed by dividing data to be processed into plural segments and executing simultaneously the processing of data corresponding to each memory request in synchronizing with a bus clock. CONSTITUTION:Processors P0-P7 in plural subsystems share and process the given work to be processed. A shared memory means 2 is constituted of plural memory banks MB0-MB7. When said processors P0-P7 transmit the memory request to use said memory banks, a mediating device 16, receiving said request, issues an enable signal for permitting the occupation of the specified memory bank, simultaneously divides data exchanged between the processors P0-P7 and the memory banks MB0-MB7 into segment data of the prescribed data amount, and assigns a time slot so formed to synchronize with a bus clock BCLK to plural memory banks.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device, and relates to a data processing device that processes digital data representing an image composed of images and characters such as letters, such as documents, drawings, etc. This is suitable for application when processing information consisting of (hereinafter referred to as image information).

[Conventional technology]

The scope of application of data processing devices for this type of image information is expanding, and if document creation, electronic files, mutual communication, etc. can be easily and inexpensively constructed as a series of systems, office automation
omation), Feature of the Office (
future of the office), paperless office
), it is believed that it is possible to provide a data processing device useful for general office processing operations in fields such as .

However, this type of image information is used when processing general data encoded in a predetermined code (for example, numerical calculations,
The amount of information is approximately 100 times larger than that of data processing, word processing, etc.). Therefore, when digitally processing image information, it is necessary to use a machine with a throughput that is 100 times or more higher than when processing general data. For this reason, conventional methods have been to use dedicated processors, dedicated hardware logic, or large computers designed with special specifications to be able to process large amounts of data, as well as to reduce the amount of processing by compressing data. Methods are being adopted to reduce the burden.

[Problem that the invention seeks to solve]

However, when this conventional method is used, there is a problem in that the overall structure of the data processing device inevitably becomes large and complicated, and moreover, a specially designed and expensive device must be used.

In order to solve this problem, it is possible to process image information using general-purpose devices such as personal computers, minicomputers, and office computers, but these general-purpose devices are not capable of processing large amounts of data. These general-purpose devices are not configured, their processing speed is slow, and they do not have the processing power to perform a variety of tasks on their own, so even if you simply use the functions of these general-purpose devices, you will not be able to process large amounts of data in a short period of time. It cannot be processed in between.

The present invention has been made in consideration of the above points, and uses a large number of devices such as general-purpose microprocessors and memories, which themselves have low processing speed and processing power, to process image information via a system bus. As well as combining with each other,
The present invention attempts to propose a data processing apparatus that has a practically sufficient execution processing speed by providing an arbitration function that simultaneously executes data processing in each device in parallel.

[Means for solving problems]

In order to solve this problem, the present invention provides data input means 9B, 9c, and 7F for inputting data, and display means 9 for displaying input data or processed data.
J, 9 has at least a file storage means 5 for storing input data or processed data, and a shared storage means 2 coupled to each of these means via a system bus 1, In a data processing device that executes data processing specified by means 9B, 9c, and 7F, a plurality of subsystems 5 perform work related to data processing.
~12, and each subsystem 5~12 is configured to perform its assigned task using a processor PO-P7 respectively coupled to the system bus 1, and also has a shared storage means 2 connected to the system bus 1, respectively. Consisting of a plurality of coupled memory banks MBO-MB7,
When the processors PO-P7 of each subsystem 5-12 issue a memory request specifying one of the memory banks MBO-MB7 to transmit and receive data via the system bus 1, the arbitration device unit 16 The arbitration unit 16 generates an enable signal for allowing the respective designated memory banks to be occupied by the processors PO to PO.
Data transmitted and received between P7 and memory banks MBO to MB7 is divided into a predetermined amount of segmented data, and data processing for memory requests issued simultaneously from multiple processors PO to P7 is performed using the bus clock of system bus 1. While synchronizing with , each partitioned data is executed sequentially and simultaneously in parallel.

In addition to this, the arbitration device section 16 also includes processors PO-P
7 and memory banks MBO to MB7 is divided into divided data of a predetermined amount of data, and the bus clock BCLK is applied to each of the plurality of memory banks.
allocate a timeslot formed to be synchronized with,
Simultaneous and parallel data processing is realized by transferring the unit processing data constituting the partitioned data via the system bus 1 at the timing of the time slot allocated to the memory bank specified by the memory request.

[Effect]

The data processing device divides the data to be processed into partitioned data of a predetermined amount based on the memory requests from each processor, and processes the data corresponding to each memory request for each partitioned data by bussing the system bus. They are executed simultaneously and in parallel while synchronizing with the clock.

In this way, when memory requests for each processor occur sequentially, it is possible to process each partitioned data item without processing all the data for each memory request at once. The process can now be executed. As a result, most of the data processing corresponding to all memory requests can be performed during the time TZO (Figure 3) during which the processing of partitioned data for multiple memory requests issued at the same time is being executed simultaneously. As a result, the overall processing time can be significantly shortened.

Therefore, even if general-purpose devices with low throughput are used as the processor and memory bank, all data can be processed in a practically sufficiently fast execution processing time. Therefore, when processing data that includes uncoded data such as image data, by using multiple general-purpose devices, it is easy to create a data processing device that has the same throughput as using a dedicated computer. Can be built.

For this reason, in particular, in the present invention, memory requests for a plurality of memory banks MBO to MB7 are handled by allocating time slots formed to be synchronized with the bus clock to each memory bank, and transmitting them between the processor and the memory banks. When transferring data, data is transferred using the system bus at the timing of the time slot assigned to the memory bank that issued the memory request, so that the data is transferred based on each memory request issued at the same time. System bus occupancy requests can be effectively arbitrated, thus ensuring simultaneous parallel processing of competing data.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

(Overall Configuration) As shown in FIG. 1, the data processing device has a system bus l coupled to eight subsystems that each share the work of a series of data processing steps to be executed sequentially, It is coupled to a shared storage device 2 shared by each subsystem.

The shared storage device 2 includes a bus and memory controller (MB
C) and board 2A each equipped with 2 (me
It has two boards 2B and 2C that are equipped with RAM having a storage capacity of 1.6 MB (ga bytes) (hereinafter referred to as (MB)), and a bus and memory controller (MBC).
When a memory request arrives from each subsystem via system bus 1, the corresponding data is transferred to local bus 2D.
The RAMs of the boards 2B and 2C are read from or written to through the RAMs of the boards 2B and 2C. In particular, when memory requests from each subsystem conflict, the bus and memory controller (MBC) arbitrates this conflict and thus allows data to be processed in parallel. , has the ability to respond to requests from all subsystems within a short period of time.

The system bus 1 is connected to processors (CPUs) PO to P7 provided in each subsystem, and is connected to each processor P0 to P7 provided in each subsystem.
O to P7 are shared by all the processors PO to P7 in order to receive and pass signals and data between the bus of the shared storage device 2 and the memory controller (MBC).

The first subsystem includes a file storage device (STS) 5
A processor PO having a data processing speed of 2 (MB/sec) is connected to the system bus 1. The processor PO is mounted on the board 5A, and is a DRAW (Direct Read af) which constitutes a storage device for filing data of the data processing device.
ter Write) 5 B and HDD (Har
d Disk Drive) File data can be stored in or read from the 5G. In this embodiment, an interface (DRAW I/F) for DRAW5B is provided on board 5A,
There is also an interface for HDD 5G (HD
Board 5D equipped with D I/F is local bus 5.
E is coupled to processor PO.

Thus, the processor PO transfers the data in the shared memory bag W2 to the HDD 5C or DRAW 5B using the system bus 1.
The data on the HDD 5G or DRAW 5B is transferred to the shared storage device 2 using the system bus 1.

The second subsystem also includes a data transmission system (NTS).
6 is allocated to system bus 1, and 2 [MB/sec
) is connected to the processor P1, which has a data processing speed of . Processor P1 is a transmission control circuit (E
ethernet controller) on the board 6A, and transmits data from the system bus 1 to the transmission line 6C made of a coaxial cable via the transmission device 6B, and also transmits data arriving via the transmission line 6C to the system bus 1. It is designed so that it can be taken into the side.

Thus, the processor P1 sends the data in the shared storage device 2 to the transmission device 6B using the system bus 1, and
Alternatively, data arriving from the outside via the transmission device 6B can be taken into the shared storage device 2 using the system bus 1, and as a result, a larger scale data processing system can be constructed by connecting the data processing device to an external device. It is made possible.

The third subsystem includes an image reading and printing device (IDS).
)7 is allocated to system bus 1, and 2 (MB/sec) is allocated to system bus 1.
) is connected to the processor P2.

The processor P2 is an image input/output controller (Iraag).
e I/O Controller) is mounted on the board A, and under the control of this image input/output controller, the image printer interface (IP1/F) board 7C and the image league interface (I It is coupled to an image printer (IP) 7E and an image reader (IR) 7F via a board 7D of an RI/F), respectively. (Then, the processor P2 takes in the image data read by the image reader 7F into the shared storage device 2 using the system bus 1, and also prints the data in the shared storage device 2 via the system bus 1 at the image printer 7. It is done like this.

The fourth subsystem includes an image information compression/decompression device (CDS).
) 8 and has a data processing rate of 2 (MB/sec), a processor P3 is connected to the system bus 1 . Processor P3 is a compression/expansion controller (
Compress/Decompress cont.
The data in the shared storage device 2 is read using the system bus 1, and the data is sent to the compression processing circuit (COMP) board 8C or decompression processing circuit (D
ECOMP) board 8D, and the compressed or expanded data is sent to the shared storage device 2 using the system bus 1.

The image information compression/expansion device 8 is the HDD of the file storage device 5.
For example, the data to be stored in 5C or DRAW 5B is
Method (Modified Huffman) or MR
The amount of stored data can be expanded by performing compression processing in advance using a Modified READ method, and the compressed data read from the HDD 5C or DRAW 5B can be expanded for display, printing, and transmission processing.

A control display device (DPS) 9 is assigned to the fifth subsystem, and a processor P4 having a data processing rate of 2.5 (MB/sec) is connected to the system bus 1. Board 9A with processor P4 installed
is equipped with a ROM and a RAM that store processing programs and data used when converting the image data read by the processor P4 into video display signals.

The operation display device 9 also has a keyboard 9 as an operation input means.
The board 9A has a keyboard 9B and a mouse 9C, and data from the keyboard 9B and mouse 9C can be input and output to the processor P4 through a serial input circuit (S110) mounted on the board 9A.

Here, the data input from the keyboard 9B and the mouse 9C are encoded data each having a predetermined format, and the processor P4 inputs this input data (
For example, character data or command data consisting of characters, symbols, etc.) can be transferred to the shared storage device 2 using the system bus 1.

On the other hand, when displaying image data (that is, data representing an image, a character, or a mixture of an image and a character), the processor P4 sends these data to the bitmap controller BMC of the board 9E via the local bus 9D. as commands and data. Here, the processor P4 transfers the coded character data as a command to the bitmap controller (BMC) and converts it into corresponding font data, and then stores it in the video memory (VRAM) via the local bus 9F. The data is transferred to boards 9G and 9H and developed on a two-dimensional screen memory.

On the other hand, the image data generated in the image reader 7F is
It is uncoded data that directly represents the black and white of pixels, and when displaying this data, the processor P4 directly stores it in two-dimensional screen memory without converting it as it does for encoded character data. Expand on top.

The image data developed on the VRAM in this way is
Timing circuit (TIM) mounted on board 9■
The data is read out via the local bus 9F and displayed on displays 9J and 9 made of cathode ray tubes (CRTs), for example.

In addition to the above functions, processor P4 also has system bus 1
It has the function of reading out image data from the shared storage device 2 via the shared storage device 2, assembling and editing it on one screen, and inserting characters input from the keyboard 9B on one screen.
Processor P4 converts the processing data during this assembly/editing into C.
The data that is displayed on the RT9J, 9 and that has been assembled and edited is transferred to the shared storage device 2 via the system bus 1.

In this way, the operation display device 9 uses the image data read out from the file storage device 5 to the shared storage device 2 to assemble and edit it into one screen according to the operations of the keyboard 9B and mouse 9C as operation input means. The data is displayed on the display 9J or 9K and transferred to the shared storage device 2 using the system bus 1. This data is stored in the file storage device 5.
or is printed by the image printer 7E of the image reading and printing device 7, or transmitted from the data transmission device 6 to the outside.

A main controller (PC5) 10 is assigned to the sixth subsystem, and a processor P5 with a data processing rate of 2.5 (MB/5ec) is connected to the system bus 1. Board IO with processor P5 installed
A is the RAM of the board IOC via the local bus IOB
and the input device I10 of the board IOD are coupled to the system bus 1 by a system operating program (operating system, application program, etc.) written from a floppy disk drive (FDD) to RAM as a local memory via Ilo. It controls each subsystem and the shared storage device 2 as a whole. Interwoven and attention signals for such control are sent to the main controller 10 via the control signal line 3.
and sent and received between all subsystems.

Furthermore, the processor P5 executes a process of assembling image data to be printed by the image printer 7E according to a program input to the RAM of the board IOC.

The seventh and eighth subsystems have spare devices 11 and 12.
(the processors are denoted by P6 and P7), which allows new functions to be added.

In the configuration shown in FIG. 1, the operator can use the keyboard 9B and mouse 9C of the operation display device 9 to input commands for specifying modes and character data such as letters and symbols, and can also input images including pictures and characters. Data can be input using the image league 7F of the image reading and printing device 7.

Here, the data input from the keyboard 9B and mouse 9C is obtained as data having a predetermined code that is easy to transfer and process, and therefore character data can be input with a relatively small amount of data. On the other hand, the image data input from the image league 7F of the image reading and printing device 9 is
Since it is composed of data representing black and white of each pixel in binary code, the amount of data becomes significantly large.

Data input from the keyboard 9B or mouse 9C is transferred from the processor P4 of the operation display device 9 to the system bus l.
The data is once written to the shared storage device 2 using the system bus 1, and then transferred to the image information compression/expansion device 8 via the system bus 1, where the data is compressed. The thus processed data is transferred to the shared storage device 2 using the system bus 1 again.

After that, this data is transferred to the file storage device 5 again using the system bus 1, and is transferred to the HDD as an external storage device.
It is stored in 5G or DRAW5B.

Similarly, the image data manually inputted from the image reading/printing device 7 is transferred to the shared storage device 2 using the system bus 1.
The image information is transferred to the compression/decompression device 8 using the system bus 1 again, and after being compressed, it is transferred to the shared storage device 2 using the system bus 1 again. The data is transferred to the file storage device 5 and stored in the HDD 5G or DRAW 5B.

In this way, data compressed by the image information compression/expansion device 8 is stored in the HDD 5C and DRAW 5B, but this data is displayed on the displays 9J, 9 of the operation display bag W9 or on the image printer of the image reading/printing device 7. It is output to 7E.

In this case, data on the HDD 5C or DRAW 5B is transferred to the HDD 5C and DR of the file storage device 5 based on data from the keyboard 9B or mouse 9C of the operation display device 9.
After the accumulated data of AW5B is transferred to the shared storage device 2 using the system bus 1, it is transferred again to the image information compression/expansion device 8 using the system bus 1, and the data is expanded. The resulting data is transferred to the shared storage device 2 again using the system bus 1, and then transferred to the shared storage device 2 again using the system bus 1.
is displayed or printed on the display 9J, 9K of the operation display device 9 or the image printer 7E of the image reading/printing device 7. At this time, display 9J
, 9K is executed in the processor P4 of the operation display device 9,
Also, the assembly of a screen for the image signals supplied to the printer 7 is executed by the processor P5 of the main controller 10.

Furthermore, the data stored in the file storage device 5 may be re-edited, or a new keyboard 9B or image reader 7F may be used.
In the mode in which characters are inserted into an image input from the processor P4, each data is once transferred to the shared storage device 2 and then edited in the processor P4 in the same manner.

In this way, the data processing device shown in FIG. Data processing is executed under the control of the main controller 10 in the main controller 10 . When executing this data processing, each subsystem accesses the shared storage device 2 while sharing the system bus l.

At this time, the shared storage device 2 needs to occupy the shared storage device 2 and the system bus based on a memory request issued by one subsystem until processing of data based on the memory request is completed. However, if this occupation time is too long, data based on memory requests issued by other subsystems must be processed again for a long period of time. To solve this problem, the shared storage device 2
The bus and memory controller (MBC) is configured to have an arbitration function that simultaneously processes the supply of data from the processors of each subsystem in parallel, thus processing a series of sequential data as described below. The processing time can be significantly reduced compared to the case where the processing is executed in a time-series manner.

In the following description, when a bar is attached to the symbol of a signal or data, it is assumed that the symbol is expressed based on negative logic.

Now, for example, when searching for image data (compressed) stored in the HDD 5C and DRAW 5 as external storage devices of the file storage device 5 and displaying it on the displays 9J and 9K of the operation display device 9, The series of data processing shown in FIG. 2 is performed sequentially.

That is, in the 0th data processing step PRO,
The HD of the file storage device 5 under the control of the main controller IO
Image data to be read from the D5C or DRAW5B is searched logically.

In the following first data processing step PR1, the retrieved data is read from the file storage device 5 and transferred to the shared storage device 2. Next, in the second data processing step PR2, the data transferred to the shared storage device 2 is read out by the processor P3 of the image information compression/expansion device 8, subjected to decompression processing, and then rewritten to the shared storage device 2. Next, in the third data processing step PR3, the processor P4 of the operation display device 9 reads out the data rewritten to the shared storage device 2 and performs processing such as editing and assembling the screen and inserting characters, and then the data is rewritten to the shared storage device 2. 2 again. Next, in the fourth data processing step PR4, the operation display device 9 reads out the data stored in the shared storage device 2 again, and the bitmap data is read out from the bit map data O--79E, VRAM9G,
It is displayed on displays 9J and 9K via 9H.

In these series of data processing steps, the steps of transferring data using the system bus 1 are the first to
The fourth data processing steps PR1 to PR4 require a total processing time of processing times T1 to T4, which are determined based on the data processing speed of the processor that processes data in each step and the amount of data to be processed. .

That is, in the data processing step PRI, the data read from the HDD 5C or DRAW 5B of the file storage device 5 is processed at the data processing speed 2 (
The data is transferred to the shared storage device 2 at a rate of MB/sec during time T1. Also, the second data processing step PR
2, the processor P of the image information compression/expansion device 8
3 reads the data from the shared storage device 2 at a data processing speed of 2 (MB/sec), and the processor P3 reads the decompressed data again at a data processing speed of 2 (MB/sec).
, and thus requires a processing time T2. Further, in the third data processing step PR3, the processor P4 of the operation display device 9
After reading the data from the shared storage device 2 at a data processing speed of 2.5 (MB/sec), processor P4 executes editing processing such as assembling the screen and inserting characters. The edited data is stored in the shared storage device 2 at a data processing speed of sec), and a time T3 is required for such data processing.

Further, in the fourth data processing step PR4, the processor P4 of the operation display device 9 has a data processing speed of 2.5 (
Data is read from the shared storage device 2 at a speed of MB/see) and displayed on the displays 9J, 9, and time T4 is required to execute such data processing.

Therefore, in the data processing device having the configuration shown in FIG. 1, if the series of data processing steps shown in FIG. 2 are sequentially executed in time series, the total processing time TSM I required to process the data is: -T1+T2+T3+T4...(1)
become.

In principle, in the present invention, the work of this amount of data can be performed using predetermined segmented data (for example, 16 (kB) or 8 (kB)).
B) (about KB = kilobyte),
Using a plurality of processors, data processing is executed simultaneously and in parallel for each section of data.

That is, the series of data processing steps PR1 to P in FIG.
In R4, the data to be processed is divided into multiple sections (7 sections in the case shown) as shown in FIG. I'll process it.

In FIG. 3(A), the data processing step P in FIG.
As the first segmented data to be processed in the RI, one sector or one track is read out from the file storage device 5 by the processor PO and transferred to the shared storage device 2 during processing step PR11 of processing execution time TUI. As shown in FIG. 3(B), this first classified data is processed in processing step PR21 as the first processing data of data processing step PR2 in FIG. 2 during the next processing execution time TU2, Image information compression/expansion device 8
The data is read out from the shared storage device 2 by the processor P3, decompressed, and then stored again in the shared storage device 2. This re-stored first segment data is shown in Figure 3 (C
), it is processed in processing step PR31 at processing execution time TU3 as the first processing data in data processing step PR3 in FIG. That is, the processor P4 reads the segmented data from the shared storage device 2, performs editing processing, and then stores it again in the shared storage device 2.

As shown in FIG. 3(D), this re-stored first classified data is processed in data processing step PR41 at processing execution time TU4 as the first processing data of data processing step PR4 in FIG. . As a result, the partitioned data in the shared storage device 2 is read out by the processor P4 and displayed on the displays 9J and 9.

Thus, the first segmented data is the processing execution time TU1, T
Data processing step PRI between U2, TU3 and TU4
The rows are processed sequentially in the order of I, PH21, PR31, and PH10 (.

During this period, at the second processing execution time TU2, the processor PO of the file storage device 5 reads out the second segmented data from the external storage device and stores it in the shared storage device 2 in a data processing step PR12. This second segmented data is processed in data processing steps PR22, PH10, P every time the processing execution times TU3, TU4, and TU5 sequentially proceed in the same manner as the first segmented data.
The data is processed in H10, and the result is displayed on the displays 9J and 9 at processing execution time TU5.

Thereafter, in the same manner, the third, fourth, etc. classification data are sequentially read out from the file storage device 5 at processing execution times TU3, TU4, and so on.
The processing execution time (TU4, TU5, TU6), (TU5, TU
6, TU7)......Sequential processing steps (PH23, PH10, PH43), (PH14, P
H14, PH10), ......, the data is processed and sequentially displayed on the displays 9J, 9 in the row
.

In this way, data processing steps PR1 and P in FIG.
The data to be processed in H1, PH1, PH1 is 1
Each piece of partitioned data is processed sequentially at each partitioned data processing execution time, but each sequential process is executed simultaneously and in parallel (this is called pipeline processing), and as a result, the partitioned data processing execution time is The processors that are assigned the work of each processing step will perform data processing operations simultaneously and in parallel, which will ultimately improve the processing power of multiple processors when viewed as a single processor. , Therefore, the data summation processing time can be shortened.

Such a result can be obtained if the data processing steps PRI to PR are performed as described above with reference to FIG.
If 4 is processed sequentially and in a time series manner, while the processor assigned the task of one data processing step is processing data, other processors are not processing data. This state waits for a command to arrive, and it is thought that this wasted time will increase the overall data processing time. However, according to the method shown in Figure 3, this wasted time can be reduced. This is because it can be significantly shortened.

After all, if the data processing method according to the present invention shown in FIG. By allocating work to each processor so that the non-overlapping time TZI and TZ2 that occur before and after becomes the sum, and the non-overlapping time becomes smaller, the overall data processing time can be reduced. The time can be significantly shortened compared to the case shown in FIG.

For example, as shown in FIGS. 3(A) to 3(D), if the divided data processing execution time in each processing step is made equal to each other, the total data processing time TSM2 is 73M2= (K+ CD5P-1)) x TU・・・・・・
...(2) It can be expressed as: Here, K is the number of partitioned data in each partitioned data processing step, and DSP is the number of programs to be processed simultaneously (i.e., processing steps PRI to PRI in FIG. 2).
The number of PR4') and TU each represent the processing execution time of the partitioned data.

Therefore, according to the configuration shown in FIG. 1, even if a general-purpose microprocessor whose data processing speed is not very fast is used as a processor, the data total processing time for the entire data processing device is longer than that required for processing image data with a significantly large amount of data. It is possible to realize a data processing device with a practically sufficient throughput suitable for processing.

Simultaneous parallel processing of partitioned data in the configuration of FIG. 1 is performed by the bus and memory controller (MBC) of the shared storage device
This is achieved by an arbitration unit provided in the system bus 1 processing contention among the processors of the subsystems connected to the system bus 1 simultaneously and in parallel.

(Shared Storage Device) As shown in FIG. 4, the shared storage device 2 includes processors PO, PI, P2 of six devices 5 to 10 and two spare devices 11 and 12 that constitute a subsystem.・P
7 (this is expressed as Pil 1 = 0.1.2...7), and the system bus 1 coupled to RAM 2B and 2
By controlling the memory section 15 constituted by C (FIG. 1) by the arbitration device section 16, it is determined which subsystem's processor is to exclusively use the system bus 1.

In this embodiment, the system bus 1 includes a 20-bit address data line ADDRESS, a 16-bit read data line RDATA, a 16-bit write data line WDATA, and a read/write command R/W for selecting high-order byte or low-order byte. It is composed of a 3-bit bus for transferring signals RDS, . . . UDS, and is terminated by a termination section 17.

The memory units 15 each have 250 (kiloward)
) eight memory banks MBO1M with a memory capacity of
BI...MB? (Let this be MBj, j-0, l,
2...7), and a system bus 1 is assigned to each memory bank MBO-MB7.
By coupling the memory banks, each of the processors PO to P7 can access each memory bank separately. By doing so, while one memory bank is performing data writing and reading operations (this is called a memory cycle), other memory banks can be accessed.

The system bus l is coupled to the arbitration unit 16, and the system bus l is connected to the processors PO to P7 of the eight subsystems.
Therefore, when conflicting memory requests are issued to the memory unit 15, by arbitrating them using the configuration shown in FIGS. 5 to 7, data can be processed simultaneously and in parallel for all memory requests. be executed. Here, the contents of the memory request sent from each processor are as follows:
This is either writing data to the shared storage bag W2 or reading data stored in the shared storage device 2.

The arbitration device section 16 performs two arbitration tasks.

Its first task is to operate eight processors Pi (i-O21
, 2, .
...7).

The second mission of the arbitration device section 16 is to arbitrate which processor Pi is allowed to occupy the same memory bank MBj when memory requests are issued from a plurality of processors Pi.

The arbitration device section 16 has a time slot allocation section 16A (FIG. 5) that performs the first mission. As shown in FIGS. 6A to 6H, this time slot allocation unit 16A generates eight time slot signals TS corresponding to memory banks MBO to MB7.

~TS'+ (This is TSj, j=1.2...
・Represented as 7) are sequentially and cyclically generated, and each time slot signal TS, ~TS? The falling interval (this is called a time slot) is sequentially assigned to the processors PO to P7 of the subsystem.

Here, each time slot signal TS, ~TS? The time slot interval is selected as the processing time for unit data (for example, 1 (ward)) that is actually processed sequentially, and therefore the repetition period of each time slot is the processing execution time required to process the segmented data. TUI〜TUIO(
(Fig. 3) is selected to be a sufficiently short value. In this way, the divided data is actually processed in units of many units of data.

Thus, the time slot signals 'rso,'rst,T
During the time slots of S, . . . TS, the corresponding processors PG, PI, P2, . . .
Memory request RQo-R10I from P7, RQ!・・・・・・
...-R-Q? (This is 100Qjs j-0,1,
2...7), the processors PO1P1, P2... of the subsystem that issued the request
...Memory bank MBO1MBI,
MB2...--Enable signal indicating that MB7 can be occupied NO, EN, , E-NO1...
...1 Ren et al. (this is 11 et al., j-0, 1, 2...
...expressed as 7). Therefore, the arbitration device section 16
When the memory requests of the processors PO to P7 do not conflict, if a memory request is made for one of the memory banks MBO to MB7, the time slot corresponding to that memory bank is unconditionally used to process the memory request. (This is called a time slot allocation function.)

In addition to this, the arbitration device section 16 also receives a time slot signal T.
In each time slot of SJ (J = 0.l...7), when no corresponding memory request is generated, the time slot with no memory request is used as memory allocated to other time slots. It has a function that can be used to process memory requests for banks (this is called a time slot utilization function).

The above relationship can be expressed as follows.

E NJ-T S j+ RQ, -+ ・ENj-.

......(4) Here, TSj is the jth (j-0, 1,...7)
RQj is a request signal for the j-th memory bank MBj, and EN is an enable signal indicating that the j-th memory bank MBj may be occupied.

Here, equation (3) is expressed as the time slot signal TSj (j=0
7) indicates that time slots are generated in a continuous and sequential manner.

On the other hand, equation (4) shows that the j-th memory bank MBj
Firstly, the enable signal EN for the memory bank MBj is generated at the time slot timing of the time slot signal TS assigned to the memory bank MBj (first term TS,'), and secondly, Previous (j-
1) The request signal RQ,-, is not generated in the time slot corresponding to the th memory bank MB (j-1), and the memory bank MB (j-1) corresponding to the time slot is not used. (Second term RQ, -.

・ENJ-1) s While a memory request is issued for the j-th memory bank MBj in this way, the memory request for the previous (j-1
)-th time slot corresponding to the memory bank MB(
j-1), if no memory request has been made for
This previous time slot can be used to process a request for the j-th memory bank MBj.

This also means that when there is no memory request for the previous (i.e. (j-2)th, (j-3)th, etc.) time slot, this (j-2)th, (j-3)th... memory bank MB
(j-2), MB (j-3)... using the time slots assigned to the j-th memory bank M
This means that Bj can be accessed (
This is called the front-loading effect).

The relationship in equation (4) is expressed as enable signals EN, ~E N ? for each memory bank MBO to MB7. If expressed as , it becomes as follows.

ENI = TS1 + RQo ・ENO・・・・・・
(5) EN□='rs2+RQl -ENI=TS,
+RQ, ・TSI +R11I ・RQo
・EN.

・・・・・・(6) ENJ=TS3 +RQZ・ENt=TS
3 +RQz ・TS, +RQ, ・
RQ, ・TS.

10RQ2　・RQI-RQO・EN.

・・・・・・(7) EN, Snow TS4 +RQ3・EN.

=TS, +RQ, ・TS3+R11, ・■2
・TS.

10RQ2 ・RQt −RQI −TSI +
RQ3 ・RQ.

・RL　'RQo　・EN.

・・・・・・(8) EN, -TSS +RQ4 ・EN.

±TS, +RQ4 ・TS, 10RQ4 ・
RQ, ・TS.

+RQ4 ・RQ, ・RQ, ・TSt10RQ
4.RQ.

-RQz-RQ, -TS, 10RQ4・RQ,
・RQ.

・RQ, ・RQ, ・ENo ・・・・・・(9) EN & = TSb + RQ! I・EN.

=TS, +RQ, ・TS, 10RQ, ・
RQ4 ・TS.

+RQ, ・RQ4 ・RQ, ・TS, 10RQ, ・RQ.

・RQ, ・RQ, -TS, 10RQ, ・
RQ, ・RQ.

・RQ, ・RQ, -TS, +RQ, ・
RQ4 ・RQ.

・RQ, ・RQ, ・RQo ・ENo...
... (10) EN, =TS, +RQ, 4N.

”TS, zer,・TS&+before, 4 rinses,・TSs-R
Q, ・RQs −TSs + RQa ・R
Qa4 waves.

...... (11) ENo =TSo +RQ?・EN? =TSO
+RQ?・TS, +RQ, ・RQ, ・TS
&+RQ? -RQ6・R(15TS5 +RQ7
・RQa・RQs ・RQ, ・TS4 +RQ,
・RQa -RQs・RQ4 ・Rlh ・
TS, +lQ, ・RQa ・RQS・RQa
・RQz 4rinz TSz +RQ?
4ηi・RQs・RQ4・RQ3
・RQz ・RQ, ・TS.

+RQ7 'RQ6 'RQs 'RQ4 'R
Q3 'RQz・RQ+' RQo -EN.

・・・・・・(12) In formulas (5) to (12), the second term is formula RQ, -.

・The term ENJ-, among the terms EN,-, is obtained by substituting the previous expression, and from the resulting expansion, This means that if there is an empty slot that is not used in ).

The arbitration device section 16 further includes a memory access control section 16B (FIG. 4). As shown in FIG. 7, this memory access control section 16B is connected to the processor PO
~Decoding means 16B11-16817 corresponding to P7
(This is expressed as 16B1ii=0.1...7), and each processor PL (i=0.1・
Memory request signal PiMRQ (i-0, 1...7) indicating that a memory request has been issued from ...7)
and memory bank number data PiRA1, PiRA2 representing the specified memory bank number as a 3-bit signal.
, PiRA3 (i-0, 1...7), respectively. Thus, a 4-bit signal indicating to which memory bank a memory request has been issued is inputted to the decoding means 16B1i from the corresponding processor Pi.

The decoding means 16B1i receives a memory bank designation signal PRQ□ representing the memory bank designated by this input signal.
. ~PRQit (t=0.1...7) is generated. This memory bank designation signal PRQ.

~PRQzy is the i-th processor P by its index
This indicates that a memory request has been issued from i to the 0th to 7th memory banks MBO to MB7, and these signals are sent to memory access means 16B20 to 16B27 (this is referred to as 16B2j) provided corresponding to memory banks MBO to MB7.
S j = 0.1...7).

That is, the 0th memory access means 16B20 receives the 0th memory bank MBO among the memory bank designation signals generated from the decoding means 16B11 to 16B17.
Signals PRQO0 to PRQ, which specify . are collected,・
. . . The seventh memory access means 16B27 receives a memory bank designation signal P RQo-I-P RQ that designates the seventh bank MB7 among the memory bank designation signals generated from the decoding means 16B11 to 16B17.
7y is collected.

Expressing this generally, the j-th memory access means 1
6B2j (3-Q, 1 . . . 7) contains a memory bank designation signal MQoj= which designates the j-th memory bank MBj among the memory bank designation signals generated from the decoding means 16B11 to 16B17. PRQ? J
(This is PRQ4j, i=0.1...7,
j=0.1...7) are collected.

As shown in FIG. 8, the memory access means 16B2j latches the memory bank designation signals PRQ, . This clock φ controls the memory banks MBO to MB? It is used to operate in synchronization with the processors PO to P7, and is generated in synchronization with the pass clock BCLK.

The memory request latched by the latch circuit 25 is input to the two-person canand circuit 27 via the NOR circuit 26. This NAND circuit 27 includes the memory access means 16B2.
A busy signal BUSYJ supplied from memory bank MBj assigned to memory bank j is given as a second condition input. This busy signal BUSYj is generated when the jth memory bank MBj is not in memory cycle operation, and thus, when a memory request is issued from any processor, the corresponding jth memory bank BUSYj is generated at the output terminal of the NAND circuit 27.
The request signal RQ is obtained on the condition that the memory bank MBj is not in a memory cycle operation. This request signal RQj indicates that a memory request has been made to a memory bank that is not in a memory cycle operation state, and is sent to the time slot allocator 16A described above with reference to FIG.

Thus, the time slot allocation unit 16A assigns the time slot T expressed by equation (4) for the request signal RQ.
The enable signal EN is generated at the timing of Sj.

is returned to the two-canand circuit 28 of the memory access means 16B2-j. A request signal RQj is input to this two-person circuit 28, and thus a request signal R
After Q is generated, the output enable signal EN is generated at the timing of the time slot to which this request signal ■ is assigned.
Send O.

This output enable signal) 10π0 is latched by the clock φ in the latch circuit 29, and the latch output is the latch enable signal φEN for the output latch circuit 30.
, is sent as .

On the other hand, the latch output φPRQ□ of the latch circuit 25 is given to the priority selection means 31, and the memory bank designation signal with the highest priority among the plurality of memory bank designation signals PRQiJ arriving at the same time is selected and sent to the output latch circuit 30. be done. In this way, the output catch circuit 30 receives the memory bank designation signal φPRO selected by the priority selection means 31.
,, is latched by the clock φ, and this is used as the occupancy permission signal ACK-P7ACK (PLACK
i"Q, 1...7). This occupancy permission signal PiACK is sent as a system signal to the first processor Pi that has issued a memory request for the j-th memory bank MBj. This is a signal that allows bus 1 to be occupied.

Thus, the memory access means 16B2j (j=0.
Occupancy permission signal PiA output from 1...7)
Among the CK signals, signals for the same processor Pi are collected (FIG. 7) and sent out as the output 21 of the memory access control section 16B.

The occupancy permission signal P1ACK obtained in the memory access control section 16B in this way is returned as an operation enable signal to the processor Pi that issued the memory request from the arbitration device section 16, and as a result, the processor Pi is connected to the system bus 1. Starts the operation of sending data to.

The priority selection means 31 includes the latch circuit 2 as shown in FIG.
5 latch output φPRQoj ~ φPRQvj (this is
PRQ, JS i=0.1...7, j=0.1
...7), and when these memory bank designation signals arrive at the same time, priority selection output signals φPRO,j to φPR00B (this is expressed as φPROijS i=0 .1...7, j=
011...7).

In this embodiment, the priority order is as shown in FIG.
predetermined. That is, as described above with respect to FIG.
5, P6, and P7 are sequential file storage devices (SPS) 5
, data transmission device (NTS) 6, image reading program +J 7
) system f (IDS) 7, image information compression/decompression device (CDS)
8. Operation display device (DPS) 9. Main control device (PO2)
10, the processors of the backup device 11 and the backup device 12 are assigned, and the priority is determined to be high (in that order).This priority is determined, for example, by the processors installed in the file storage device 5 as an external storage device. HD05C
When a memory request is issued, a higher priority is assigned to a subsystem that includes a device with a high need for real-time processing.

In this way, the priority selection output signal pRoa, PR completed1j...
...PRO, j has processors PO, PL-...
...Memory bank designation signals PRQoj, PRQ, j that arrive based on the memory request issued from P7...
- An output containing PRQ7J will be sent, and these priority selection outputs φPROOj, φPRO,j...
... φPR100 and 1 are latched in the output latch circuit 30 and priority permission signals POACK and PIACK are issued, respectively.
...It will be sent as 7 with P7A.

In this way, when the same i-th memory bank MBj is designated by multiple processors at the same time, one priority selection output signal corresponding to the memory bank designation signal with the highest priority among them is output to the output latch circuit 30. The occupancy permission signal P i ACK is given only to the processor Pi corresponding to this one priority selection output signal, and thus only the processor Pi can occupy the system bus 1.

In this embodiment, the priority selection means 31 includes the locking means 3.
2 is provided (FIG. 8), and the processor Pi to which the permission signal P1ACK is given based on the priority selection output signal φPROiJ selected and obtained by the priority selection means 31 selects the predetermined data. Memory requests from other processors are rejected until the processing is completed to maintain data processing using the j-th memory bank MBj.

The function of the locking means 32 is executed based on a program stored in the local memory 10C (FIG. 1) of the main controller 10, and in this embodiment, the first
For memory bank designation signals that arrive at the same time at a certain time and are selected as having a high priority, the processor corresponding to the selected memory bank designation signal finishes processing a series of data. Even if a high-priority memory bank designation signal arrives later, this is ignored and the previously selected processor is allowed to continue occupying the j-th memory bank.

Further, the locking means 32 locks a specific memory area among the memory areas of the j-th memory bank when a memory bank designation signal based on a predetermined memory request of a predetermined processor is selected by the priority selection means 31. Lock the data so that it can only be updated.

In this way, data stored in a predetermined memory bank can be saved.

Furthermore, the arbitration device section 16 has a memory bank enable signal generation section 16G (FIG. 4), and this memory bank enable signal generation section 16C is connected to a time slot allocation section 16A (FIG. 5) as shown in FIG. Enable signal EN sent out.

It has a latch circuit 41 that receives the signal. This latch circuit 41
latches the enable signal ENJ using the clock φ, and outputs the latch output as the bank enable signal BE.
Send as NBj. This bank enable signal BE
NBJ is given to the j-th bank MBj as an operation enable signal, and thus the j-th memory bank MBj takes in data from the system bus 1 or sends stored data to the system bus 1 (this A series of operations called a memory cycle) is started.

When the memory cycle operation state is entered, the j-th memory bank MBj stops sending out the busy signal BUSYj to the arbitration device unit 16, and thus notifies the arbitration device unit 16 that it is currently in the memory cycle operation state. .

When operating the memory bank MB O-MB 7 in this way, the processors PO-MB 7 are operated via the arbitration device section 16.
In order to operate in synchronization with P7, the bus clock BCLK is supplied from the arbitration device section 16 to each memory bank.

As shown in FIG. 12, each memory bank MBj making up the memory section 15 is made up of a memory area 45 made up of, for example, a dynamic RAM and its controller 46. Then, the address data AD arriving from the address data line ADDRESS of the system bus 1 is latched by the address latch circuit 47 at the rising edge of the bus clock BCLK, and the latch output is separated into column data and row data by the address multiplexer 48, and the memory area is The row and column addresses of the 45 memory locations to be processed are specified.

On the other hand, write data WD arriving from write data line WDATA of system bus 1 is latched by write data latch circuit 49, and its latch output is input to memory area 45. Further, the data read from the memory area 45 is latched by the read data latch circuit 50, and the latch output is sent to the read data line RDATA of the system bus l according to an output timing signal generated separately by the memory control logic 52.

Furthermore, the memory controller 46 has an arbitration logic 51 and a high and low byte selection line L of the system bus 1.
The memory bank MB receives the selection signal supplied from the DS and UDS, the write/read command signal R/W, the bank enable signal BENB supplied from the arbitration device section 16, etc.
j is driven and controlled based on these signals. That is,
First, by sequentially applying drive signals to the rows and columns of the memory area 45 via the memory control logic 52 at predetermined timing, the address multiplexer 4
Read data stored in, or write data to, the memory location in the column and row specified by 8.

Second, under the control of the arbitration logic 51 and via the refresh control logic 53, the refresh address counter 54 is driven for a predetermined period of time, e.g.
The stored data is saved by sequentially refreshing each memory cell in the memory area 45 at intervals of [μ5ec].

(Operation of the embodiment) In the above configuration, the data processing device as a whole is
3. Data processing operations are executed in synchronization with the bus clock BCLK shown in FIG. 3(A). In this embodiment, the bus clock BCLK is used for each memory bank MBO to MBO of the memory section 15.
A cycle time shorter than the cycle time required for MB7 to perform one write or read operation (dynamic RAM requires a cycle time of 230 (nsec) for precharge and refresh operations) (for example, approximately 1/3 time) TCK (=76.7 (nsec)
), and this pass clock BCL
For example, the rising or falling edge of K is used to synchronize each component unit.

The time slot allocation unit 16A of the arbitration device unit 16 assigns the period TC of one cycle based on this bus clock BCLK.
A time slot signal TSO-TS7 (FIG. 6) is generated having time slots corresponding to 0 and thus 0 for each successive period section of each bus clock BCLK.
Time slots are assigned to the 7th memory banks MBO to MB7, so that data can be written to or read from memory banks MBO to MB7 for each time slot.

Now, suppose that, for example, at time t in FIG. 13, a memory request is issued from the i-th processor Pi to the j-th memory bank MBj. At this time, a memory request signal PiMRQ (FIG. 13(B)) indicating that there is a memory request from the processor Pi to the arbitration device unit 16, and j
Memory bank number signals PiRA1 to piR indicating that the memory location of the th memory bank MBj has been accessed
A block (Fig. 13(C)) is given. These signals are supplied to the i-th decoding means 16B1i of the memory access control unit 16B (FIG. 7), decoded into the memory bank designation signal PRQ+j (FIG. 13(E)), and sent to the j-th memory access means 16B2j. Supplied.

The memory access means 16B2j (FIG. 8) receives this memory bank designation signal PRQ+J in the latch circuit 25 and latches it by a clock φ synchronized with the bus clock BCLK. As a result, the memory bank designation signal PRG
At the time t when the pass clock BCLK rises for the first time after the generation of signal 11j, the latch output φPRQiJ (FIG. 13(F)) is generated from the latch circuit 25.

On the other hand, if the j-th memory bank MBj to which the processor Pi issued a memory request is not performing a memory cycle operation at the time t2 when the latch output 6P■100 occurs, the memory bank MBj sends a request to the arbitration device unit 16. A busy signal BUSYj is given (Fig. 13 (
G)). Therefore, the NAND circuit 27 of the memory access means 16B2j (FIG. 8) has a latch output φp RQL.
, is applied to the NOR circuit 26 with its logic level inverted, a request signal RQ, whose logic level falls (FIG. 13(H)), is obtained at its output terminal, and this is sent to the time slot allocation unit 16A (No. Figure 5).

The time slot allocation unit 16A generates the enable signal ENJ (FIG. 13 (I)) at the timing of the time slot allocated to the j-th memory bank MBj to which the memory request has been issued, as described above with respect to equation (4). Then, this is returned to the NAND circuit 28 of the memory access means 16B2j. Since the request signal RQ is applied to this NAND circuit 28, the output BNO is latched into the latch circuit 29 at the timing of the next clock φ. , Thus, at this timing t3, the latch output enable signal φENj (FIG. 13(J)) is output.

On the other hand, priority selection means 3 for memory access means 16B2j
When the latch output φPRQij (FIG. 13(F)) is applied to the input terminal 1, the priority selection means 31 performs a priority selection operation. If there is no competing memory request for the j-th memory bank MBj, the priority selection means 31 selects the priority selection output φPROi corresponding to the latch output φP RQij.
j (FIG. 13(K)) is applied to the output latch circuit 30.

Therefore, the output latch circuit 30 is the latch output φEN of the latch circuit 29.

(FIG. 13(J)) is generated based on the clock φ, a latch operation is performed simultaneously with the clock φ, and as a result, the occupancy permission signal Pi for the i-th processor Pi
Sends ACK (FIG. 13(M)).

After receiving this occupancy permission signal PiACK, the processor Pi restores the output of the memory bank designation signal PRQij (FIG. 13(E)), and then sends the address data AD to the address data line ADDRESS of the system bus 1.
((0) in FIG. 13). Along with this, when writing data to memory bank MBj that has issued a memory request, processor Pi writes data WD (first
Figure 3 (P)) is connected to the write data line W of system bus 1.
At the same time, the write/read command R/W (FIG. 13(D)) is lowered to the write mode level.

Thus, a state is obtained in which the i-th processor Pi occupies the system bus 1.

In this state, the j-th memory bank MBj receives a bank enable signal BENBj ('tl113 (L)) synchronized with the bus clock BCLK from the arbitration device unit 16.
) is given, the address bus ADDR
The address data AD of the ESS (FIG. 13 (0)) and the write data WD (FIG. 13 (P)) are transferred to the address latch circuit of the memory bank MBj (FIG. 12) at the first rise time t4 of the bus clock BCLK. 47 and the write data latch circuit 49.

When this latched state is obtained, the memory control logic 52 of memory bank MBj generates a row address signal RAS (FIG. 13(R)) and a column address signal CAS (FIG. 13(S)) to the memory area 45. At the same time, the write/read control signal WE (FIG. 13(T)) is lowered to the write mode level. Thus memory bank MB
The write data WD latched by the write data latch circuit 49 is written into the memory location specified by the address data AD latched by the address latch circuit 47 in the memory area 45 of j.

In this way, data transfer and writing to the shared storage device 2 using the system bus 1 is completed based on the memory request PiMRQ (FIG. 13(B)) issued from the i-th processor Pi. become.

FIG. 13 describes the operation in the so-called write mode in which data is written from the i-th processor Pi to the j-th memory bank MBj.
In a so-called read mode in which data stored in the j-th memory bank MBj is read out, data is read out under the control of the arbitration device section 16 as shown in FIG.

As shown in FIG. 14 corresponding to FIG. 13, the arbitration device unit 16 receives a memory request P from the i-th processor Pi.
Based on the fact that the iMRQ (FIG. 14 (B)) has occurred at time t, the memory access means 16B2j (FIG. 8) issues a memory request in the same manner as in the cases of FIGS. 13 (A) to (N). Based on the request signal RQ, the time slot allocation unit 16A (FIG. 5) generates the enable signal TFrj (FIG. 14(I)) in the time slot corresponding to the j-th memory bank MBj. Based on this enable signal 100Nj, the i-th processor P is activated in the memory access means 16B2j.
It gives an occupancy permission signal ACK to i and (
14(M)), the bank enable signal B is generated in the memory bank enable signal generating section 16C (FIG. 11).
ENBJ (FIG. 14(L)) is generated and applied to the j-th memory bank MBj.

As a result, the processor Pi uses the address line ADDRES
Address data AD is sent to S (Fig. 14 (
0)). At this time, memory bank designation data PiRA1 to Pi supplied from the processor Pi to the arbitration device unit 16
RA3 is given to the arbitration device section 16 along with the memory request PiMRQ (FIG. 14(B)). At the same time, the read/write command R/W (FIG. 14(D)) is sent to the system bus 1, so that the bank enable signal BENBJ of the memory bank MBj is given to the arbitration logic 51. The write/read control signal W of the memory control logic 52 is maintained at the read signal level (first
4 (T)), row and column drive signals RAS and CA
S is given to the memory area 45. Therefore memory area 4
5, the data MD stored in the memory location specified by the address data AD latched by the address latch circuit 47 is latched by the read data latch circuit 50.

Data M latched in this read data latch circuit 50
D outputs read data RD (FIG. 14 (U)) to the read data line RDATA of the system bus 1 at the falling timing of the read data output signal RDEN (FIG. 14 (U)) which is separately generated in the memory controller 46.
Q)).

In this way, a state is obtained in which data is read from the j-th memory bank MBj while occupying the system bus 1 based on the data read request from the i-th processor Pi.

In this state, the arbitration device unit 16 sends a strobe signal PiR3TB ((N) in FIG. 14) to the processor Pi.
is sent to notify that the requested data has been sent to system bus 1.

At this time, the processor Pi receives the data MD sent to the system bus 1 at the time T when the bus clock BCLK rises.
When the strobe signal PiR5TB rises at , the signal is taken in at this rising edge.

After the memory request is issued from the processor Pi in this manner, the data read from the memory block MBj can be taken into the processor Pi when a time corresponding to about four cycles of the bus clock BCLK has elapsed.

When there is only one processor that simultaneously requests memory for one memory bank MBj, as in the case of FIGS. Every time a memory request occurs, the arbitration device unit 16 selects the memory bank MB.
Enable signal EN in the time slot assigned to j.

By generating , data is written to or read from the memory location of the specified address according to the content of the memory request. In this way all memory banks M
When non-conflicting memory requests occur for BQ to MB7, data processing according to the contents of the memory request is basically executed using the time slots assigned to each memory bank. (.

On the other hand, in a conflicting state in which memory requests are simultaneously made by multiple processors for one memory bank MBj, and in a state in which there are no memory requests for memory banks MBO to MB7, the arbitration device unit 16 sequentially processes memory requests in order of priority, and at the same time executes data processing using time slots assigned to memory banks to which no memory requests have been issued. For example, as shown in FIG. 15, a memory request PLMR100 whose content is to write data from the i-th processor Pi to the j-th processor MBj at time t 111 (FIG. 15 (B))
occurs, and before the data processing for this memory request is completed, a memory request whose content is to write data from the n-th processor Pn to the j-th memory bank MBj occurs at time 'IIfi. P
Consider the case where nMRi (FIG. 15 (BX)) occurs.

In this case, the (j+3)th memory bank MB(j+3)
It is assumed that there is no memory request from any processor, and therefore the time slot corresponding to the memory bank is empty.

In this state, time t +1! The memory request PiMRQ that occurred at time t117 and the memory request Pn that occurred at time t117
The MRQ is sequentially given to the arbitration device section 16, and decoding means 16B1i and 16BIn are provided corresponding to the i-th and n-th processors Pi and Pn, respectively.
are applied as memory bank designation signals PRQNJ and PRQRJ to the memory access means 16B2j (FIG. 8) corresponding to the j-th memory bank MBj.

First, at time t Ill, the i-th processor Pi
When a memory request for writing data is issued to the jth memory bank MBj, the arbitration unit 16 causes the time slot allocation unit 16A to write data to the jth memory bank MBj in the same manner as described above with reference to FIG. The enable signal EN is generated during the time slot TST assigned to MBj (FIG. 15(1)), and the memory access means 16B is activated based on this enable signal EN.
An occupancy permission signal PiACK is given to the i-th processor Pi from 2j (FIG. 8). At the same time, based on the enable signal ENj, the memory bank enable signal generating section 16C generates the bank enable signal BENB for the j-th memory bank MBj at the time slot TS.
This occurs in the next bus clock cycle of L (FIG. 15(L)).

Therefore, processor Pi sends address data AD, ((0) in FIG. 15) and write data WD to system bus 1.
i (Fig. 15 (P)) and stores it in the memory bank MB.
j latches these data into address latch circuit 47 and write data rack circuit 49 (FIG. 12) at time t14.

A memory request PnMR whose content is that data should be written from processor Pn to memory bank MBj at time jlIn before the data write cycle from processor Pi to memory bank MBj is completed.
When Q (FIG. 15 (B
2j (Fig. 8) from the latch circuit 25 to the priority selection circuit 31
supplied to However, at this time point i+1yi, the latch output φPRQij (FIG. 15(
F)) is given, and the priority selection means 31 has already received this latch output φPRQ! It is in a state where it selects priority i and outputs the corresponding occupancy permission signal PiACK.

In this state, even if at time t11n the latch output φP
The memory request PiMRQ (15th
(B)) disappears and the latch output φP RQij is not supplied to the priority selection circuit 31, the current state is maintained. As a result, data processing based on the memory request PnMRQ (FIG. 15 (BX)) from the processor Pn is performed based on the memory request piM from the processor Pi.
The user will have to wait until the data processing for RQ is completed.

As described above with respect to the priority selection means 31 (FIGS. 9 and 10), this relationship is directly applied even if the priority of the n-th processor Pn is higher than the priority of the i-th processor Pi. This means that even if the memory request is from a low-priority processor, the data processing cycle for the first priority-selected processor is maintained until the processing of that data is completed, thereby ensuring that the data is This is to allow processing to be executed.

In this standby state, the data ADi and WDi latched in the memory bank MBj are sent to the memory area 45 by the row and column designation signals RAS (FIG. 15 (R) and CAS (
15 (S)), and the write/read control signal W100 (Fig. 15
(T)) until the write operation ends at time t's. When writing is completed at time tts, memory bank MBj outputs a busy signal BUSY.
, (FIG. 15(G)), notifies the arbitration device unit 16 that the memory cycle of memory bank MBj has ended.

At this time, the memory access means 16B2 of the arbitration device section 16
j (FIG. 8) is the busy signal BU in the NAND circuit 27.
In response to the change in SYJ, the logic level of request signal RQ (FIG. 15(H)) is lowered. Here, latch circuit 2
5, the latch output φPRQij (FIG. 15 (F)) for the processor Pi whose processing has already been completed is not obtained, but the latch output φPRQ,j (FIG. 15 (FX)) for the processor Pn is not obtained. ) is still available, so the request signal RQ, responds immediately to changes in the busy signal BUSY,.

Thus, when the request signal RQ is generated in the time slot TSa allocated to the (J+3)th memory bank MB (j+3), the time slot allocation unit 1
6A (Figure 5) is the (j+3)th memory bank M
It is determined that the time slot allocated to B(j+3) is in an empty state, and as described above for equation (4), the j-th memory bank MBj is stored at the timing of the empty time slot TS. The enable signal τN is sent out (FIG. 15 (1)).

Therefore, the output latch circuit 30 of the memory access means 16B2j receives the priority selection output φ sent from the priority selection means 31.
latches PROn= and outputs the corresponding priority permission signal P.
Send nACK to the nth processor Pn. At the same time, the enable signal ENJ was obtained again, so
Memory bank enable signal generator 16C (Figure 11)
The bank enable signal BENB from bus clock B
It is transmitted in the next cycle of CLK (FIG. 15(L)).

Therefore, processor Pn uses address data ADn (15th
(0)) and write data WDn (FIG. 15 (P)) are sent to the system bus 1, and the memory bank MBj (12th
) transfers these data to the address data latch circuit 47.
After latching into the write data latch circuit 49, the signal R
Write to the memory area 45 using AS, CAS, and WE.

When the write operation is completed, memory bank MBj inverts the busy signal BUSY to notify arbitration unit 16 that the memory cycle has ended, thus returning to the original state.

In this way, when memory requests from multiple processors occur sequentially for the same memory bank, the arbitration unit 16 sequentially allocates the system bus l and the designated memory bank to each processor in the order in which they occur. Arbitrate such conflicts by granting permission. Then, when data processing for multiple memory requests is sequentially executed, if a time slot other than the time slot allocated to the j-th memory bank MBj for which the memory was requested is free, this free time slot is used. can perform processing on the data.

In the case of Figure 15, we have described the case of arbitrating the conflict when multiple memory requests occur sequentially with a time difference, but if multiple memory requests occur at the same time without a time difference, the memory request is not generated. Among each processor, the one with the highest priority (Fig. 10) is selected by the priority selection means 3.
Conflicts of memory requests are arbitrated in the same manner as in the above case, except that occupancy permission signals are sequentially generated based on the selection at step 1.

In the case of FIG. 15, the content of two competing memory requests is a request to write data to a memory bank, but the content is a request to read data stored in a memory bank. In this case, the arbitration device section 1
6 operates as shown in FIG. In the case of Figure 16,
The difference from the case shown in FIG. 15 is that the reading time when reading data from the memory bank is longer than when writing data.
This is the same as in Figure 5.

That is, in this case, the address data ADi ((0) in FIG. 16) is sent to the system bus 1 by the memory bank enable signal BENBj ((L) in FIG. 16) based on the enable signal 100 Nj generated in the time slot TSi. Then, this is latched by the address latch circuit 47 of memory bank MBj. This latch output is a data latch circuit that reads data stored in the memory area 45 by specifying a corresponding memory location using row and column drive signals RAS and CAS and a write/read control signal WE having a read mode level. 50 and latches.

The latch output is the read data output signal summer DEN (first
6 (U)) to the system bus 1, and thus the read data RDi (FIG. 16 (Q)) corresponding to the memory request from the i-th processor Pi is sent to the system bus 1.
) is output. When memory bank MBj sends data to output bus 1 in this way, at time t
At ts, the busy signal BUSYJ (Figure 16 (G)
) to inform the arbitration unit 16 that the memory cycle has ended by inverting the signal level of
3TB (Fig. 16(N)) is given.

As a result, the processor Pi takes in the data RDi being sent to the system bus 1 at the rising edge of the strobe signal P i R3TB at time t0.

Thus, a memory request P i MRQ from processor Pi
Bus clock BCL K from the time L Il+ is generated
Data can be read from the memory bank MBj to the processor Pi using four periods of time. This data reading time takes a considerable amount of time compared to the data writing time of approximately two cycles in the case of FIG. However, as shown in FIG. 16, even if the time required for the entire read operation becomes longer, the time that bus system 1 is still occupied is one cycle of the bus clock BCLK, so data processing is forced to wait due to contention. Processor Pn
It is possible to effectively avoid the possibility that the system bus 1 becomes a hindrance when the system bus 1 is occupied.

That is, in the case of FIG. 16 as well, the change in the busy signal B U S yj indicating the end of data processing by the processor Pi may occur at the same time tls as in the case of FIG.
In the case of Figure 6, the processing of data by processor Pn is (j+3
)-th memory bank MB(,113) is activated and the enable signal ENj is activated.
(Fig. 16 (■)) can be generated. This enable signal ENj is generated in the arbitration device section 16, and based on this enable signal ENj, the address data ADn based on the memory request of the processor Pn is sent to the system bus 1 in the next cycle of the bus clock BCLK. At the end time tll, the address latch circuit 47 of memory bank MBj latches the address.

However, when the data based on the memory request of the processor Pn is sent to the system bus 1 in this way, the data RDi read from the memory bank MBj based on the memory request of the processor Pi is at the time t.
Since the data has already been taken into the processor Pi at point 0, it is possible to effectively avoid sending two pieces of data onto the system bus 1 at the same time.

After the data stored in the memory location specified by the address data ADn sent onto the system bus 1 is latched into the read data latch circuit 50,
The latch output RDEN (FIG. 16 (U)) is sent onto the system bus 1, and the strobe signal PnR3TB (FIG. 16 (U)) generated in the arbitration device section 16 is sent out to the system bus 1.
The data can be taken into the processor Pn by the rising edge of NX)').

In this way, when the read time in memory bank MBj is long, while the read cycle is being executed in memory bank MBj, at the same time, a signal related to the data to be subsequently processed is generated on the arbitration device section 16 side. Therefore, when these two data are sequentially processed, the time that each data occupies the system bus 1 can be compressed to one cycle of the bus clock BCLK.

In the case of FIG. 16 as well, if two memory requests occur simultaneously without a time difference, the memory access means 1
Based on the priorities assigned to each processor (FIG. 1θ) in the priority selection means 31 of the 6B2j, data is processed in such a way that occupation of the system bus 1 is permitted in order from the processor with the highest priority.

As can be seen in FIGS. 13 to 16, the enable signal EN, occurs in the time slot assigned to the j-th bank, and this enable signal E
N, is generated and the bank enable signal BENB7 is generated in the next time slot. Furthermore, at the point in time when approximately 1.5 time slots have elapsed after the enable signal EN is generated, the address data line ADDRE
At the same time that address data AD is sent to SS, write data WD is sent to write data line WDATA in the write mode.

On the other hand, when approximately two time slots have elapsed after the enable signal EN is generated, the memory bank M
In the read mode, the read data line RDA is activated approximately 2.5 time slots after the enable signal ENj is generated since Bj initiates a data write or read operation (i.e., starts a memory cycle).
The data RD read from the memory bank MBj is sent to the TA, and as a result, the enable signal EN is generated. After approximately three time slots have elapsed, the processor Pi
can take in the data stored in memory bank MBj.

Such an operation is repeated every time the enable signals ENO to 100X for the memory banks MBO to MB7 are generated, whereas the enable signals ENO to EN?
occur sequentially in time slots assigned to memory banks MBO to MB7, respectively. Therefore, address data line ADDRESS, write data line WDA
The timings at which data corresponding to memory buses MBO to MB7 are sent to TA and read data line RDATA are at different timings in the order of the allocated time slots. In this way, even if memory requests occur at conflicting timings for multiple memory banks MBO to MB7, the system bus 1 arbitrates without causing any confusion and ensures that data is sent to the shared storage device 2. can be written or read.

FIG. 17 illustrates this relationship as an arbitration operation when four memory requests are issued simultaneously, as described above with respect to FIG. In this case, as shown in FIG. 17(A), 1
jth memory bank MBj from the th processor Pi
A write request is issued to the nth processor P
A read request is issued from n to the memory bank MBk, a write request is issued from the m-th processor Pm to the X-th memory bank MBx, and a write request is issued from the j-th processor Pr to the y-th Read requests are issued to memory bank MBy, and these requests occur at time t2.
It is assumed that these events occur simultaneously at ゜.

At this time t! I”” L tt%i I! ”' j g
3s j 23~t t4゜tZ4~t□, sequentially j-th, k-th, X-th, y-th time slot TS
Assuming that J5TSh, TSx, and TSy are allocated, as shown in FIG. 17(B), an enable signal 10π1 for the j-th memory bank MBj is generated in the time slot TSJ, and in the following time slot)
The enable signal EN for the Xth memory bank MBK is generated at T S *, the enable signal EN for the Xth memory bank MBx is generated at the following time slot TSx, and the enable signal EN for the Xth memory bank MBx is generated at the following time slot T
An enable signal EN for the y-th memory bank MBY is generated in Sy. In this way, the enable signals 4, EN, SEN, 100XA are sequentially activated in time slots TSj1TSk1TSx, TS,
When the bank enable signals BENBj, BENBm, BENB, , , for each memory bank are generated sequentially with a time difference maintained by the time slot time,
BENB also occurs in a similar manner, with time increasing by one time slot (FIG. 17(C)). Along with this, memory banks MBj, MBk.

Address A D 1 s A for MBXSMBY
As shown in FIG. 17(D), D n sADm and ADr are similarly sent out sequentially to the address data line ADDRESS with a difference of one time slot time.

Thus, a plurality of memory banks MBj, MBk, MBx,
Among the address addresses of MBy, processors pi, Pn, and P
The address addresses specified by ms Pr are sequentially confused (designated,
, MBx, and MBy enter the write or read memory cycle at times shifted by l time slots (FIG. 17(F)). When entering the memory cycle in this way, the processors Pi and Pm that have issued a write request to the memory bank write to the write line at the timing when the address data Al)i and A[)m are sent to the address data line ADDRESS. Write data WDi to WDATA
, WDm (FIG. 17(E)). Therefore, in the memory cycle in memory bank MBjSMBx, write data WDi, WDm are sent as address data ADi, ADm.
, respectively, and the response operations to the memory requests of the processors Pi and Pm are thus completed.

On the other hand, processors Pn, . . . Pr that have issued read requests to memory banks
The stored data is read from the address address corresponding to the address data A D n % A Dr of V, and is sequentially sent to the read data line RDATA (FIG. 17(G)).

This timing is caused by the fact that memory banks MBk and MB3F start their memory cycles at different times based on their assigned time slots, so that they are sent to the read data line RDATA at different times, thus sending a read request from the read data line RDATA. The processor P n sPr that has been configured can take in the data read from the chaotic (memory bus banks MBk, MBY).

In this way, memory banks MBj, MBk, MBx,
Even though the memory cycle of MBy itself is longer than the time slot, the timing of fetching data from the system bus and the timing of sending read data to system bus 1 are executed sequentially at the timing of l time slots. , which has an access time effectively corresponding to one time slot time to the system bus 1, performs the same operation.

Similarly, for the processors P i, Pns Pm, and P r, the timing for sending data to the system bus 1 and the timing for taking in data from the system bus 1 are within one time slot time. Even if you use a device that requires more than one time slot time to send data, and a device that requires more than one time slot time to process the captured data, the system bus 1 will function for l time slots, so even if processor P i
x Pns Pm, data processing time in Pr is 1
Even if it is sufficiently longer than the time slot time, it will function as a device that can respond to the system bus 1 during one time slot time. .

Even if a dynamic memory with a long memory cycle is used as the memory bank and a microprocessor with a slow processing speed is used as the processor,
For system bus 1, it can function as a device that operates in response to successive time slots.
The memory and processor throughput for the entire time slot can be scaled up by the number of memory banks that make up the memory and the number of microprocessors that make up the processor, thus providing data with sufficient data processing capabilities for practical use. A processing device can be obtained.

Therefore, at the timing when data is read from the shared memory bag w2 to the system bus 1, there may be a section in which write data is sent from another processor to the system bus 1 at the same time (for example, at time t25 in FIG. 17), While the read data is sent to the read data line RDATA,
The write data is written on a different write data line DWDA.
Since it is sent to the TA, there is no confusion.

(Other Embodiments) (1) In the above embodiment, all memory banks M
Although a time slot is assigned to BO-MB7, instead of this, a time slot to which no memory bank is assigned may be provided. In this case, the time slot allocation unit 1 of the arbitration device unit 16
In 6A (Fig. 5), for time slots to which the current memory bank has not been assigned, the time slots are allocated by determining this as an empty channel based on the advance function based on equation (4) above. data processing for requests to memory banks that are currently being processed. In this way, it is possible to speed up the processing of a memory request for a memory bank assigned to a time slot following a time slot to which no memory bank is assigned.

(2) In the case of the above embodiment, as is clear from FIG. 1, the devices 5 to 12 assigned to each subsystem are configured to share different tasks, but instead of this, Two or more subsystems may be provided that share the same work. In this way, during the series of data processing steps PRO-PR4 (Fig. 2),
If there is a processing step that requires an extremely large amount of work, the work for that processing step may be shared between two or more subsystems. Therefore, in this case, the data processing time in each processing step can be made to be approximately the same, so when each subsystem processes data in parallel for partitioned data, the data can be processed quickly. It is possible to shorten the time that a completed subsystem waits for the completion of data processing of a subsystem that has not yet completed, and it is possible to increase the throughput of this subsystem.

In addition, because the amount of data processed by some subsystems is extremely large, the processor of that subsystem may have to continue processing data even after the processors of other subsystems have finished processing data. In some cases, the processors of subsystems whose work has been completed may be assigned to handle unfinished work.

In this way, it is possible to effectively utilize a processor that normally stops operating after completing the processing of data assigned to it, thereby shortening the data processing time of a processor with a large workload.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of processors connected to a system bus are assigned tasks, and a shared storage device provided in common to these processors is shared between multiple processors connected to a system bus. It consists of memory banks, and divides the data sent and received between the processor and the memory banks into divided data of a predetermined amount of data, allocates time slots to each memory bank, and requests the unit processing data that constitutes the divided data from the memory. By transferring data using the system bus at the timing of the time slot corresponding to the memory bank specified by You can arbitrate as you can. As a result, even if a general-purpose device whose data processing speed is not very fast is used as a processor and a shared storage device, it is possible to realize a data processing device with a sufficiently large overall throughput, and thus an image processing device with a significantly large amount of data processing can be realized. A data processing device suitable as a means for processing data can be constructed using a general-purpose device without special specifications.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall configuration of a data processing device according to the present invention, Fig. 2 is a route map showing a series of data processing steps to be processed, and Fig. 3 shows data processing steps when performing simultaneous parallel processing. Route map, FIG. 4 is a block diagram showing components related to the system bus in FIG. 1, FIG. 5 is a block diagram showing the detailed configuration of the time slot allocation section 16A in FIG. 4, and FIG. 7 is a block diagram showing the detailed configuration of the memory access control unit 16B of FIG. 4, and FIG. 8 is a signal waveform diagram showing the slot signal.
A block diagram showing a more detailed configuration of the memory access means 16B2j shown in the figure, FIG. 9 is the priority selection means 31 of FIG.
FIG. 11 is a block diagram showing the detailed configuration of the memory bank enable signal generator 16G in FIG. FIGS. 13 to 16 are signal waveform diagrams showing signals of each part, and FIG. 17 is a route diagram showing a data processing procedure in simultaneous parallel processing. ■...System bus, 2...Shared storage device, 5...File storage device, 6...
・Data transmission device, 7... Image reading/printing device, 8... Image information compression/expansion device, 9...
...Operation display device, 10...Main control device, 16
... Arbitration device section, 16A ... Time slot allocation section, 16B ... Memory access control section, 16C ... Memory bank enable signal generation section, PO- P7...Processor, M
BO~MB7...Memory bank. Vines 6 Arts lO diagram

Claims (1)

[Scope of Claims] 1. Data input means for inputting data, display means for displaying the input data or processed data, and file storage means for storing the input data or processed data. , a data processing apparatus that has at least a shared storage means coupled to each of the above means via a system bus, and executes data processing specified by the data input means, comprising: a. Each of the above means is coupled to the system bus; It has a processor that has been done, shares the work on the above data processing, and the work that is assigned to the assigned work is combined with the above -mentioned processor, and the above -mentioned system buses are combined, and the above -mentioned shared memories. a plurality of memory banks constituting the means; c. when a processor of each of the above subsystems issues a memory request specifying one of the above memory banks to send and receive data through the system bus; , an arbitration device section that generates an enable signal that allows the respective designated memory banks to be occupied in response to each of the memory requests; In addition to dividing the data into divided data of the amount of data, time slots formed to be synchronized with the bus clock of the above system bus are assigned to each of the plurality of memory banks, and unit processing data making up the above divided data is requested from the memory. Processing of data regarding memory requests simultaneously issued by the plurality of processors is performed by transferring data via the system bus at the timing of the time slot allocated to the memory bank specified by the system bus. 1. A data processing device characterized in that the data processing apparatus executes the processing in parallel simultaneously for each of the partitioned data in synchronization with the bus clock of the data processing apparatus. 2. The data processing device according to claim 1, wherein the plurality of subsystems include two or more subsystems that share the same work with each other. 3. The system bus includes an address bus that transfers address data specifying the address of the memory location in the memory bank where the memory request was issued, and a write bus that transfers address data that specifies the address of the memory location in the memory bank where the memory request was issued, and a write that is to be written to the memory location specified by the address data. The data processing device according to claim 1, comprising a write data bus for transferring data and a read data bus for transferring read data read from a memory location specified by the address data. . 4. The data processing device according to claim 1, wherein the processor is a microprocessor. 5. The data processing device according to claim 1, wherein the memory bank is constituted by a dynamic RAM. 6. The data processing device according to claim 1, wherein the time slot is selected to be shorter than a memory cycle required when the memory bank writes or reads data. 7. Claim 1, wherein the time slot is selected to be shorter than the data processing time required when the processor internally processes data read out via the system bus. The data processing device described in .