JPH0542703B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a data processing device, for example, a document processing device,
It is suitable for application when processing information (hereinafter referred to as image information) made up of digital data representing an image composed of images and characters such as characters, such as drawings. . [Prior Art] The scope of application of data processing devices for this type of image information is expanding, and if document creation, electronic files, mutual communication, etc. can be easily and inexpensively constructed as a series of systems, office automation will be possible. It is believed that the present invention can provide a data processing device useful for general office processing operations in fields such as Office Automation, Future of the Office, and Paperless Office. However, this type of image information requires approximately 100 times more processing time than processing general data encoded in a predetermined code (for example, in the case of numerical calculations, data processing, word processing, etc.). It contains a large amount of information. Therefore, when digitally processing image information, it is necessary to use a machine with a throughput that is 100 times or more greater than when processing general data. Therefore, in the past, in addition to using a dedicated processor, dedicated hardware logic, or large-scale computer designed with special specifications to be able to process large amounts of data, data was compressed to reduce the amount of processing. Methods are adopted to reduce the burden on the machine. [Problems to be solved by the invention] However, when using this conventional method, it is inevitable that the overall structure of the data processing device becomes large and complicated, and moreover, it is necessary to use specially designed and expensive equipment. There is a problem that cannot be solved. In order to solve this problem, it is possible to process image information using general-purpose devices such as personal computers, mini-computers, and office computers, but these general-purpose devices are not capable of processing large amounts of data. These general-purpose devices are not configured, their processing speed is slow, and they do not have the processing power to perform a variety of tasks independently, so even if you simply use the functions of these general-purpose devices, you will not be able to process large amounts of data. It cannot be processed in a short period of time. The present invention has been made in consideration of the above points, and
When processing image information, the processing speed itself
A large number of general-purpose microprocessors, memories, and other devices with low processing power are used to connect them to each other via a system bus, and an arbitration function is provided to execute data processing in each device simultaneously and in parallel. By doing so, we aim to propose a data processing device that has a practically sufficient execution processing speed. [Means for solving the problem] In order to solve the problem, the present invention provides data input means 9B, 9 for inputting data.
C, 7F, display means 9J, 9K for displaying input data or processed data, file storage means 5 for storing input data or processed data, each of these means, and system bus 1. In a data processing apparatus that has at least a shared storage means 2 coupled via a data input means 9B, 9C, and 7F, and executes data processing specified by the data input means 9B, 9C, and 7F, the data processing work is performed by a plurality of subsystems. 5 to 12, each subsystem 5 to 12 executes its assigned task using processors P0 to P7 respectively coupled to the system bus 1, and the shared storage means 2 is connected to the system bus 1, respectively. The processors P0 to MB7 of each subsystem 5 to 12 are connected to a plurality of memory banks MB0 to MB7.
When P7 specifies one of the memory banks MB0 to MB7 and issues a memory request indicating that data should be sent and received via the system bus 1, the arbitration device unit 16 selects one of the memory banks MB0 to MB7. The arbitration unit 16 generates an enable signal for allowing the processors P0 to P7 to occupy the processors P0 to P7.
It divides data sent and received between memory banks MB0 to MB7 into segmented data of a predetermined amount of data, and synchronizes data processing for memory requests issued simultaneously from multiple processors P0 to P7 with the bus clock of system bus 1. At the same time, each partitioned data is executed simultaneously and in parallel. In addition, the arbitration device section 16 divides the data transmitted and received between the processors P0 to P7 and the memory banks MB0 to MB7 into divided data of a predetermined amount of data, and also divides the data transmitted and received between the processors P0 to P7 and the memory banks MB0 to MB7 into divided data of a predetermined amount. Allocate time slots formed to be synchronized, and transfer unit processing data constituting the partitioned data via the system bus 1 at the timing of the time slot allocated to the memory bank specified by the memory request. This enables simultaneous and parallel data processing. [Operation] The data processing device divides the data to be processed into partitioned data of a predetermined amount of data based on memory requests from each processor, and processes the data corresponding to each memory request for each partitioned data. They are executed simultaneously and in parallel while synchronizing with the bus clock of the system bus. In this way, when memory requests from each processor occur sequentially, it is possible to process each piece of partitioned data without processing all the data for each memory request at once. The process can now be executed. As a result, most of the data processing corresponding to all memory requests can be performed during the time TZ0 (Figure 3) during which the processing of partitioned data for multiple memory requests issued at the same time is being executed simultaneously. As a result, the overall processing time can be significantly shortened. Therefore, even if general-purpose devices with small throughput are used as the processor and memory bank, all the data can be processed in a sufficiently fast execution time for practical use. Therefore, when processing data that includes non-coded data such as image data, by using multiple general-purpose devices, it is possible to create a data processing device that has a throughput comparable to that of using a dedicated computer, for example. can be easily constructed. For this reason, in particular, in the present invention, memory requests for a plurality of memory banks MB0 to MB7 are handled by assigning to each memory bank a time slot formed to be synchronized with the bus clock.
When transferring data between the processor and the memory bank, the data is transferred using the system bus at the timing of the time slot assigned to the memory bank that issued the memory request, so that data can be transferred at the same time. System bus occupancy requests can be effectively arbitrated based on each memory request made, thus ensuring simultaneous parallel processing of competing data. [Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings. (Overall Configuration) As shown in FIG. 1, the data processing device has a system bus 1 coupled to eight subsystems that each share the work of a series of data processing steps to be executed sequentially.
It is coupled to a shared storage 2 shared by each subsystem. The shared storage device 2 consists of a board 2A equipped with a bus and memory controller (MBC), and two boards each equipped with a RAM having a storage capacity of 2 mega bytes (hereinafter referred to as MB). When a memory request arrives from each subsystem via the system bus 1, the bus and memory controller (MBC) transfers the corresponding data to the board 2 via the local bus 2D.
It is configured to read from or write to RAM B and 2C. In particular, when memory requests from each subsystem conflict, the bus and memory controller (MBC) arbitrates this conflict and thus allows data to be processed in parallel. , has the ability to respond to requests from all subsystems within a short period of time. The system bus 1 is connected to processors (CPU) P0 to P7 provided in each subsystem.
Each processor P0-P7 is shared by all the processors P0-P7 in order to exchange signals and data between the bus of the shared storage device 2 and the memory controller (MBC). A file storage device (STS) 5 is assigned to the first subsystem, and a processor P0 having a data processing speed of 2 [MB/sec] is connected to the system bus 1. Processor P0 is mounted on board 5A, and is a DRAW processor that constitutes a storage device for filing data from the data processing device.
(Direct Read after Write) 5B and TDD
(Hard Disk Drive) File data can be stored in or read from the 5C. In this embodiment, an interface (DRAW I/F) for DRAW5B is provided on board 5A, and board 5D, which is equipped with an interface (HDD I/F) for HDD5C, is connected to processor P0 via local bus 5E. combined. Thus, processor P0 uses shared storage device 2
data is stored in HDD5C or DRAW5B using system bus 1, and
The data of DRAW 5B is transferred to the shared storage device 2 using the system bus 1. In addition, a data transmission device (NTS) 6 is assigned to the second subsystem, and two
A processor P1 having a data processing speed of [MB/sec] is connected. The processor P1 is mounted on the board 6A together with a transmission control circuit (Ethernet Controller), and transmits data from the system bus 1 via the transmission device 6B to the transmission line 6C made of a coaxial cable.
Data arriving via C can be taken into the system bus 1 side. Thus, the processor P1 sends data in the shared storage device 2 to the transmission device 6B using the system bus 1, or sends data arriving from the outside via the transmission device 6B to the shared storage device 2 using the system bus 1. Incorporate into. As a result, by connecting the data processing device to an external device, it is now possible to construct an even larger scale data processing system. An image reading/printing device (IDS) 7 is assigned to the third subsystem, and two
Processor P2 with a processing speed of [MB/sec]
is connected. The processor P2 is mounted on the board 7A together with an image input/output controller (Image I/O Controller), and under the control of this image input/output controller, each image printer interface (IP
It is coupled to an image printer (IP) 7E and an image reader (IR) 7F via an image reader interface (IR I/F) board 7C and an image reader interface (IR I/F) board 7D, respectively. Thus, the processor P2 reads the image data read by the image reader 7F into the shared storage device 2 using the system bus 1, and prints the data in the shared storage device 2 via the system bus 1 on the image printer 7E. being done. An image information compression/decompression device (CDS) 8 is assigned to the fourth subsystem, and a processor P3 having a data processing speed of 2 [MB/sec] is connected to the system bus 1. Processor P3 is a compression/decompression controller (Compress/Decompress).
It reads the data of the shared storage device 2 using the system bus 1, and sends this data to the compression processing circuit (COMP) board 8C and the compression processing circuit (COMP) board 8A through the local bus 8B.
Alternatively, the data is transferred to the board 8D of the decompression processing circuit (DECOMP), and the compressed or decompressed data is sent to the shared storage device 2 using the system bus 1. The image information compression/expansion device 8 is the file storage device 5
Data to be stored on HDD 5C or DRAW 5B of MH method (Modified Huffman) or
The amount of stored data can be expanded by pre-compression processing using the MR method (Modified READ), and the compressed data read from HDD5C or DRAW5B can be decompressed for display, printing, and transmission processing. . The fifth subsystem is a control display system (DPS).
A processor P4 having a data processing speed of 2.5 [MB/sec] is connected to the system bus 1. The board 9A on which the processor P4 is mounted includes a ROM and a ROM that store processing programs and data used to convert image data read by the processor P4 into video display signals.
RAM is installed. Further, the operation display device 9 has a keyboard 9B and a mouse 9C as operation input means, and inputs and outputs data from the keyboard 9B and mouse 9C to the processor P4 through a serial input circuit (S I/O) mounted on the board 9A. It has been made possible. Here, the data inputted from the keyboard 9B and the mouse 9C are encoded data each having a predetermined format, and the data input from the processor P
4 can transfer this input data (for example, character data or command data consisting of characters, symbols, etc.) to the shared storage device 2 using the system bus 1 . On the other hand, when displaying image data (that is, data representing an image, a character, or a mixture of an image and a character), the processor P4 sends these data to the bitmap controller BMC of the board 9E via the local bus 9D. as commands and data. Here, the processor P4 transfers the coded character data as a command to the bit map controller (BMC) to convert it into corresponding font data, and then transfers it to the video memory (VRAM) via the local bus 9F. Boards 9G and 9
The data is transferred to H and developed on a two-dimensional screen memory. On the other hand, the image data generated in the image data 7F is non-coded data that directly represents black and white pixels, and when displaying this, the processor P4 performs the same processing as it does for coded character data. The image is expanded as is on the two-dimensional screen memory without any conversion. The image data developed on the VRAM in this way is read out via the local bus 9F by a timing circuit (TIM) mounted on the board 9I and displayed on displays 9J and 9K made of cathode ray tubes (CRTs), for example. will be displayed. In addition to the above functions, the processor P4 reads image data from the shared storage device 2 via the system bus 1, assembles and edits it on one screen, and also displays characters input from the keyboard 9B on one screen. Has the ability to insert. Processor P4 is
The processing data for this assembly/editing is CRT9J, 9
The data that has been assembled and edited is transferred to the shared storage device 2 via the system bus 1. In this way, the operation display device 9 assembles and edits the image data read out from the file storage device 5 to the shared storage device 2 into a single screen according to the operations of the keyboard 9B and mouse 9C as operation input means. The data is displayed on the display 9J or 9K and transferred to the shared storage device 2 using the system bus 1. This data is stored in the file storage device 5, printed by the image printer 7E of the image reading and printing device 7, or transmitted from the data transmission device 6 to the outside. The sixth subsystem includes a main controller (PCS) 1
A processor P5 is connected to the system bus 1 and has a data processing speed of 2.5 [MB/sec]. The board 10A on which the processor P5 is mounted is connected to the RAM of the board 10C and the input device I/O of the board 10D via the local bus 10B, and is connected to the local memory via the I/O from the floppy disk drive (FDD). Each subsystem coupled to the system bus 1 and the shared storage device 2 are controlled as a whole by a system operation program (operating system, application program, etc.) written in the RAM as the system bus. Interrupt and attention signals for such control are provided on control signal line 3.
The information is transmitted and received between the main control device 10 and all subsystems via. In addition, processor P5 is the RAM of board 10C.
The image printer 7
At step E, assembly processing of image data to be printed is executed. The seventh and eighth subsystems have spare equipment 11
and 12 are assigned (that processor is assigned P6
and P7). This allows new functions to be added. In the configuration shown in FIG. 1, the operator can use the keyboard 9B and mouse 9C of the operation display device 9 to input commands for specifying modes and character data such as letters and symbols, and can also input character data such as pictures and characters. Image data can be input using the image reader 7F of the image reading and printing device 7.
Here, the data input from the keyboard 9B and mouse 9C are obtained as data having predetermined codes that are easy to transfer and process, and therefore character data can be input with a relatively small amount of data. In contrast, the image reader 7 of the image reading and printing device 9
Since the image data inputted from F is composed of data representing black and white of each pixel using a binary code, the amount of data becomes significantly large. Data input from the keyboard 9B or mouse 9C is once written to the shared storage device 2 from the processor P4 of the operation display device 9 using the system bus 1, and then transferred to the image information compression/decompression device 8 via the system bus 1 again. The data is transferred and compressed. The thus processed data is transferred to the shared storage device 2 using the system bus 1 again.
Thereafter, this data is again transferred to the file storage device 5 using the system bus 1 and stored in the HDD 5C or DRAW 5B as an external storage device. Similarly, image data input from the image reading/printing device 7 is once imported into the shared storage device 2 using the system bus 1, and then transferred to the image information compression/expansion device 8 using the system bus 1 again. After being compressed, the data is transferred to the shared storage device 2 using the system bus 1 again, and then transferred to the file storage device 5 using the system bus 1 again and stored in the HDD 5C or DRAW 5B. In this way, data compressed by the image information compression/expansion device 8 is stored in the HDD 5C and DRAW 5B. is output to.
In this case, the data on HDD5C or DRAW5B is
Keyboard 9B or mouse 9C of operation display device 9
of the file storage device 5 based on data from
After transferring the accumulated data of HDD5C and DRAW5B to shared storage device 2 using system bus 1,
Using the system bus 1 again, the data is transferred to the image information compression/expansion device 8 for decompression processing. The resulting data is transferred to the shared storage device 2 using the system bus 1 again, and then transferred to the display 9J of the operation display device 9 using the system bus 1 again.
9K or displayed or printed on the image printer 7E of the image reading and printing device 7. At this time, the screen assembly for the image signals supplied to the displays 9J and 9K is executed by the processor P4 of the operation display device 9, and the screen assembly for the image signals supplied to the printer 7E is executed by the main controller 10. It is executed in processor P5. Furthermore, in a mode in which data stored in the file storage device 5 is edited again or characters are newly inserted into an image input from the keyboard 9B or image reader 7F, each data is temporarily transferred to the shared storage device 2. After that, the processor P4 edits the data in the same manner. In this way, the data processing device of FIG.
Operating program (i.e. operating system or application program) input from the floppy disk drive FDD into RAM
The main controller 1 in each operation mode based on
Data processing is executed under the control of 0. When executing this data processing, each subsystem uses the system bus 1 for the shared storage device 2.
The shared storage device 2 is accessed while being shared. At this time, the shared storage device 2 needs to occupy the shared storage device 2 and the system bus based on a memory request issued by one subsystem until processing of data based on the memory request is completed. However, if this occupation time is too long, data based on memory requests issued by other subsystems must be processed again for a long period of time. To solve this problem, the shared storage device 2
The bus and memory controller (MBC) is configured to have an arbitration function that simultaneously handles the supply of data from each subsystem's processor in parallel, thus processing a series of sequential data as described below. The processing time can be significantly reduced compared to the case where the processing is executed in a time-series manner. In the following description, when a bar is attached to the symbol of a signal or data, it is assumed that the symbol is expressed based on negative logic. Now, for example, when image data (compressed) stored in the HDD 5C and DRAW 5 as external storage devices of the file storage device 5 is to be displayed on the displays 9J and 9K of the operation display device 9, The series of data processing shown in FIG. 2 is performed sequentially. That is, in the 0th data processing step PR0, image data to be read out from the HDD 5C or DRAW 5B of the file storage device 5 is logically searched under the control of the main controller 10. In the following first data processing step PR1, the retrieved data is read from the file storage device 5 and transferred to the shared storage device 2. Next 2
In the second data processing step PR2, the data transferred to the shared storage device 2 is read out by the processor P3 of the image information compression/decompression device 8, decompressed and then rewritten to the shared storage device 2. Next, in the third data processing step PR3, the processor P4 of the operation display device 9 reads out the data rewritten to the shared storage device 2, and after performing processing such as editing and assembling the screen and inserting characters, the data is rewritten to the shared storage device 2. Store it again in 2. Next, the fourth data processing step PR4
The operation display device 9 reads out the data stored in the shared storage device 2 again and displays it on the displays 9J and 9K via the bitmap controller 9E and VRAM 9G and 9H. In these series of data processing steps,
The steps for transferring data using system bus 1 are the first to fourth data processing steps PR1.
~PR4, which is a processing time T determined based on the data processing speed of the processor that processes data in each step and the amount of data processed.
A total processing time of 1 to T4 is required. That is, in data processing step PR1,
HDD5C or DRAW5B of file storage device 5
Data read from the processor P0 is transferred to the shared storage device 2 during a time T1 at a data processing speed of 2 [MB/sec] of the processor P0. In the second data processing step PR2, the processor P3 of the image information compression/decompression device 8 reads the data from the shared storage device 2 at a data processing speed of 2 [MB/sec], and reads the decompressed data. Processor P3 again stores the data in shared storage device 2 at a data processing speed of 2 [MB/sec], thus processing time T2
Requires. Also, the third data processing step
In PR3, the processor P4 of the operation display device 9
After reading the data from the shared storage device 2 at a data processing speed of 2.5 [MB/sec], editing processing such as assembling the screen and inserting characters is executed, and then the processor P4
The edited data is stored in the shared storage device 2 again at a data processing speed of 2.5 [MB/sec], and a time T3 is required for such data processing. Further, in the fourth data processing step PR4, the processor P4 of the operation display device 9 has a data processing speed of 2.5.
It takes time T4 to read data from the shared storage device 2 at a speed of [MB/sec] and display it on the displays 9J and 9K, and to execute such data processing.
Requires. Therefore, in the data processing apparatus having the configuration shown in FIG. 1, if the series of data processing steps shown in FIG. 2 are executed sequentially and in time series,
Total processing time required to process the data
TSMI is TSMI=T1+T2+T3+T4...(1). In principle, the present invention divides the work of this amount of data into predetermined data segments (for example, about 16 [kB] or 8 [kB] (KB = kilobyte)), and uses multiple processors to simultaneously and 1 in parallel
Process data piece by piece. In other words, the series of data processing steps shown in Figure 2
The data to be processed in each of PR1 to PR4 is divided into multiple sections (7 sections in the case shown) as shown in Figure 3, and each section of data is sequentially and simultaneously parallelized for each section data processing execution time TU1 to TU10. We will process it accordingly. In FIG. 3A, the processor P0 reads out one sector or one track from the file storage device 5 as the first segmented data to be processed in the data processing step PR1 of FIG. It is transferred to the shared storage device 2 during processing step PR11. As shown in Figure 3B, this first segment data is used for the next processing execution time.
During TU2, the data processing step PR2 in Figure 2
Processing step PR21 as the first processing data of
The image data is processed by the processor P3 of the image information compression/expansion device 8, read out from the shared storage device 2, decompressed, and then stored again in the shared storage device 2. As shown in FIG. 3C, this re-stored first classified data is processed in processing step PR31 of processing execution time TU3 as the first processing data of data processing step PR3 in FIG. That is, the processor P4 reads the segmented data from the shared storage device 2, performs editing processing, and then stores it again in the shared storage device 2. As shown in FIG. 3D, this re-stored first classified data is processed in data processing step PR41 at processing execution time TU4 as the first processing data of data processing step PR4 in FIG. As a result, the partitioned data in the shared storage device 2 is read out by the processor P4 and displayed on the displays 9J and 9K. Thus, the first partitioned data is the processing execution time.
Data processing steps PR11, PR21, PR31, and PR41 are sequentially processed during TU1, TU2, TU3, and TU4. During this period, the second processing execution time TU2
, the processor P0 of the file storage device 5
reads the second segmented data from the external storage device and stores it in the shared storage device 2 in data processing step PR12. This second segmented data is
In the same manner as in the case of the first partitioned data, data is processed in data processing steps PR22, PR32, PR42 each time the processing execution times TU3, TU4, and TU5 successively continue, and as a result, the display 9J is displayed at processing execution time TU5. , 9K. Thereafter, in the same manner, the 3rd, 4th, etc. classification data are sequentially read out from the file storage device 5 at processing execution times TU3, TU4... Processing execution time TU4, TU5, TU6, TU5, TU
6, TU7..., sequential processing steps (PR23, PR33, PR43), (PR24, PR34,
The data is processed in PR44), . . . and sequentially displayed on the displays 9J and 9K. In this way, the data processing steps in FIG.
The data to be processed in PR1, PR2, PR3, and PR4 is processed sequentially at each partitioned data processing execution time in which each partitioned data is read sequentially, but each sequential process is executed simultaneously and in parallel. This is called pipeline processing).
As a result, during the execution time of partitioned data processing, the processors that are assigned the work of each processing step will perform data processing operations simultaneously and in parallel. This improves the performance and therefore reduces the data summation processing time. Such a result can be obtained because if the data processing steps PR1 to PR4 are processed sequentially and in time series as described above with reference to FIG. While the assigned processor is processing data, other processors are not processing data and are waiting for commands to arrive, resulting in this wasted time. Although the overall data processing time is considered to be long, the method shown in FIG. 3 can significantly reduce this wasted time. After all, if the data processing method according to the present invention shown in FIG.
The work for each processor is calculated so that the sum of the time TZ0 in which the data processing steps in ~P4 overlap and the non-overlapping times TZ1 and TZ2 that occur before and after that is small, and the non-overlapping time becomes small. By doing so, the overall data processing time can be significantly shortened compared to the case of FIG. 2. For example, as shown in FIGS. 3A to 3D, if the execution time for segmented data processing in each processing step is made equal to each other, the data summation processing time
TSM2 can be expressed as TSM2=[K+(DSP-1)]×TU...(2). Here, K is the number of partitioned data in each partitioned data processing step, DSP is the number of programs to be processed simultaneously (ie, the number of processing steps PR1 to PR4 in FIG. 2), and TU is the processing execution time of the partitioned data. Therefore, according to the configuration shown in Figure 1, even if a general-purpose microprocessor whose data processing speed is not very fast is used as a processor, the data total processing time for the data processing device as a whole is significantly larger than the amount of data. A data processing device with a practically sufficient throughput suitable for processing image data can be realized. Simultaneous parallel processing of partitioned data in the configuration shown in FIG.
This is achieved by processing contention among the processors of the subsystems connected to the system bus 1 simultaneously and in parallel. (Shared Storage Device) The shared storage device 2, as shown in FIG.
1, P2...P7 (this is Pi, i=0, 1, 2...
... 7) coupled to the system bus 1;
By controlling the memory section 15 composed of RAMs 2B and 2C (FIG. 1) by the arbitration device section 16, it is possible to decide which subsystem's processor should exclusively use the system bus 1. being done. In this embodiment, the system bus 1 includes a 20-bit address data line ADDRESS, a 16-bit read data line RDATA, a 16-bit write data line WDATA, and a read/write command R/high byte or low byte selection signal. ，
It consists of a 3-bit bus that transfers UDS,
It is terminated by a terminal end 17. The memory unit 15 includes eight memory banks MB0, each having a memory capacity of 250 [kiloward].
MB1...MB7 (MBj, j=0, 1, 2
...7), and by connecting system bus 1 to each memory bank MB0 to MB7, each processor P0
~P7 can access each memory bank separately. By doing this, one memory bank performs data writing and reading operations. (This is called a memory cycle)
Other memory banks can be accessed in between. The system bus 1 is coupled to an arbitration device section 16 and is connected to eight subsystem processors P0 to P7.
When conflicting memory requests are issued to the system bus 1 and thus the memory unit 15 from the system bus 1 and thus the memory unit 15, by arbitrating these requests using the configuration shown in FIGS. 5 to 7, all memory requests can be satisfied. To enable data processing to be executed simultaneously and in parallel. Here, the content of the memory request sent from each processor is either writing data to the shared storage device 2 or reading data stored in the shared storage device 2. The arbitration device section 16 performs two arbitration tasks. Its first mission is to operate eight processors Pi (i
=0, 1, 2...7) respectively from the memory section 15.
Memory bank that should be granted occupancy for this request when memory requests for are issued at the same time.
It is to allocate MBj (j=0, 1, 2...7). The second mission of the arbitration unit 16 is to arbitrate which processor Pi is allowed to occupy the same memory bank MBj when memory requests are issued from a plurality of processors Pi. The arbitration device section 16 has a time slot allocation section 16A (FIG. 5) that performs a first task. This time slot allocating section 16A is shown in FIG.
As shown in the figure, eight time slot signals TS ₀ to TS ₇ (denoted as TS _j , j=1, 2...7) corresponding to memory banks MB0 to MB7 are sequentially and cyclically generated, and each time slot signal is The falling sections (this is called a time slot) of the lot signals TS ₀ -TS ₇ are sequentially assigned to the processors P 0 -P 7 of the subsystem. Here, the time slot section of each time slot signal TS ₀ to _{TS 7} is selected as the processing time of unit data (for example, 1 [ward]) that is actually processed sequentially, and therefore the repetition period of each time slot is , processing execution time required to process partitioned data
The value is selected to be sufficiently short compared to TU1 to TU10 (Fig. 3). In this way, the divided data is actually processed in units of many units of data. Thus, the time slot signals TS ₀ , TS ₁ , TS ₂
...During the time slot of TS ₇ , memory requests ₀ , ₁ , ₂ ... ₇ (this is _{called j}
，
j = 0, 1, 2...7), the processor P of the subsystem that issued the request
An enable signal indicating that memory banks MB0, MB1, MB2, .
₀ , ₁ , ₂ ... ₇ (represent this as _j , j=0,
1, 2...7) are generated. Therefore, when the memory requests of the processors P0 to P7 do not conflict, the arbitration device unit 16 selects the memory banks MB0 to MB0 to
When a memory request is made for one of the MBs 7, it has a function (this is called a time slot allocation function) that unconditionally uses the time slot corresponding to the memory bank to process the memory request. In addition, when no corresponding memory request is generated in each time slot of the time slot signal TS _j (j=0, 1...7), the arbitration device section 16 selects the time slot for which there is no memory request. It has a function that can be used to process memory requests for memory banks allocated to other time slots (this is called a time slot utilization function). The above relationship can be expressed as follows. ₇ 〓 ^j=0 TS _j =1 ...(3) EN _j = TS _j + _j-1・EN _j-1 ...(4) Here, TS _j is the jth (j=0, 1, ...7 ), _j is the request signal for the jth memory bank MBj, and EN _j is the jth memory bank MBj.
Each shows an enable signal indicating that MBj can be occupied. Here, equation (3) is expressed as the time slot signal TS _j (j=
0 to 7) indicate that time slots are generated sequentially and cyclically. On the other hand, in equation (4), since the enable signal EN _j for the j-th memory bank MBj is generated, first, it must be the timing of the time slot of the time slot signal TS _j assigned to the memory bank MBj. (the first term TS _j ), and the second term is 1
The previous (j-1)th memory bank MB (j-
Request signal RQ _j-1 is not generated in the time slot corresponding to 1), and the memory bank MB (j-1) corresponding to the time slot is not generated.
1) is not used (second term RQ _j-1・EN _j-1 ). In this way, while a memory request is issued for the jth memory bank MBj, a memory request is issued for the memory bank MB(j-1) corresponding to the previous (j-1)th time slot. If no memory request has been issued, the previous time slot can be used to process the request for the jth memory bank MBj. This also applies to the sequential previous one (i.e. (j
-2)th, (j-3)th...), when there is no memory request for the (j-2)th, (j-3)th... memory bank MB(j-2). , MB(j-3) . . . (this is called an advance effect). The relationship of this equation (4) is calculated for each memory bank MB0 to MB.
If this is expressed as enable signals EN ₁ to EN ₇ for EN 7, it will be as follows.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of processors connected to a system bus are assigned tasks, and a shared storage device provided in common to these processors is shared by a plurality of processors connected to a system bus. It consists of a memory bank, and divides the data sent and received between the processor and the memory bank into divided data of a predetermined amount of data,
A time slot is assigned to each memory bank, and the unit processing data constituting the partitioned data is transferred using the system bus at the timing of the time slot corresponding to the memory bank specified by the memory request. By doing so, it is possible to arbitrate memory requests simultaneously issued from each processor so that each memory bank can be occupied simultaneously and in parallel. As a result, even if a general-purpose device whose data processing speed is not very fast is used as a processor and a shared storage device, a data processing device with a sufficiently large overall throughput can be realized, and thus an image processing device with a significantly large amount of data processing can be realized. A data processing device suitable as a means for processing data can be constructed using a general-purpose device without special specifications.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a data processing device according to the present invention, FIG. 2 is a schematic diagram showing a series of data processing steps to be processed, and FIG. 3 is a diagram showing data processing steps for simultaneous and parallel processing. 4 is a block diagram showing the components related to the system bus in FIG. 1, FIG. 5 is a block diagram showing the detailed configuration of the time slot allocation section 16A in FIG. 4, and FIG. A signal waveform diagram showing the time slot signal; FIG. 7 is a block diagram showing the detailed configuration of the memory access control section 16B in FIG. 4;
FIG. 8 shows the memory access means 16B2j of FIG.
9 is a block diagram showing a detailed structure of the priority selection means 31 of FIG. 8, FIG. 10 is a chart for explaining the priority order, and FIG. 12 is a block diagram showing the detailed configuration of the memory bank MBj in FIG. 4, and FIGS. 13 to 16 are signal waveforms showing the signals of each part. FIG. 17 is a schematic diagram showing a data processing procedure when performing simultaneous parallel processing. 1...System bus, 2...Shared storage device, 5
...File storage device, 6...Data transmission device,
7... Image reading and printing device, 8... Image information compression/expansion device, 9... Operation display device, 10... Main control device, 16... Arbitration device section, 16A... Time slot allocation section, 16B... Memory Access control section, 16C...Memory bank enable signal generation section, P0 to P7...Processor, MB0
~MB7...Memory bank.

Claims (1)

[Scope of Claims] 1. A data input means for inputting data, a display means for displaying the input data or processed data, and a file storage means for accumulating the input data or processed data. In a data processing device that has at least a shared storage means coupled to each of the above means via a system bus, and executes data processing designated by the data input means, a. a plurality of subsystems each having a processor, each of which shares the task of the data processing, and each executes the divided task using the processor; c. When a processor of each of the above-mentioned subsystems issues a memory request specifying one of the above-mentioned memory banks to transmit/receive data through the system bus, each of the above-mentioned memories an arbitration device section that generates an enable signal that allows the occupancy of the respective designated memory banks in response to a request; At the same time, time slots formed to be synchronized with the bus clock of the system bus are allocated to each of the plurality of memory banks, and unit processing data constituting the divided data is specified by a memory request. By transferring the data via the system bus at the timing of the time slot assigned to the memory bank, the processing of data for memory requests simultaneously issued by the plurality of processors is synchronized with the bus clock of the system bus. While
A data processing device characterized in that the processing is executed simultaneously and in parallel for each of the above-mentioned partitioned data. 2. The data processing device according to claim 1, wherein the plurality of subsystems include two or more subsystems that share the same work with each other. 3. The system bus is an address bus that transfers address data specifying the address of the memory location of the memory bank to which the memory request has been issued;
a write data bus that transfers write data to be written to the memory location specified by the address data; a read data bus that transfers read data read from the memory location specified by the address data; Claim 1 comprising:
The data processing device described in section. 4. The data processing device according to claim 1, wherein the processor is a microprocessor. 5. The data processing device according to claim 1, wherein the memory bank is composed of a dynamic RAM. 6. The data processing device according to claim 1, wherein the time slot is selected to be shorter than a memory cycle required when the memory bank writes or reads data. 7. According to claim 1, the time slot is selected to be shorter than the data processing time required when the processor internally processes data read out via the system bus. The data processing device described.