JPS61150049A - Information processing unit - Google Patents

Abstract

PURPOSE:To attain write protection of a common area and to arrange a stack area on each bank memory section by moving the stack area to the common area at bank switching to attain interruption protection at switching. CONSTITUTION:In calling a sub-program (existing in a bank memory section 15) by a main program (existing in a bank memory section 14), a bank switch program 12 designates a decoder 11, releases write protection, permits the write on a common area 12 and locates the stack area on the common area section 12 to save restoration information of the main program. A prescribed value is set to a bank register 6, the bank memory section 15 is adopted and the stack area is arranged there on. Then a decoder 10 is designated to set a latch section 9 to protect writing of the common area section.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information processing device that performs segment switching.

In recent years, as the functionality of electronic devices has expanded, the lack of addressing in microprocessors has become a major hindrance to program development. One way to solve this problem is to create banks of memory.

The area excluding the common storage means (common area) is referred to as a segment and is hereinafter referred to as a bank), and the individual storage means (hereinafter referred to as bank memory) has an external selection register (hereinafter referred to as a bank register) and has a common address area. ).

This is an attempt to expand the addressing area of microprocessors.

In the above means, the stack area of the application program is placed in a common area because if it is placed in a bank memory, data may be destroyed if an interrupt occurs during bank switching.

Therefore, not only is the common area increased and the bank memory area reduced, but it is no longer possible to apply a write protection function to the common area.

Management programs such as bank switching programs are stored in the common area, and must not be accidentally destroyed by application programs.

Therefore, there is a need for an information processing device that allows the stack area to be placed in a bank memory and that provides write protection to the common area.

[Conventional technology]

The conventional technology will be explained below.

FIG. 2(a) is a diagram explaining the possibility of data destruction when a stack area is placed in a bank memory, and FIG. 2(b) is a flowchart explaining the bank switching operation in FIG. 2(a). .

In FIG. 2(a), 1 is a microprocessor.

2 is a common area section of the memory, and 3 to 5 are bank memory sections.

If the addressable area of the microprocessor 1 is 64 bytes, then as shown in Figure 2 <oooo~FFFF (1
Although expressed in hexadecimal notation), this area is occupied by the common area section 2 and the selected bank memory sections 3 to 5.

Although the bank memory sections 3 to 5 have the same addressing in the microprocessor 1, they are each selected by the bank switching program 2a in the common area section 2.
The addressing area will essentially be expanded.

, bank memory sections 3 to 5 are selected by bank register 6.
This is done by writing selection information into the .

It is possible to access the common area section 2 from each of the bank memory sections 3 to 5, and therefore, the stack areas of the application programs in the bank memory sections 3 to 5 are arranged in the common area section 2, respectively.

The common area portion 2 increases, the bank memory portions 3 to 5 decrease accordingly, and write protection of the common area portion 2 becomes impossible.

As explained above, the stack area is for each bank memory section 3 to
5, but during puncture changeover, NM
If an interrupt such as I occurs, there is a possibility that information in the bank memory will be destroyed.

The reason will be explained below.

In FIG. 2(a), it is assumed that the main program currently stored in the bank memory section 4 is in operation and the stack area from a to b is currently being used. That is, the stack pointer points to the current location.

Here, an example of the operation when branching to a subprogram in the bank memory section 5 will be described with reference to FIG. 2(b).

(1) The main program of the bank memory section 4 specifies the subprogram name and requests the bank switching program 2a to branch.

(2) The bank switching program 2a switches to the bank memory section 5 and starts the subprogram.

(3) In this subprogram, the stack area is placed in the eye area, and then the final information of the main program is placed in the star area.
The data is saved to a new area and the predetermined process is started.

After the above processing is completed, the saved data is restored and the process returns to the bank switching program 2a.

(4) The bank switching program 2a switches to the bank memory section 4 in which the main program is stored, and starts the main program.

In the above operation, after bank memory switching.

Until a subprogram is started and the subprogram allocates a stack area, the value of the stack pointer SP that specifies the address of the stack area is that of the main program, and for the bank memory unit 5, it is an address unrelated to the stack address. It becomes.

Therefore, if an interrupt such as NMI occurs at this point,
Address b of bank memory section 5 is recognized as a stack address, and there is a possibility that it will be destroyed.

The bank switching operation by subprogram branching has been described above, but the same applies to the bank switching operation by hardware interrupt.

For the above reasons, conventionally the stack area is placed in the common area section 2. Therefore, write protection cannot be applied to the common area section 2.

[Problem that the invention seeks to solve]

As explained above, the conventional method of providing a stack area in the common area has the problem that the area of the bank memory is reduced and the common area cannot be protected from writing.

For this reason, it is possible to provide a stack area in the bank memory, but when switching the bank memory.

As mentioned above, the microprocessor holds the stack pointer of the previous bank memory until the stack pointer is updated. Therefore, there is a problem that when an interrupt such as NMI occurs, the information in the bank memory after switching may be destroyed.

The present invention provides an information processing device that prevents failures due to the above-mentioned interrupts, arranges a stack area in a bank memory, and protects a common area from writing during a bank switching period.

[Means for solving problems]

The above conventional problem is that writing to the common storage means is prohibited/
means for canceling, a means for arranging a stack area in the common storage means or the individual storage means, and a means for switching the individual storage means, and upon a switching request, the write protection is canceled and the stack area of the requesting individual storage unit is changed. The problem is solved by the information processing apparatus of the present invention, which switches to the request destination individual storage means after arranging the problem in the common storage means, and after the above switching, arranges a stack area in the individual storage means, prohibits the above writing, and starts a predetermined program. be able to.

[Effect]

That is, according to the second invention, if there is a bank switching request.

First, move the stack area of the running program to the common area. After this operation, even if bank switching is performed, the star 7
Since the pointer is specified correctly, data will not be destroyed by an interrupt. Therefore, after bank switching, the stack area can be moved into the bank.

By arranging the stack area in each bank by the above means, write protection of the common area can be implemented, but the write protection is canceled during the above switching.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) is a block diagram showing a part of the information processing apparatus according to the present invention, and FIG. 1(b) is a flowchart showing the operation. Note that the same symbols represent the same objects throughout the figures.

- In FIG. 1 (al), 12 is a common area section in which a bank switching program 12a, a stack area section 12b, a startup information memory section 12c, etc. are stored.

The bank switching program 12a performs a stack area arrangement operation,
Bank switching operation, recovery information saving operation.

Performs program startup operations, etc.

Bank memory units 13 to 15 each have means (not shown) for identifying the output of the bank register 6 and validating the addressing of the microprocessor 1. It is assumed that the operating system is stored in the bank memory section 13.

The bank memory section 13 is configured to be selected when the bank register 6 is cleared.

Reference numeral 8 represents a bank switching section, which includes a bank switching program 12.
Bank selection information is written into the bank register 6 by a, and the signal is sent to each bank memory section 13-15 through the bank memory selection signal line 104.

Reference numeral 16 denotes a write inhibit/cancel signal generating unit, which specifies the decoder 10.11 by the command of the bank switching program 12a, resets the launch unit 9, and sends the signal to the write enable signal line 101. do.

102 is a read/IF write control line connected to the microprocessor 1, which is logically ANDed (gate 17) with the write enable signal line 101, and when the launch section 9 is set, 1 is forcibly written. inclusion is prohibited. Note that 100 represents a bus line.

An example of the operation of the above configuration will be explained with reference to the flowchart shown in FIG. 1('b).

(1) The main program (bank memory section 14) requests the bank switching program 12a to call the subprogram (bank memory section 15).

(2) The bank switching program 12a designates the decoder 11, cancels write protection, and permits writing to the common area section 12.

(3) After the bank switching program 12a arranges the stack area in the common area section 12, it saves the return information of the main program.

(4) Next, a predetermined value is sent to the bank register 6 to switch the bank memory section.

(5) A stack area is arranged in the bank memory section 15.

(6) Specify the decoder 10 and set the latch section 9,
Write protection for the common area section 12 is implemented.

(7) The startup information memory section 12C is connected to the microprocessor 1
, and start the subprogram.

As explained above, by moving the stack area to the common area section 12, data protection against one interrupt can be implemented, so the stack area can be placed in each bank memory section. Therefore, write protection of the common area can be implemented, but because of the bank switching operation described above, the write protection is canceled at the time of switching.

[Effects of the Invention] As explained above, by moving the stack area to the common area when switching banks, it is possible to protect interrupts at the time of switching. This has the effect of making it possible to write protect the area.

[Brief explanation of drawings]

Figure 1 (al is a book diagram of an information processing device that implements the present invention. Figure 1 (b) is an operation flowchart. Figure 2 (a) (bl is the effect of interrupts when a stack area is placed in bank memory. 1 is a microprocessor. 6 is a bank register. ?, 10.11 is a decoder. 8 is a bank switching section. 9 is a latch section. 12 is a common area section. 12a is a bank switching section. Program. 12b is a stack area section. 12C is a startup information memory section. 13 to 15 are bank memory sections. 16 is a write inhibit/release signal generation section. 17 is a gate. 100 is a bus line. 101 is a write enable signal line . 102 is a read/write control line. 104 is a bank memory selection control line.

Claims (1)

[Claims] An information processing device comprising a plurality of individual storage means that have a common address and are selected and operated, and a common storage means,
Means for prohibiting/cancelling writing to the common storage means, means for arranging a stack area in the common storage means or the individual storage means, and means for switching the individual storage means are provided, and the writing prohibition is canceled upon a switching request. After arranging the stack area of the request source individual storage means in the common storage means, switch to the request destination individual storage means, and after the above switching, after arranging the stack area in the individual storage means, prohibit the above writing and start a predetermined program. An information processing device characterized by: