JPS5831651A - Restart processing system for electronic exchanger - Google Patents
Restart processing system for electronic exchangerInfo
- Publication number
- JPS5831651A JPS5831651A JP13056281A JP13056281A JPS5831651A JP S5831651 A JPS5831651 A JP S5831651A JP 13056281 A JP13056281 A JP 13056281A JP 13056281 A JP13056281 A JP 13056281A JP S5831651 A JPS5831651 A JP S5831651A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- restart
- data
- backup
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
- H04M3/241—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for stored program controlled exchanges
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/54558—Redundancy, stand-by
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
Description
【発明の詳細な説明】 本発−１は、電子交換機の再開処理方式に関する。[Detailed description of the invention] The present invention-1 relates to a restart processing method for an electronic exchange.
従来、電子交換機では障害による再開のため、コールデ
ータセーブエリアをディスク上又はバブル上に確保し、
再開時そのデータを用ｉて再開原因が発生する前の状態
にもどし再開していた。このため、周期的に書き込むプ
ログラムが必要になることや、ディスクやバブルをアク
セスしているため、データが古くなる欠点牟あうた。Conventionally, in electronic exchanges, a call data save area is secured on a disk or bubble in order to restart in the event of a failure.
When restarting, the data was used to return to the state before the restart cause occurred and restart. For this reason, there are disadvantages such as the need for a program to periodically write data, and the fact that the data becomes outdated because the disk or bubble is accessed.
本発明は従来の方法のこのような欠点を除去し、再開処
理を行なう時点を早め、又データの書き込みをプロゲラ
文によらずに行なうため、電子交換機のオーバヘッドを
低減した電子交換機の再開処理方式を提供するものであ
る。The present invention eliminates these drawbacks of the conventional method, accelerates the restart processing time, and writes data without using progera text, thereby reducing the overhead of the electronic switching equipment. It provides:
０１つは交換処理用として使用し、他のメモリは障害が
発生し再開が起った場合再開用バックアップデータとし
て使用することを特・黴とする電子交換機の再開処理方
式が得られる。01 is used for switching processing, and the other memories are used as backup data for restarting when a failure occurs and restarting occurs. This is a restart processing method for an electronic switching equipment.
以下本発明を図面にり埴て説明する。第１図は本発明の
詳細な説明図で、従来 電子交換機では周期的に、再開
のためのデータを、交換処理で使用しているメインメモ
リの１定エリアより読み出し、ディスク又はバブルに書
き込んで一九。本発明は第１ＩＩＫ示すようにこのメイ
ンメモリ１の１定エリア２のメモリ実装を２重又はそれ
以上にし、同で。The present invention will be explained below with reference to the drawings. FIG. 1 is a detailed explanatory diagram of the present invention. In a conventional electronic exchange, data for restarting is periodically read from a fixed area of the main memory used in the exchange process and written to a disk or a bubble. Nineteen. As shown in IIK of the present invention, the memory implementation of one fixed area 2 of the main memory 1 is doubled or more.
−アドレ〉像すことができるメモリを２個以上設けるこ
とにより、ディスク又はパズルへの書き込みを不要とす
るものである。再開時は、この現に使用中のメモリ以外
Ｏメモリを使用する。通常再開時はメモリクリアが行な
われるが、このエリア２に限っては、同一アドレスの他
メモリのデータを転送し、再開用バックアップデータと
して使用する。従って、ディスク又はバブルのアクセス
がなくなるため、再開時点が、２５０ｍ５ｅｃ前の時点
から行なえるようになる。-Address> By providing two or more memories that can be imaged, writing to a disk or puzzle is not necessary. When restarting, O memory other than the memory currently in use is used. Normally, when restarting, memory is cleared, but only for this area 2, data from other memories at the same address is transferred and used as backup data for restart. Therefore, since there is no access to the disk or bubble, the restart can be made from a point 250 m5ec earlier.
すなわち、通常再開のためにコールデータセーブエリア
はある定まったメモリエリアが割付けられて埴るので、
仁のコールデータセーブエリアを対象に、このメモリの
構造を第１図のよりに作成する。コールデータセーブエ
リア２と同じアドレスを持ち、同じエリアナイズを持つ
２重またはそれ以上のメモリ３．４を実装する。これら
をメモリバックアップメモリと称し、メインメモリ１に
関係の深いものからメモリ番号を付与する。通常メイン
メモリｌのコールデータセーブエリア２は、呼処理の動
作に伴ないアクキスされている。この間に周期的にメモ
リバックアップメモ１す３に対するゲートが開き、メイ
ンメモリ１と同一内容のデータがメモリバックアップメ
モリ３に書き込まれる。さらに次の層４へは、周期的に
、データ転送が行なわれる。従ってこの周期により、メ
インメモリｌ←メモリバックアップメモリ３間又は、メ
モリバックアップメモリ同志３．４間で、セーブしたデ
ータに時間差が生じる。In other words, a certain fixed memory area is allocated and saved as the call data save area for normal restart.
This memory structure is created as shown in Figure 1, targeting Jin's call data save area. Implement double or more memories 3.4 with the same address as the call data save area 2 and with the same areaization. These are referred to as memory backup memories, and memory numbers are assigned from those most closely related to the main memory 1. Normally, the call data save area 2 of the main memory 1 is accessed during call processing operations. During this period, the gates for the memory backup memo 1 to 3 are periodically opened, and the same data as the main memory 1 is written to the memory backup memory 3. Further, data is transferred periodically to the next layer 4. Therefore, due to this period, a time difference occurs in the saved data between the main memory 1 and the memory backup memory 3 or between the memory backup memories 3 and 4.
データがこのような構造でセーブされてφる時に再開が
発生すると、まずメモリバックアップメモリへのアクセ
スを中断し各データの破壊が行なわれないことを確認し
た時点で、再開処理の初期コールデータセーブエリア２
へ転送し、呼処理の再開を試みる。失敗し九場合は、次
の層４のデータを転送し、再開を試みる。とのようにし
て、５００ｍ５ｅｃの単位で保存したデータを使用して
再開が試みられることになる。When restarting occurs when data is saved in this structure and φ, access to the memory backup memory is first interrupted, and once it is confirmed that each data is not destroyed, the initial call data save of restart processing is executed. Area 2
and attempts to resume call processing. If it fails, the next layer 4 data is transferred and a restart is attempted. In this way, a restart will be attempted using the data saved in units of 500 m5ec.
現実的には、瞬時に同一メモリ内容のものを作成するこ
とはできないと考えられるので、メモリバックアップメ
モリを２面使用した方式が考えられる◎これを第２図に
示す。第１図でメモリバックアップメモリ３に相当する
メモリを入面Ｂ面に分・け、交互にコピーを行なう。メ
モリＡがメインメモリｌと接続され、コピー中の時は、
メモリＢは書き込み禁止とし、次の層４へのデータ転送
のための読み出しのみ可能とする。コピー中でない方の
面は、再開時のバックアップメモリとして使用される。In reality, it is not possible to instantly create the same memory contents, so a method using two memory backup memories can be considered. This is shown in FIG. 2. The memory corresponding to the memory backup memory 3 in FIG. 1 is divided into an input side B side, and copies are made alternately. When memory A is connected to main memory L and copying is in progress,
Memory B is write-protected and only readable for data transfer to the next layer 4. The side that is not being copied is used as backup memory when restarting.
メインメモリから見ると常時どちらかの面とのコピー動
作が行はれている。尚メモリコピー途中でデータが変わ
ることがあるが、各面の中で、コピーが済んだ部分は、
メインメモリメモリバックアップメモリ共書きかえ、済
んでいない部分は、メインメモリを書き替えるだけで、
常に、メインメモリと同じ状態でコピーが行なわれる。When viewed from the main memory, a copy operation with either side is always occurring. Although the data may change during memory copying, the portion of each side that has been copied is
Rewrite both the main memory and backup memory, and for the unfinished portions, simply rewrite the main memory.
Copying is always performed in the same state as main memory.
再開時は、第１図の場合と同じ処理を行なう。When restarting, the same processing as in FIG. 1 is performed.
本発明は、以上説明したように、再開用のコールデータ
を２５０ｍ５ｅｃ単位で確保しておくことができる。コ
ールデータのメモリサイズにもよるが、約５００ＫＷ（
１６ピツト）としてその確保には、ＩＷ当り５００ｎｓ
ｅｃとすると２５０ｍ５ｅｃかかり、古くても、２５０
ｍ５ｅｃｉｌｌＯデータが使用できることＫなシ、デー
タ交換機では、呼処理データの多くが救済されることに
なる。As described above, the present invention can secure call data for restart in units of 250 m5ec. Approximately 500KW (depending on the memory size of call data)
16 pits), it takes 500ns per IW to secure it.
If it is ec, it will take 250m5ec, and even if it is old, it will take 250m5ec.
If m5ecilO data is available, much of the call processing data will be saved in the data switch.
又、再開時にディスクやバブルをアクセスしないため、
再開に要する時間が低減される。Also, since the disk and bubble are not accessed when restarting,
The time required for restarting is reduced.
本発明によると以上説明したように、再開処理を行なう
時点を早め、また電子交換機のオーバヘッドを低減する
ことができる。According to the present invention, as described above, it is possible to accelerate the restart process and reduce the overhead of the electronic exchange.
第１図は本発明の原理説明
雷、第２図は本発明の実施例の構成図である。
１・・・・・・メインメモリ、２・・・・・・コールデ
ータセーブエリア、３ ｅ ４ ・”・メモリバックア
ップメモリ。FIG. 1 is an explanation of the principle of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention. 1...Main memory, 2...Call data save area, 3e4...Memory backup memory.
Claims (1)
して使用し、他のメモリは障害が発生し再開が起った場
合再開用バックアップデータとして使用することを特徴
とする電子交換機の再開処理方式。A restart process for an electronic exchange, characterized in that one of the wrinkled memories is used for exchange processing, and the other memory is used as backup data for restart when a failure occurs and restart occurs. method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13056281A JPS5831651A (en) | 1981-08-20 | 1981-08-20 | Restart processing system for electronic exchanger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13056281A JPS5831651A (en) | 1981-08-20 | 1981-08-20 | Restart processing system for electronic exchanger |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5831651A true JPS5831651A (en) | 1983-02-24 |
Family
ID=15037214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13056281A Pending JPS5831651A (en) | 1981-08-20 | 1981-08-20 | Restart processing system for electronic exchanger |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5831651A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6273847A (en) * | 1985-09-27 | 1987-04-04 | Hitachi Ltd | On-line constitution control system |
| US4819154A (en) * | 1982-12-09 | 1989-04-04 | Sequoia Systems, Inc. | Memory back up system with one cache memory and two physically separated main memories |
| US4823261A (en) * | 1986-11-24 | 1989-04-18 | International Business Machines Corp. | Multiprocessor system for updating status information through flip-flopping read version and write version of checkpoint data |
| US5737514A (en) * | 1995-11-29 | 1998-04-07 | Texas Micro, Inc. | Remote checkpoint memory system and protocol for fault-tolerant computer system |
| US5745672A (en) * | 1995-11-29 | 1998-04-28 | Texas Micro, Inc. | Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer |
| US5751939A (en) * | 1995-11-29 | 1998-05-12 | Texas Micro, Inc. | Main memory system and checkpointing protocol for fault-tolerant computer system using an exclusive-or memory |
| US5787243A (en) * | 1994-06-10 | 1998-07-28 | Texas Micro, Inc. | Main memory system and checkpointing protocol for fault-tolerant computer system |
| US5864657A (en) * | 1995-11-29 | 1999-01-26 | Texas Micro, Inc. | Main memory system and checkpointing protocol for fault-tolerant computer system |
-
1981
- 1981-08-20 JP JP13056281A patent/JPS5831651A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4819154A (en) * | 1982-12-09 | 1989-04-04 | Sequoia Systems, Inc. | Memory back up system with one cache memory and two physically separated main memories |
| JPS6273847A (en) * | 1985-09-27 | 1987-04-04 | Hitachi Ltd | On-line constitution control system |
| US4823261A (en) * | 1986-11-24 | 1989-04-18 | International Business Machines Corp. | Multiprocessor system for updating status information through flip-flopping read version and write version of checkpoint data |
| US5787243A (en) * | 1994-06-10 | 1998-07-28 | Texas Micro, Inc. | Main memory system and checkpointing protocol for fault-tolerant computer system |
| US5737514A (en) * | 1995-11-29 | 1998-04-07 | Texas Micro, Inc. | Remote checkpoint memory system and protocol for fault-tolerant computer system |
| US5745672A (en) * | 1995-11-29 | 1998-04-28 | Texas Micro, Inc. | Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer |
| US5751939A (en) * | 1995-11-29 | 1998-05-12 | Texas Micro, Inc. | Main memory system and checkpointing protocol for fault-tolerant computer system using an exclusive-or memory |
| US5864657A (en) * | 1995-11-29 | 1999-01-26 | Texas Micro, Inc. | Main memory system and checkpointing protocol for fault-tolerant computer system |
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