JPS61149336U - - Google Patents
Info
- Publication number
- JPS61149336U JPS61149336U JP3261485U JP3261485U JPS61149336U JP S61149336 U JPS61149336 U JP S61149336U JP 3261485 U JP3261485 U JP 3261485U JP 3261485 U JP3261485 U JP 3261485U JP S61149336 U JPS61149336 U JP S61149336U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- wiring pattern
- expansion coefficient
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 4
- 239000002184 metal Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 3
- 239000000919 ceramic Substances 0.000 claims 1
Description
第１図Ａは、本考案の一実施例に係るピングリ
ツドアレイタイプＩＣパツケージ基板を示す斜視
図、同Ｂは第１図Ａは―′線断面図、第２図
は従来のピングリツドアレイタイプＩＣパツケー
ジ基板を示す斜視図である。
FIG. 1A is a perspective view showing a pin grid array type IC package board according to an embodiment of the present invention, FIG. FIG. 2 is a perspective view showing a lay-type IC package board.
Claims (1)
数の金属ピンを突設し、該半導体素子と該金属ピ
ンとを電気的に接続する配線パターンを基板の表
面及び／又は内部に形成してなるものにおいて、
半導体素子の熱膨張係数をａとするとき、該基板
の半導体素子搭載部が熱伝導率４０Ｗ／ｋ・ｍ以
上で、熱膨張係数βが｜α―β｜≦２０×１０−
７／℃を満足する材料よりなり、非搭載部が温度
９００〜１１００℃で焼結する低誘電率セラミツ
クスよりなり、配線パターンが比抵抗２．５×１
０−６Ωcm以下の低抵抗金属よりなるピングリツ
ドアレイタイプＩＣパツケージ基板。 A semiconductor element is mounted on one main surface of a substrate, a large number of metal pins are provided protruding from the back surface, and a wiring pattern for electrically connecting the semiconductor element and the metal pins is formed on the surface and/or inside of the substrate. In what becomes
When the thermal expansion coefficient of the semiconductor element is a, the semiconductor element mounting portion of the substrate has a thermal conductivity of 40 W/km/km or more, and the thermal expansion coefficient β is |α−β|≦20×10 −
7 /℃, the non-mounting part is made of low dielectric constant ceramics sintered at a temperature of 900 to 1100℃, and the wiring pattern has a specific resistance of 2.5×1.
Pin grid array type IC package board made of low resistance metal of 0-6 Ωcm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3261485U JPS61149336U (en) | 1985-03-06 | 1985-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3261485U JPS61149336U (en) | 1985-03-06 | 1985-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61149336U true JPS61149336U (en) | 1986-09-16 |
Family
ID=30534291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3261485U Pending JPS61149336U (en) | 1985-03-06 | 1985-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61149336U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649550A (en) * | 1979-09-28 | 1981-05-06 | Hitachi Ltd | Semiconductor device |
| JPS5816596A (en) * | 1981-07-23 | 1983-01-31 | 日本電気株式会社 | High density multilayer circuit board |
| JPS59137341A (en) * | 1983-01-20 | 1984-08-07 | Ngk Spark Plug Co Ltd | Crystallized glass body |
-
1985
- 1985-03-06 JP JP3261485U patent/JPS61149336U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649550A (en) * | 1979-09-28 | 1981-05-06 | Hitachi Ltd | Semiconductor device |
| JPS5816596A (en) * | 1981-07-23 | 1983-01-31 | 日本電気株式会社 | High density multilayer circuit board |
| JPS59137341A (en) * | 1983-01-20 | 1984-08-07 | Ngk Spark Plug Co Ltd | Crystallized glass body |
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