JPS61147341A - Branch control system - Google Patents

Abstract

PURPOSE:To attain high speed processing with simple control by setting a branch destination address of a branch instruction to an address register for the 2nd operand. CONSTITUTION:In executing a normal instruction, the 1st operand address register 2 and the 2nd operand address register 3 are used together, and in case of a branch instruction, since the 2nd operand address register 3 is not used, the branch destination address is set to the register 3. In branching the instruction, the instruction is branched by using the content of the 2nd operand address register 3 so as to fetch the instruction. In this case, the address of the instruction to be executed next after branching is produced by adding 1 to the content of the 2nd operand address register 3, and it is stored to an instruction fetch address register 1 via a multiplexer 4.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a control method for executing conditional branch instructions and unconditional branch instructions in an information processing device having conditional branch instructions and unconditional branch instructions in the instruction system. be.

[Conventional technology]

When executing an instruction in the arithmetic unit of an information processing device, the address of the instruction to be executed next to the currently executing instruction is determined by adding the instruction length of the instruction to the address of the currently executing instruction. Since the address value can be easily determined as the address value, it can be controlled by calculating the address value and setting it in the instruction fetch address register. - On the other hand, with a conditional branch instruction, when the condition for branching is not met, the next instruction to be executed is read using the control described above, but when the condition for branching is met, the operand of the conditional branch instruction is read. Must branch to the specified address. Furthermore, these addresses are usually not directly designated as address values, and it is necessary to derive the address value actually used by adding values such as the contents of designated registers.

Conventionally, as a control method for a branch related to the execution of such a conditional branch instruction, after confirming that the branch condition has been met, the address specified by the operand of the conditional branch instruction is calculated, and this is then executed by the instruction. It was common practice to set the fetch address register and read out the next instruction to be executed.

On the other hand, in an information processing device that adopts a proactive control method in which an instruction is fetched in advance for the purpose of speeding up processing, and a table source necessary for executing the instruction is prepared, when branching In preparation for this, a special register is provided to store the branch destination address in advance.The branch destination address is stored in this register in advance, and when the branch instruction is executed, the contents of the register are A method was adopted in which instructions were fetched using .

Furthermore, if these information processing devices handle logical addresses and have a conversion mechanism from logical addresses to real addresses, in any of the above methods,
After generating the instruction fetch address (logical address),
A method has been adopted in which this is translated by an address translation mechanism to obtain a real address, and an instruction is fetched using the real address.

[Problem that the invention seeks to solve]

In each of the conventional methods mentioned above, the method that calculates the branch destination address after confirming that the branch conditions are met has the problem of slow processing speed. In the case where a special register is provided to store the branch destination address in advance for the purpose of timing, there is a problem in that the amount of hardware required for the register and its peripheral circuit K13 is large.

Further, those having a mechanism for converting an instruction fetch address from a logical address to a real address have the problem of slow processing speed.

Furthermore, if the branch instruction is an unconditional branch instruction, unlike a conditional branch instruction, the branch destination address is uniquely determined from the beginning, so the control and conditions for executing the unconditional branch instruction are Some information processing devices are configured to separately control the execution of branch instructions, but in such cases there are problems in that the amount of hardware increases and the control becomes complicated. .

SUMMARY OF THE INVENTION In view of the above conventional problems, it is an object of the present invention to provide a control system for executing branch instructions that allows for simple control and high-speed table processing without increasing the amount of hardware.

[Means for solving problems]

According to the present invention, when executing a branch instruction in an information processing device FT having a branch instruction in its instruction system, the branch instruction is In this case, the branch destination address is stored in a register that is not used, and when branching, the contents of this register are used to fetch the instruction, and the value obtained by adding one address unit to the contents of this register is stored in the instruction fetch address register. A branch control method characterized in that the branch destination address is a logical address, and when the branch destination address is stored in a register, the branch destination address is simultaneously converted to a real address and the resulting information is retained. When branching, fetch the instruction using this information and the contents of the register, and at the same time store the value obtained by adding one address unit to the contents of the register in the address register for instruction 7. This is achieved by the branch control method described above, which converts to a real address and holds the resulting information in the resources used for normal instruction fetches.

〔Example〕

FIG. 1 is a schematic diagram of one embodiment of the present invention, in which 1 is an address register (IA) for fetching instructions, 2 is an address register for the first operand, 3 is an address register for the second operand, 4.7 is a multiplexer, 5 is an address update/calculation processor, 6 is an instruction prefetch unit, 13 is +
It represents one circuit.

In FIG. 1, the address update/calculation block 5 has the function of updating and calculating addresses for instruction fetch, first operand, and second operand, and also has an address register for instruction fetch. Since this circuit prefetches instructions by the instruction prefetch unit 6, 1 indicates the address of the instruction that precedes the currently executed instruction. When executing a normal instruction, address register 2 for the first operand and address register 3 for the second operand are both used, but in the case of a branch instruction, address register 3 for the second operand is not used. In the case of this embodiment, the branch destination address of the branch instruction is set in the address register for this second operand, and when branching, the instruction is executed using the contents of address register 3 for the second operand. Branching by fetching. At this time, by adding the content (branch destination address) Kl of the address register 3 for the second operand, the address of the instruction to be executed in the branching method is generated, and this is sent to the instruction fetch address register IK multiplexer. It is stored via 4.

The operation of the embodiment shown in FIG. 1 will be explained in detail below using a time chart.

FIG. 2 is a time chart for normal instruction execution. That is, in FIG. 2, during cycles b-d, instruction n is executed, and in cycle C, when the memory is not accessed during the execution of the instruction, the instruction prefetch section +2 is accessed. . This figure shows a case where the contents of the address indicated by address register 3 for the second operand are processed and stored at the address indicated by address register 2 for the first operand. There is a time chart set when the branch condition is not satisfied during execution. In this case, the branch instruction has no first operand, and the branch destination address is stored in the second operand address register 3 at the same time as the execution cycle begins. Since the judgment result in cycle C is that the branch condition is not satisfied, the data stored in the second operand address register 3 is not used, and the next instruction (n+1 instruction) is executed as in normal instruction execution.

FIG. 4 is a time chart when branching is performed upon execution of a conditional branch instruction or an unconditional branch instruction. In the same figure, in cycle C, since it was found that the branch condition was established, the X instruction was executed 7 times using the branch destination address previously stored in the address register for the second operand.
Eh, I'm doing it. At this time, the value of the branch destination address +1 is stored in the instruction fetch address register, and %x+1' instructions are fetched in cycle d.

In the case of an unconditional branch, there is no need to recognize whether the branch condition has been met or not, so the instruction is fetched using the branch destination address uniquely stored in the address register for the second operand. do.

FIG. 5 is a block diagram of another embodiment of the present invention, showing an example of an implementation in which address translation (conversion from a logical address to a real address) is required when fetching an instruction.

In FIG. 5, 1' to 7' are the same as 1 to 7 in FIG. 1, 8 is a multiplexer, 9 is an address conversion processor,
10 to 12 represent registers, and 13' represents a +1 circuit. In the case of this embodiment, address register 1' for instruction fetch, address register 2 for first operand
' and the address value stored in the second operand address register 3' are logical addresses. At the same time as the logical address stored in these registers is stored in the register, the logical page portion thereof is selected by the multiplexer 8, converted to a physical page value by the address conversion block 9, and stored in one of the registers 10 to 12. be done.

Then, a memory address is generated from the physical page value and the lower value of the logical address value.

The symbol F displayed in register 10 represents address translation data related to instruction fetch, and TLB
Contains information such as faults, address overs, and protection.

The symbol PIF indicates that it holds the physical page portion of the address for fetching instructions.

The symbol D displayed in register 11 represents address translation data regarding the first operand, and the symbol 8 displayed in register 12 represents address translation data regarding the second operand, respectively. and protection information. Furthermore, the display of POI and PO2 displayed in register 11 or register 12 indicates that the physical page part of the address for the first operand or the physical page part of the address for the second operand is held, respectively. .

In FIG. 5, when a branch instruction is executed, the branch destination address (logical address) is set in the address register 3' for the second operand, but at the same time, the logical page part of the branch destination address is set to the address register 3'. It is converted into a physical page value by the conversion processor 9 and held in the register 12. Then, a memory address is generated from the lower contents of the address register 3' for the second operand and PO2 of the register 12, and a branch is performed based on this. At this time, the second operand address register 3'
The contents of are incremented by +1 by the +1 circuit 13' and sent to the instruction fetch address register 1 via the multiplexer 4'.
', and the value incremented by 1 is converted to a physical page value by the address conversion processor 9 and held in the register 10.

The operation of this embodiment will be explained below using a time chart.

FIG. 6 is a time chart for normal instruction execution, and shows a case where data of the second operand is processed and stored in the first operand.

In FIG. 6, the cycles b to d of the Kf-n instruction are execution cycles. The n instruction has been decoded by the instruction prefetch section before entering cycle b, and at the same time as entering cycle b, LO2 and register 12 are stored in the second operand address register 3'.
8/PO2 is set.

The read cycle is performed in cycle b.

The next cycle C is a data processing cycle and the memory is free, so during that time the instruction pre-fetching section prefetches instructions using PIF7I and IP. Also, at the same time as cycle C is entered, LOI is stored in the first operand address register 2'.
Does the D/PO1 set line appear in register 11? At cycle d in the table, machining data is written in the first operand.

On the other hand, at the end of cycle C, I, IP is updated to fetch the next instruction. In the case of FIG. 6, since n to n+4 are on the same page, the PIF does not change (it was set before entering this time chart).

FIG. 7 is a time chart when the branch condition is not satisfied when a conditional branch instruction is executed. In FIG. 7, upon entering cycle b, the branch destination logical address is set in the second operand address register 3'. 3' and at the same time set the address translation result to 12.

When it becomes clear that the branch is not taken in cycle C, cycles d to n
+1 starts executing the instruction. Since there is no operand access in the top cycle d of the n+1 instruction, an instruction fetch (n+3) access is performed to prefetch the instruction.

FIG. 8 is a time chart when a branch is executed upon execution of a false conditional branch instruction or an unconditional branch instruction. In the same figure, when it is found that the branch condition is met in cycle C, the X instruction is fetched using the branch destination logical address set in the second operand address register 3' and the physical page value held in the register 12. .

Then, in cycle d, the X instruction is executed. Furthermore, at this time, 1 is added to the contents of the second operand address register 3' (branch destination address) and stored in the instruction fetch address register 1', and the physical page is held in the register 10. , the 'x+1' instruction is fetched using these in cycle d. In the case of an unconditional branch, there is no need to recognize whether or not the branch condition has been met, so the branch can be uniquely branched.

〔Effect of the invention〕

As described in detail above, according to the branch control method of the present invention, information processing that can perform high-speed processing with simple control without causing an increase in downtime related to the execution of branch instructions is possible. Since it is possible to realize the device, the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a time chart for normal instruction execution, FIG. 3 is a time chart for when the branch condition is not satisfied when executing a conditional branch instruction, and FIG. Figure 4 is a time chart for branching when executing a conditional or unconditional branch instruction, Figure 5 is a diagram of another embodiment of the present invention, and Figure 6 is for normal instruction execution. FIG. 7 is a time chart when the branch condition is not satisfied when executing a conditional branch instruction, and FIG. 8 is a time chart when branching is performed when executing a conditional branch instruction or an unconditional branch instruction. 1.1'...address register for instruction fetch, 2.
2'...Address register for first operand, 3.3
'...Address register for second operand, 4.4'
, 7.7', 8... multiplexer, 5... address update/update pro, ri, 6... instruction prefetch unit,
9...Address conversion professional, 10-12...Register, 13.13'...+1 circuit agent Patent attorney Hiroshi Matsuoka 4th Department Figure 1 vT2 Figure 'i43 Figure $4 Zuso Bunbin Article #Weiyu Hanro No. 5 Figure 146

Claims (2)

[Claims] (1) In an information processing device that has a branch instruction in its instruction system, when executing a branch instruction, the branch destination address is placed in a register that is not used for the branch instruction among the registers that are provided for the execution of normal instructions. Store the
A branch control method characterized in that when branching, an instruction is fetched using the contents of the register, and a value obtained by adding one address unit to the contents of the register is stored in an instruction fetch address register. (2) When the branch destination address is a logical address, and when the branch destination address is stored in a register, the branch destination address is simultaneously converted to a real address, and the resulting information is retained and the branch is made. An instruction is fetched using the information and the contents of the register, and when the value obtained by adding one address unit to the contents of the register is stored in the instruction fetch address register, the value is simultaneously converted to a real address and the The branch control method according to claim 1, wherein result information is held in a resource used for normal instruction fetching.