JPS61198334A - Instruction division processing system - Google Patents

Abstract

PURPOSE:To perform processing in a high speed with a simple control by changing the sequence of instruction execution according as all elements required for execution of instructions are read out from a storage device or not. CONSTITUTION:If 4* of an instruction 1 exists in the following page, the processing is interrupted temporarily, and the processing is restarted after mak ing it possible to read 4*. Since the processing precedes with respect to already read-in 0*-3*, the processing is completed up to a cycle 1. When it is detected that 4* exists in the following page, internal states are saved for the purpose of starting the condition meeting processing, and internal states are restored after the condition meeting processing to restart the processing from a cycle 2. Thus, the processing of the instruction can be executed though two pages of virtual memory do not exist simultaneously on an actual memory. If elements are read in time for the cycle of the execution, the instruction is executed though all elements of one instruction are completed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the control of information processing devices, and in particular, in order to speed up instruction execution, a method is adopted in which one instruction is divided and processed using a pipeline method. This is related.

[Conventional technology]

2. Description of the Related Art In order to meet the demand for faster calculations in order to achieve advanced processing by information processing devices, information processing devices based on instruction execution methods such as advance control and pipeline processing have been devised and used.

Conventionally, in an information processing apparatus of this type, all instructions to be executed are read from a storage device and then passed to a pipeline processing section.

For example, if the width of the instruction fetched from the storage device is 2 bytes and the instruction to be executed is 5 bytes, the instruction is fetched from the storage device three times, and after 5 bytes are completed, Moving on to the next process.

Conventionally, the control method described above has been adopted because by starting processing after all instructions have been completed, it is possible to execute the processing in each part of the pipeline according to a fixed, synchronized sequence. It is intended to achieve simple control by using 6 ratios.

[Problem that the invention seeks to solve]

In the case of the above-mentioned conventional control method, in an information processing device that employs a virtual memory method, for example, when an instruction consists of two pages, each of those pages must exist simultaneously in real memory. , there are problems in that the swapping control algorithm is complicated, such as swapping in all other necessary pages without swapping out the currently existing page, and it requires at least two pages of real memory. Ta.

In addition, in the case of a system that handles variable length instructions, add the instruction length of the instruction to be executed to the instruction start address and check whether the result exceeds the page boundary (pretest)?
However, complicated pretreatment was required.

Since these pre-processings must be performed for all instructions, there is another problem in that they impede speed-up of processing and, of course, increase the amount of equipment resources required.

In view of the above conventional problems, an object of the present invention is to provide a pipeline type information processing device that can be expected to perform high-speed processing with simple control and does not cause an increase in device resources. It is said that

[Means for solving problems]

According to the present invention, this object is achieved in an information processing apparatus configured to perform processing related to instruction execution in a pipeline method, as described in the claims.
a register that holds the address value of the starting position of a portion to be divided and extracted from one instruction; a means for adding the contents of the register and a value given by the control unit and storing the result in the register; means for dividing and retrieving an instruction read from a storage device using the value of the register; and means for detecting whether all elements necessary for executing the instruction have been read from the storage device when executing the instruction. The system divides the instruction read from the storage device into the parts necessary for execution at that time and processes it, and executes the instruction depending on whether all the elements necessary for executing the instruction have been read from the storage device. This is achieved by using an instruction division processing method characterized by changing the sequence of instructions.

〔Example〕

FIG. 1 is a professional diagram of one embodiment of the present invention, in which 1 is a storage device, 2 is an instruction aligner, 3 is an instruction sequence control section, 4 is a control storage device, 5 is an instruction division fetch section, 6 is BX
D calculation section, 7 is ADH calculation section, 8 is address conversion section, 9
represents an arithmetic unit.

In FIG. 1, a storage device 1 stores instructions or data to be executed. The transfer path from the storage device 1 to the instruction aligner 2 has a constant width (4 bytes). However, since the instructions are not aligned every 4 bytes in the storage device 1i11, the instruction aligner 2 performs trap control to align the nine data transferred from the storage device 1 from the beginning of the instruction.

Furthermore, the aligner 2 has a buffer for storing fetched instructions.

A part of the output (opcode) of the instruction aligner 2 and a part of the output of the control storage device are input to the instruction sequence control unit 31C, and an address of the control storage device 4 is generated by the output of the instruction sequence control unit 3. . Each section is controlled by the output (microprogram) of this control storage device 4.

The instruction division and extraction unit 5 divides and extracts the instruction into parts necessary for processing from the instruction aligner 2, and distributes the divided instructions to the corresponding parts.

The BXD calculation unit 6 calculates operand addresses, and the ADH calculation unit calculates addresses such as branch destinations.

The address conversion unit 8 further converts these addresses from virtual addresses to real addresses.

The arithmetic unit 9 uses the real address to perform processing such as referring to the storage device, performing arithmetic operations between registers, or branching to a specified address.

The instruction sequence control unit 3 can determine the part of the instruction necessary for execution based on the value of IBP (described later) and the value read from the control storage device 4 at that time. Then, from the process of referencing the storage device 1, it can be detected whether reading of that portion has been completed. Based on these results and the opcode of the instruction to be executed, an address indicating whether the control information is stored in the location of the control storage device 4 is generated and used as a CS address. Furthermore, the detection circuit checks whether the same instruction has already been read or whether the next instruction has not been read, and thereby the instruction execution sequence is controlled.

FIG. 2 is a block diagram showing an example of the configuration of an instruction aligner and an instruction division and extraction unit, in which 1o is an adder, 11 is an instruction buffer for setting the value of IBP, 12 is a multiplexer,
13 to 16 each represent a 4-byte buffer (instruction buffer), and 17 to 20 each represent a validity display flag attached to the buffer.

As shown in the figure, the buffers 13 to 16 and the validity display flags 17 to 20 are indicated by IBO to IB, respectively, in addition to the above-mentioned codes.
3 Oh! The symbol whole village is 3v from biyori ov to 3v,
This is to facilitate the subsequent explanation. In addition, regarding each signal name, M is the address code between the storage device, cs is the signal from the control memory, OP is the signal to the instruction sequence control unit, BXD is the signal to the BXD calculation unit, and ADH is the signal from the ADH
Signals to the calculation unit and calculation represent signals to the calculation unit. The display IB"t takes 2B appended to each signal indicates that these signals are 1 byte or 2 bytes.

FIG. 3 is a diagram showing in more detail an example of the configuration of the multiplexer in FIG. 2, in which 21 and 21' are data buses connected to respective buffers, 22 to 24 are multiplexer circuits, 25 is a +1 circuit, 26 is +2 circuit, 27f'i
It represents an AND circuit.

The fourth @ is a diagram showing an example of the actual configuration of a multiplexer circuit, and shows the case of the multiplexer circuit 22 (MPXI) in FIG. 3.

In Figure 2, the validity display flags 17 to 20 are '1''
', and assuming that the contents of the respective buffers are valid, the validity of the data output from the rainbow multiplexer can be determined using equation (1).

IB2v-IB3V+IB2V-*IB3V-(1≦I
BP+IP≦4) 10*IB2V-IB3V-(5≦IB
P+IP≦8)・・・・・・・・・・・・・・・・・・
...(1) Formula (1) ((, . represents logical product, . represents logical sum, * represents logical negation, and (1≦
IBP+IP≦4) is the updated value of IBP.

Validity display flags 17 to 20 are set when data is read from the memory into the corresponding instruction buffer, and are reset when all the data in the corresponding instruction buffer has been used via the multiplexer and becomes unnecessary ((). .

Of the buffers 13 to 16, buffer 14 (IB2) and buffer 16 (IB3) are connected to multiplexer 12.

Storing data into each instruction buffer is controlled by a control circuit (not shown) as described below.

That is, the validity display flag IBOV-also 111BI
If V is an invalid display, data 'ft, 4 is stored from the storage device.
Comes to fetch bites. (The address at this time is used as the instruction address register') When the 7 etch is successful and data arrives, it is stored in the instruction buffer whose validity display flag indicates invalidity at /'L'. At this time, if the validity display flag IB2V is invalid, the data passes through the instruction buffer 13 (IBO) and is stored in the instruction buffer 14, and the validity display flag IB2V indicates validity.

Therefore, in steady state, if the instruction buffer is always empty,
The next 4 bytes of data are stored, 4 bytes are prefetched, and the old 8 bytes are visible to the multiplexer.

However, if you need something other than prefetched data for branching, set all the valid display flags to 1-invalid, and send the new friend data from the storage device sequentially by 4 bytes at a time.
Come have sex with me.

The value of the instruction address register is updated when the instruction 7 is successfully executed and stored in the instruction buffer, and is ready to be executed immediately when the validity indicator flag indicates invalid.

The 8-byte data input to the multiplexer is IBP
The output is determined by the value of and the signal (C8) from the control memory. That is, more P.

The byte at the position corresponding to the value goes to the instruction sequence control unit as part 02, and the data at the following two bytes are output. This 2-byte output is a flow signal (flowing even when not needed) and is sent to the BXD% ADH% calculation section, and is set to the destination section using a separately given setting signal. (The signal to section 02 is also a feed signal.) Hereinafter, how an actual command is processed by the method of the present invention will be specifically explained.

FIG. 5 is a diagram showing the format of instructions; (a) shows instruction 1 (5 bytes), (b) shows instruction 2 (3 bytes), and O
P is the instruction code, BXD is the address information of the storage device, R
1, R* represents a register number, M represents mask information, and ADH represents address information.

For example, instruction 1 shown in FIG. 5 is an instruction to calculate the contents of general-purpose registers indicated by &, Rv, and store it at an address of a storage device indicated by BXD, and instruction 2 is an instruction to operate the contents of general-purpose registers indicated by
An instruction that compares the mask information indicated by and the contents of the condition code register of the arithmetic unit, and if they match, branches to the address of the value obtained by adding the value of ADR to the address value of this instruction, FIG. 7 shows a time chart for the case where instruction 1 and instruction 2 are processed successively. In addition, the instruction aligner (buffer) in the time chart
The format of the output is shown in FIG.

Regarding cycles 1 to 7 shown in FIG. 7, the following operations will be described below.

"Cycle 1" ・IBP is '0#, C8 is 0'', and the buffer (IB
2), OP, BXD, R1 of instruction 1 and buffer (
R2 of instruction 1 and instruction 2 are set in IB3).

・Output of the instruction aligner shown in Figure 6 (O*(1) output)
1* and 2* are output to the instruction sequence control unit, and the updated value of P becomes 3.

“Cycle 2” ・IBP is 13” and C8 is 11”, so 3* and 4
* is output, and the updated value of IBP is 2.

- At this stage, the above-mentioned logical formula is established, 2V is displayed as invalid, and the contents of IBO are set to IB2.

“Cycle 3” - IBP is @5” and CS is IO” and 0*, that is, part 02 of instruction 2 is sent to the instruction sequence control unit.

and ■ is also output.

“Cycle 4” - IBP update value is '2', therefore IBP is '7'
becomes. 7* and O* are output.

- Transfer of M is performed.

"Cycle 5" - The updated value of IBP is 2". Therefore, IBP is "1"
′ means that the 9th order instruction is output.

@ADH calculation is performed.

"Cycle 6" - IBP is updated to '0#'. This points to the beginning of the subsequent instruction. (The same operations as those described above will be repeated thereafter, but are omitted here.) If the comparison result between M and the condition code matches, an instruction to branch to the destination of the converted address is read from C8.

- Address translation and comparison of M and condition code are performed. (Here, it is assumed that there is a match.) "Cycle 7" - Branches because the comparison results match.

As explained above, according to the method of this embodiment, if data is prepared in units of 4 bytes, it is possible to execute even the first half of a 5-byte instruction such as instruction 1.

In the series of processing described above, it is assumed that the instructions are read out from the storage device without any delay. However, if for some reason the data is not available by the time the processing starts (for example, the data corresponding to 4* of instruction 1) (When cycle 1 starts with part R8 not yet read),
In the method of the present invention, processing can be started from a location where data exists even if all of one instruction is not available. As long as 4* is read during this cycle, the instruction execution will proceed without any hitch. However, if it is not read by cycle 2, cycle 2 is forced to wait for execution.

On the other hand, if instruction 2 has not been read, the portion of cycle 3 related to instruction 2 will not be executed, and only instruction 1 will be executed independently.

Next, the relationship between the virtual storage system and the present invention will be explained.

For example, when 4* of the above-mentioned instruction 1 exists on the next page, in order to read this 4*, the page containing 4* must exist in real memory and its real address must be known. Therefore, if this condition is not met, the original processing is temporarily interrupted and the processing is restarted after making it possible to read 4*. At this time, in the case of this method,
Since the processes for 0* to 3* that have already been read are carried out in advance, up to cycle 1 in FIG. 4 is completed. 4* at this time.

When it is detected that is the next page, the internal state at this point is saved in order to move on to the process of adjusting the conditions.
Thereafter, after performing processing to adjust the conditions, the saved internal state is restored and restarted from cycle 2.

According to this process, an instruction can be processed even if two pages of virtual memory do not exist in real memory at the same time. In addition, at this time, as described above, as long as the instructions are read in time for the execution cycle, the instructions can be executed without having to prepare all of the - instructions.

Furthermore, the system of the present invention has the feature that the instruction format can be easily expanded. That is, in the conventional method of executing instructions after all the instructions have been prepared, in order to process the instructions in a certain synchronized sequence, it is required that the instructions be formatted in accordance with a specific convention. Therefore, it has been extremely difficult to implement an instruction having a format that does not follow this because the logic becomes complicated, but the system of the present invention can flexibly deal with such situations. for example,
An instruction in the format of instruction 1 shown in FIG. 5(a), an instruction in which the order of BXD and R1R8 is reversed, or an instruction in the format of instruction 2 shown in FIG. 5('0) When an instruction in which the mask information M part is doubled (to 2 bytes) is required, the system of the present invention can be implemented by simply rewriting the same content in the control storage device. Also,
In addition to the above, changes in instruction length and number of operands can be easily accommodated.

〔Effect of the invention〕

As explained above in detail, according to the method of the present invention,
r! 'J High-speed processing due to clean control? The effect is great because a promising pipeline information processing device can be easily realized with a small amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of an instruction aligner and an instruction division/extraction unit, and FIG. 3 is a diagram showing an example of the configuration of a multiplexer. Figure 4 shows an example of the actual configuration of a multiplexer circuit.
6 is a diagram showing the format of the command, FIG. 6 is a diagram showing the format of the output of the command aligner, and FIG. 7 is a time chart. 1...Storage device, 2...Instruction aligner, 3...Instruction sequence control unit, 4.
... Control storage device, 5 ... Instruction division fetching section, 6 ... BXD calculation section, 7 ...
...ADR calculation unit, 8...Address conversion unit, 9...Arithmetic unit, 10...Adder, 11...IBP value 12...Multiplexer 1
3~16...Buffer, 17~20...
...Validity display flag, 21.21'...Data bus, 22-24...Multiplexer circuit, 25...+1 circuit, 26... +
2 circuits, 27...AND circuits (,-1,'
1.1 Fig. 7 Fig. 2 Fig. 3 Fig. 4 Fig. 5 (cL) (b) Fig. 6

Claims (1)

[Claims] In an information processing device configured to perform processing related to instruction execution using a pipeline method, there is a register that holds the address value of the starting position of a part that should be divided and extracted from one instruction, and the contents and control of the register. means for adding the value given by the register and storing the result in the register; means for dividing and retrieving the instruction read from the storage device using the value of the register; means for detecting whether all the elements necessary for execution have been read from the storage device, and processing the instruction by dividing it into parts necessary for execution at that time; An instruction division processing method characterized in that the instruction execution sequence is changed depending on whether all elements necessary for executing the instruction have been read from a storage device.