JPS61146961U - - Google Patents
Info
- Publication number
- JPS61146961U JPS61146961U JP2784986U JP2784986U JPS61146961U JP S61146961 U JPS61146961 U JP S61146961U JP 2784986 U JP2784986 U JP 2784986U JP 2784986 U JP2784986 U JP 2784986U JP S61146961 U JPS61146961 U JP S61146961U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- master slice
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は、本考案によるアナログマスタスライ
スＩＣにおける各素子の配列を示す要部平面図で
ある。第２図は、第１図に示された小電流用ＮＰ
Ｎトランジスタと大電流用ＮＰＮトランジスタの
平面図と断面図で、イ，ロは小電流用ＮＰＮトラ
ンジスタ、ハ，ニは大電流用ＮＰＮトランジスタ
を夫々示す。
図において、１は基板、２はクロスアンダ素子
、３はワイヤボンデイングパツド、４は大電流用
ＮＰＮトランジスタ、７…は抵抗、８…は小電流
用ＮＰＮトランジスタ、９，９′はコレクタ電極
、１０，１０′はベース電極、１１，１２，１２
′はエミツタ電極、ＥＳ１，ＥＳ２，ＥＳ２′は
エミツタ面積である。
FIG. 1 is a plan view of essential parts showing the arrangement of each element in an analog master slice IC according to the present invention. Figure 2 shows the small current NP shown in Figure 1.
2A and 2B are plan views and cross-sectional views of an N transistor and a large current NPN transistor, where A and B show small current NPN transistors, and C and D show large current NPN transistors, respectively. In the figure, 1 is a substrate, 2 is a cross-under element, 3 is a wire bonding pad, 4 is a large current NPN transistor, 7... is a resistor, 8... is a small current NPN transistor, 9 and 9' are collector electrodes, 10, 10' are base electrodes, 11, 12, 12
' is an emitter electrode, and ES 1 , ES 2 , ES 2 ' are emitter areas.
Claims (1)
の夫々のエミツタ面積比が整数倍となるように構
成されていることを特徴とするアナログマスタス
ライス半導体集積回路装置。 (2) 前記トランジスタのうち、大電流用のトラ
ンジスタをワイヤボンデイングパツドの近くに配
置したことを特徴とする実用新案登録請求の範囲
第(1)項記載のアナログマスタスライス半導体集
積回路装置。[Claims for Utility Model Registration] (1) An analog master slice semiconductor integrated circuit device characterized in that the emitter area ratio of each of a plurality of transistors formed on a chip is an integral multiple. (2) The analog master slice semiconductor integrated circuit device according to claim 1, wherein a high current transistor among the transistors is arranged near a wire bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2784986U JPS61146961U (en) | 1986-02-27 | 1986-02-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2784986U JPS61146961U (en) | 1986-02-27 | 1986-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61146961U true JPS61146961U (en) | 1986-09-10 |
Family
ID=30525183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2784986U Pending JPS61146961U (en) | 1986-02-27 | 1986-02-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61146961U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101281A (en) * | 1978-01-26 | 1979-08-09 | Nec Corp | Logic circuit |
-
1986
- 1986-02-27 JP JP2784986U patent/JPS61146961U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101281A (en) * | 1978-01-26 | 1979-08-09 | Nec Corp | Logic circuit |