JPS6114690A - Image display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image display method for displaying character patterns and the like on an image display device of a personal computer, for example.

BACKGROUND ART In the conventional image display system using a personal computer IC, the entire screen is controlled by one image position control circuit (CRT controller). In detail, the address of the text memory has a one-to-one correspondence with the address of the screen of the display device, and the CRT controller sequentially accesses the previous 8 text memory. Stored in
) was displaying text data.

In such prior art, when trying to move a character pattern displayed in an area of the screen to the right,
Character pattern you want to move to the address you want to move?
It needed to be rewritten. Therefore, there is a drawback that the processing time becomes long, and the text address for rewriting the contents of the text memory is complicated, making it difficult to manage software.

Objective VI of the present invention is to be able to selectively move one display area divided into a plurality of image display areas to the remaining display area easily and at high speed, and to An object of the present invention is to provide an image display method that can always display an image at a predetermined position.

Example FIG. 1 is a block diagram of one embodiment of the present invention.

The horizontal scanning address signal and vertical scanning address signal from counter 1 are transmitted to control circuits Sl, S2 . ....

Snl can't give each one. This control circuit Sl.

S2. . . , 5nVi As shown in FIG. 2, the text random access memory 2 (hereinafter referred to as text RAM) is divided into a plurality of storage areas Bl.

B2. . . , Bn, and controls the screen. The control circuit 81 has a horizontal scanning position register 3 and a vertical scanning position register 4, and is a central processing unit (hereinafter referred to as CPU). The control circuit 51Vi also includes a horizontal scanning shape register 30 and a vertical scanning shape register 31.

This register 30 is given a horizontal display period from the display start address position, and the register 31 is given a vertical display period. Furthermore, the control circuit S1
It has a horizontal scan start register 40 and a vertical scan start register 41 for setting which dot in the display area to start displaying, and initial values for display start are given by the CPU.

Active signal generation [Horizontal scanning address signal and vertical scanning address signal derived from the counter 1 and the display start address set in the register 3.41? When the comparison is made and the two match, the text address generation circuit 7 is placed in position 1.

This text address generation circuit 7 registers 30°31
The register 40 is activated only for the display period set to
．． A text address based on the initial @1 given to 41 is given to selector 8 via line 9a', and a block raster address is given to selector 1 via line 9bft.
Give 01. Note that the block raster address here refers to the control circuit Sl.

S2. . . , indicates the number of dots from the display start position in each display area of the image display surface managed by Sn.

Control circuit S2. ..., Sn also has the same configuration as the control circuit S1, and sends the text address and block raster address to the selector 8 and selector l, respectively.
Give to O. Line 11 in selector 8? The control circuits Sl, S2 .・
..., all text addresses from Sn are selected and derived to the selector 13.

This selector 131 also receives no address signal from the central processing unit via the address bus line 14 for accessing the text RAM2k.

The address signal from the selector 13 is sent to the text RAM 21.
This gives me strength. It is also given to an attribute random access memory 15 (hereinafter referred to as attribute RAM). The text RAM 2 receives the address signal from the selector 13, reads out the information in the store area corresponding to this address IC, and supplies it to the character generator 16. A character generator 16Vi is given a raster address from selector 0, and by kneading, it supplies video signals for displaying a character corresponding to the information from the text RAM 2 to game consoles 17, 18, and 19, respectively. AND gates 17, 18, and 19 take the logic 8 of the character video signal and the color signal from the attribute RAM 15, and the AND gate 17 produces a red signal, and the AND gate 18 produces a green signal, and the AND gate ]9 produces a red signal. When the blue signal is led to the video processing circuit 20, the video processing circuit 20 is not activated and a desired image is not displayed on the display surface of the cathode ray tube 21.

Figure fA3 is a diagram showing the display mode on the display screen of the cathode ray tube 21. Reference point 0 for horizontal scanning position and vertical scanning position
(0,0) Specified in the upper left corner on the screen of the t-tffia diagram. Sequential scanning lines starting from the upper left corner/1. A desired image is displayed on the image plane A of the cathode ray tube 21 by sequentially scanning the image plane A of the cathode ray tube 21.

The relationship between one display area Ap divided into a plurality of screen A and the display portions within that display area Ap is not shown in FIG. Display portion Kl in display area Ap (r display area Ap
It is assumed that the character pattern C1i is displayed in a predetermined display portion KO, that is, a case is assumed in which one character pattern C1i is displayed in the display portion KO. Note that the vertex ep of 1 display area Ap
Let the coordinates of be (xp, yp). In addition, the coordinates of vertex e1 of 1 are (xel, Yel) in the display area, and the coordinates of vertex f1 k
(xel+l (1, yel) coordinate k of vertex gl (x
e 1 + H1, y e 1 + v 1 ) vertex h
Let the coordinates of 1 be 'r(xe]+yel+vl). First, 1 display area A I) The horizontal direction display start address rx is sent from the CPU to the register 3P in the control circuit Sp that manages lr.
pJ is given. Also, register 4 in the control circuit Sp
The vertical direction display start address ryp cannot be given to p by the CPU. The register 30p1 in the control circuit Sp is given data rHIJ that determines the display period in the horizontal direction,
Register 31. The data "V" indicating the display period in the vertical direction is displayed. 1jrxelJ is in the register 40p in the control 1st path Sp, and the register 4 is in the trench.
1 p Ic trJ r yellow is given. 1 [scan address signal from counter l and registers 3p, 4
Display start address rxpJ, rypJ
When they match, the text address generation circuit changes to the oil side only in the range of July display period [HIJ, rVIJ.

In addition, at this time, the coordinates of the display start address position (xp, y
p) Corresponds to ke (xel, yel).

In other words, start displaying one display area.
All addresses of M2 are set as initial values, and after υ, consecutive addresses from this address are lost.

In this X direction (xel, yel), rl in the horizontal direction
llJ, vertical direction only ``■】'', i! By outputting the consecutive addresses, the character pattern c1 of 1 is displayed in the display part KO in the ↓ uni display part shown in the third figure.

Vertex e 2 (x e 2. y e 2 )'? If the character pattern C2i is to be displayed in the display portion KO of the same size, rxeZJ is given to the register 40p and rye2 is given to the register 41p.

In addition, when moving the display head Apr to another display area Aq, the vertex eq of the 0 display area Aq is (xq.

yq), the display contents of 1 display area Ap are stored. The horizontal direction display start address rxqJ is stored in the register 3p in the control circuit Sp that manages the store area Bp.
Also, the vertical direction display start address ry Q is stored in register 4p.
Icx forces you to do what J cannot give.

As described above, according to the present invention, it is possible to selectively move one display area divided into multiple parts of one image display surface to the remaining display area easily and at high speed, and moreover, the display area can be moved easily and at high speed. It becomes possible to always display a partial display at a predetermined position within the screen.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of the text RAM 2, FIG. 3 is a diagram showing the display mode of the display screen of the cathode ray tube 21, and FIG. 4 is a diagram showing the display area Ap. It is an enlarged view of. l...Counter, 2...Text random access memory, 3-3n, 4 . . .-4n, 30. ~30n,
31-31n, 40. −． 40n. 41,-. 41n...Register, 6...Active signal generation circuit, 7...Text address generation circuit, 2
1... Cathode ray tube, S], ~, Sn... control] l path,
B】~, Bn... Store area agent Patent attorney Kei Nishi C'2 ) \hl (xel, yel+1) K2 Figure 4

Claims (1)

[Scope of Claims] Scanning address signal deriving means for deriving signals representing a horizontal scanning address position and a vertical scanning address position of one display screen, and display contents displayed in display areas divided into smaller areas than the display screen. a memory comprising a storage area in which each of the addressed areas is stored; addressing means for addressing the display area to a position to be displayed on the display screen; and means for specifying a display period to be displayed; means for specifying a display start address within the display area, and the display content in the store area corresponding to each divided display area is within the display area corresponding to the specified address and within the specified address. An image display method characterized by displaying from a display start address and selectively displaying a display portion within a display area.