JPS6114688A - Image display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image display method for displaying character patterns and the like on an image display device of a personal computer, for example.

BACKGROUND ART In a conventional image display system using a personal computer, one image position control circuit (CRT controller) controls the entirety of both sides. To be more specific, the address of the text memory has a one-to-one correspondence with the address of the screen of the display device, and the CRT controller sequentially accesses the text memory to store the data on the screen of the display device in the memory. was displaying text data.

In such prior art, when attempting to move a character pattern displayed in an area of the screen to the right, it was necessary to rewrite the character pattern to be moved to the address to be moved. Therefore, there is a drawback that the processing time becomes long, and the text address for rewriting the contents of the text memory is complicated, making it difficult to manage software.

Purpose An object of the present invention is to make it possible to selectively move one display area divided into a plurality of image display areas to the remaining display areas easily and at high speed, and to arbitrarily change the shape of the display area. It is an object of the present invention to provide an I-image display method that can be set.

Example FIG. 1 is a block diagram of one embodiment of the present invention.

The horizontal scanning address signal and the direct scanning address signal from the KAKUNTAR 1 are transmitted to the control circuits Sl, S2. ....

are given to Sn respectively. This control circuit Sl.

S2. . . 5nij, as shown in FIG. 2, a store area Bl that is divided into a plurality of parts of the text random access memory 2 (hereinafter referred to as text RAM).

B2. . . , Bn, respectively, and are provided to control the screen. The control circuit 5IV has a horizontal scanning shape register 3 and a vertical scanning position register 4, and has a central processing unit (not shown).
It has a register 30 for horizontal scanning shape and a register 31 for vertical scanning shape, and the display period in the horizontal and half directions from the display start address position is given to this register 30.31. The active signal generation circuit 6 compares the horizontal scanning address signal and the vertical address signal derived from the kakunta 1 with the display start address set in the registers 3 and 4, and when the two match, the text address generation times II & 7 are started. Fi! , be animated. This text address occurrence time 1 @ 7Vi, register 30.31
is activated only for the display period set to derive text addresses and glock cluster addresses.

Selector 8 is provided with a text address via line 9a, and selector IOK is provided with a glock raster address via line 9b. It should be noted that here, the Glock raster address and the control circuits Sl, S2 . ...
This indicates the number of dots from the display start position in each display area of the image display surface managed by SnK.

Control circuit S2. ...Sn is also used to have the same configuration as the control circuit S1, and the text address and the clock raster address are sent to the selector 8 and selector IO, respectively.
Give K. In selector 8, control circuits Sl, S2 .・・・
・Select the text address from Sn and press selector 1
3. This selector 13 is also connected to a text RAM 2 from the central processing unit via an address bus line 14.
An address signal is given to access the . The address signal from selector 13 is given to text RAM 2. Also attribute random access memory 1
5 (hereinafter referred to as attribute RAM).

The text RAM 2 receives the address signal from the selector 13, sequentially outputs information on the store area corresponding to this address, and supplies it to the character generator 16. The character generator 16Vi and the selector 1o are given the last address, and the video signals for displaying the character corresponding to the information from the text RAM 2 are given to the computer games 17, 18 and 19, respectively.

AND gates 17, 18 and 19 perform the logical product of the character video signal and the color signal from the attribute RAM 15, and the AND gate 17 outputs the red signal, the AND gate 18 outputs the green signal, and the AND gate 19 outputs the blue signal. This video processing (b) is guided to the processing circuit 20.
The fNI 20 is activated and a desired image is displayed on the display surface of the cathode ray tube 21.

FIG. 3 is a diagram showing the relationship between the display screen of the cathode ray tube 21, the horizontal scanning position register 3, and the block display position according to the vertical scanning position register 4.

Reference point 0 (0°o) for horizontal scanning position and vertical scanning position
V'i is defined in the upper left corner of the screen in FIG. Scanning lines/1, 12 and below are sequentially scanned from the upper left corner to the cathode ray tube 21.
A desired image is displayed on image plane A of . One display area Ap divided into a plurality of planes A is divided into another display area Aq
Assume that you move to Note that the coordinates of the vertex ep of the display area JJEAp are (xp, yp), and the coordinates of the vertex fp are (
xp ten HP.

yp), the coordinates of the river fish gp are (xp + Hp, yp + Vp)
, the coordinates of the vertex hp are (xp, yp+Vp). Also, the coordinates of the vertex eq of the display area Aq are (xqpyq), and the coordinates of the point fq are (xq+HQ).

yq), coordinates of vertex gq as (xq+Hq, yq+Vq)
, the coordinates of the 1st point hq are (xq, yq+Vq). In moving display area Ap to display area Aq,
Text R in which the display contents of the display area Ap are stored
Control @1 circuit S that manages store f#41tBp of AM2
The horizontal direction display start address rxqJ is given from the register (register p)3pKCPU. -! From register 4pKCPU in control circuit Sp to vertical direction display N start address r
yqJ is given. Register 30p in control circuit Sp
is given data rHqJ indicating the horizontal display period, and the register 31pVC is given data rVqJ indicating the vertical display period. Horizontal scanning address signal and vertical scanning address signal from Kakunta 1 and display start address rxqJ, r set in register 3p*4p
yqJ, the text address generating circuit 7p is activated for a display period rHqj in the horizontal direction and for a display period rVqJ in the vertical direction. The text address from the text address generation circuit 7p is applied to the character generator 16 via the selector 8.13 and the store input jJEBp of the text RAM 2. Further, the block rask address is given to the character generator 16 via the selector IO. Therefore, on the screen A of the cathode ray tube 21, the coordinates of the display start position are converted from ep (xp, yp) to eq (xq, yq)K, and become eq (xq + yq
) and the display area Aq is displayed. In this way, by rewriting the two values of the horizontal scanning position register and the vertical scanning position register, it becomes possible to arbitrarily move the display area to a desired position.

Display t14M is also performed by rewriting the two values of the horizontal scanning shape register and the direct scanning shape register.

The ability of t3 is to arbitrarily set the shape of .

Effects As described above, according to the present invention, one divided display f# area of 11 image display can be selectively moved easily and at high speed to the remaining display area with simple operation and at high speed. Moreover, the shape of the display area can be set as desired.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the text random access memory 2, and FIG. 3 is a diagram showing the state of movement of the display area on the display surface of the Fi cathode ray tube 21. . 1...Kakunta, 2...Text random access memory, 30~. 30n, 31-31n...Register, 6...Active number h generation circuit, 7...Text address generation circuit, 21...Cathode ray tube, 81-
Sn...Control circuit, B1~Bn...Store area agent Patent attorney Kei Nishi - Figure 3

Claims (1)

[Scope of Claims] Scanning address signal deriving means for deriving signals representing a horizontal scanning address position and a vertical scanning address position of one display screen, and a display displayed in a display area divided into smaller areas than the display screen. a memory comprising a storage area in which contents are respectively stored; addressing means for addressing the display area to a position to be displayed on the display screen; and means for specifying a display period to be displayed; An image display method characterized in that display contents in a store area corresponding to each divided display area are displayed from the specified address position for the specified display period.