JPS61145870A - Thin-film field effect transistor and manufacture thereof - Google Patents
Thin-film field effect transistor and manufacture thereofInfo
- Publication number
- JPS61145870A JPS61145870A JP26908784A JP26908784A JPS61145870A JP S61145870 A JPS61145870 A JP S61145870A JP 26908784 A JP26908784 A JP 26908784A JP 26908784 A JP26908784 A JP 26908784A JP S61145870 A JPS61145870 A JP S61145870A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin film
- semiconductor layer
- organic thin
- positive resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 30
- 230000005669 field effect Effects 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 21
- 229920001721 polyimide Polymers 0.000 abstract description 13
- 239000004642 Polyimide Substances 0.000 abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 7
- 239000010408 film Substances 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 230000007797 corrosion Effects 0.000 abstract description 3
- 238000005260 corrosion Methods 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 241001428214 Polyides Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920003051 synthetic elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、液晶等と組合せて画像表示装置を構成するた
めのシリコンを主成分とする非晶質シリコン半導体より
なる薄膜電界効果トランジスタ以後ＴＰＴと呼ぶ）およ
びその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a thin film field effect transistor (hereinafter referred to as TPT) made of an amorphous silicon semiconductor mainly composed of silicon and used in combination with a liquid crystal etc. to constitute an image display device. ) and its manufacturing method.
従来の技術 第３図に従来のＴＰＴの要部構成断面図を示す。Conventional technology FIG. 3 shows a sectional view of the main part of a conventional TPT.
ガラス等の絶縁基板１上にゲート電極なる第１の導電体
２が被着形成され、第１の絶縁層３を介して非晶質シリ
コン半導体層が形成され、前記半導体層のチャンネル部
上に窒化シリコン等からなる第２の絶縁層８が被着形成
され、さらにソース・ドレイン電極１７ａ、１７ｂがリ
ン等を添加した非晶質シリコン層１５を介して形成され
ている逆スタガー型ＴＰＴである。A first conductor 2 serving as a gate electrode is deposited on an insulating substrate 1 made of glass or the like, an amorphous silicon semiconductor layer is formed with a first insulating layer 3 interposed therebetween, and an amorphous silicon semiconductor layer is formed on the channel portion of the semiconductor layer. This is an inverted stagger type TPT in which a second insulating layer 8 made of silicon nitride or the like is deposited, and source/drain electrodes 17a and 17b are formed via an amorphous silicon layer 15 doped with phosphorus or the like. .
次に上述の構造をもつＴＰＴの製作工程について簡単に
説明する。まず、ガラス等の絶縁基板上にゲート電極な
る第１の金属層２を選択的に被着形成する。ついで全面
に第１の絶縁層３．非晶質シリコン半導体層４．窒化シ
リコン、酸化シリコン等からなる第２の絶縁層８を順次
被着する。この第２の絶縁層８は大気、液晶材料等に対
する保護、または不純物を含む非晶質シリコン層除去時
のチャンネル部保護を目的とするものである。次に前述
の第２の絶縁層８の一部をチャンネル部上に残した後に
、不純物を含む非晶質シリコン層を全面に被着する。そ
の後、第３図に示すように、非晶質シリコン半導体層お
よび不純物を含む非晶質シリコン層を島状にする。さら
に、ソース・ドレインを形成した後、第２の絶縁層上に
残つている不純物を含むシリコン層を除去して第３図に
示すＴＰＴが完成する。（特願昭５７−９５３４３）発
明が解決しようとする問題点
このような従来あ構造、材料のＴＰＴでは窒化シリコン
、酸化シリコン等からなる第２の絶縁層の除去工程にお
いてフッ酸系統のエツチング液を使用するために、第１
の非単結晶半導体層のピンホール等からエツチング液が
浸入して第１の絶縁膜の腐食およびゲート電極のバス配
線を切断するという不良を発生しやすかった。Next, the manufacturing process of the TPT having the above structure will be briefly explained. First, a first metal layer 2 serving as a gate electrode is selectively deposited on an insulating substrate such as glass. Next, a first insulating layer 3 is applied to the entire surface. Amorphous silicon semiconductor layer 4. A second insulating layer 8 made of silicon nitride, silicon oxide, etc. is successively deposited. The purpose of this second insulating layer 8 is to protect against the atmosphere, liquid crystal material, etc., or to protect a channel portion when removing an amorphous silicon layer containing impurities. Next, after leaving a portion of the second insulating layer 8 on the channel portion, an amorphous silicon layer containing impurities is deposited over the entire surface. Thereafter, as shown in FIG. 3, the amorphous silicon semiconductor layer and the amorphous silicon layer containing impurities are formed into an island shape. Furthermore, after forming the source and drain, the silicon layer containing impurities remaining on the second insulating layer is removed to complete the TPT shown in FIG. 3. (Patent Application No. 57-95343) Problems to be Solved by the Invention In the conventional structure and material of TPT, a hydrofluoric acid-based etching solution is not used in the process of removing the second insulating layer made of silicon nitride, silicon oxide, etc. In order to use
The etching solution penetrates through pinholes in the non-single crystal semiconductor layer, which tends to cause corrosion of the first insulating film and breakage of the gate electrode bus wiring.
本発明はかかる問題点に鑑みなされたもので、第２の絶
縁層として液晶等に不純物が溶は出すことのない有機薄
膜を使用することにより、ＴＰＴ作製工程における第１
の絶縁膜の腐食およびゲートバス配線切断の不良のない
ＴＰＴおよびその製造方法を提供することを目的として
いる。The present invention was made in view of this problem, and by using an organic thin film that does not dissolve impurities into the liquid crystal etc. as the second insulating layer, the first insulating layer in the TPT manufacturing process is
An object of the present invention is to provide a TPT which is free from defects such as corrosion of the insulating film and disconnection of gate bus wiring, and a method for manufacturing the same.
問題点を解決するための手段
本発明は上記問題点を解決するため第２の絶縁層の除去
工程におけるエツチング液に、半導体層。Means for Solving the Problems In order to solve the above problems, the present invention uses a semiconductor layer as an etching solution in the second insulating layer removal process.
第１の絶縁層、第１の金属層を腐食させない液が使用で
きるように、第２の絶縁層として有機薄膜を用いること
を特徴とする。A feature is that an organic thin film is used as the second insulating layer so that a liquid that does not corrode the first insulating layer and the first metal layer can be used.
作用
本発明は上記の技術的手段により、第２の絶縁層である
有機薄膜層の除去工程において第１の半導体層のピンホ
ールなどより有機薄膜のエツチング液が浸入したとして
も、第１の絶縁膜が腐食されることなく、さらにゲート
電極のバス゛配線が切断されることのない良好なＴＰＴ
を作製できる。Effect of the present invention By using the above-mentioned technical means, even if the etching solution for the organic thin film enters through a pinhole in the first semiconductor layer during the removal process of the organic thin film layer that is the second insulating layer, the first insulating layer can be removed. A good TPT that does not corrode the film and prevent the bus wiring of the gate electrode from being cut.
can be created.
実施例
第１図は本発明の一実施例であるＴＰＴの要部構成断面
図を示す。第１図において、１はガラス基板、２はモリ
ブデンゲート電極、３は窒化シリコン絶縁膜、４は非晶
質シリコン半導体層、６はリンを含む非晶質シリコン半
導体層、６はポリイばド、７ａ、７ｂはアルばニウムよ
りなるソース・ドレイン電極である。そのＴＰＴの工程
断面図を第２図に示す。まず第２図ａに示すように、ガ
ラス基板１上にゲート電極２を選択的に被着形成した後
に窒化シリコン絶縁膜３、非晶シリコン半導体層４１を
順次堆積し、さらにポリイミド６１を塗布する。つづい
て、ポジレジスト及びその現像液を使用して前述のポリ
イばドロ１の必要以外の部分を除去し、ポジレジストを
除いて第２図すに至る。その後、第２図Ｃに示すように
全面にリンを含む非晶質シリコン半導体層６１を堆積し
、第２図ｄに示すように非晶質シリコン半導体層４１と
リンを含む非晶質シリコン半導体層５１を島状に形成す
る。さらに第２図６に示すようにソース・ドレイン電極
７＆、７ｂを被着形成し、それをマスクにして、ボリイ
はドロ上に被着しているリンを含む非晶質シリコン半導
体層６２を除去して本発明によるＴＰＴが完成する。Embodiment FIG. 1 shows a sectional view of the main part of a TPT which is an embodiment of the present invention. In FIG. 1, 1 is a glass substrate, 2 is a molybdenum gate electrode, 3 is a silicon nitride insulating film, 4 is an amorphous silicon semiconductor layer, 6 is an amorphous silicon semiconductor layer containing phosphorus, 6 is a polyimide, Reference numerals 7a and 7b are source/drain electrodes made of aluminum. A cross-sectional view of the TPT process is shown in FIG. First, as shown in FIG. 2a, a gate electrode 2 is selectively deposited on a glass substrate 1, a silicon nitride insulating film 3 and an amorphous silicon semiconductor layer 41 are sequentially deposited, and polyimide 61 is further applied. . Subsequently, using a positive resist and its developer, unnecessary portions of the above-mentioned polyimide film 1 are removed, and the positive resist is removed, resulting in the process shown in FIG. Thereafter, as shown in FIG. 2C, an amorphous silicon semiconductor layer 61 containing phosphorus is deposited on the entire surface, and as shown in FIG. The layer 51 is formed into an island shape. Furthermore, as shown in FIG. 2, source/drain electrodes 7&, 7b are deposited and, using these as a mask, the amorphous silicon semiconductor layer 62 containing phosphorus deposited on the electrode is removed. Thus, the TPT according to the present invention is completed.
本実施例によれば、ポリイミドの選択的な除去にポジレ
ジスト用現像液を使用できるために、ポジレジスト現像
と同時にボリイばドを除去でキルという利点を有し、さ
らにポジレジスト現像液が非晶質シリコン半導体層４１
のピンホールなどをとおして侵入しても窒化シリコン３
を腐食することなく、ゲート電極２のバス配線を切断す
ることもない。According to this embodiment, since the positive resist developer can be used to selectively remove polyimide, there is an advantage that the polyimide can be removed and killed at the same time as the positive resist development, and furthermore, the positive resist developer is Crystalline silicon semiconductor layer 41
Silicon nitride 3
The bus wiring of the gate electrode 2 is not cut off without corroding the gate electrode 2.
また、ポリイミドは３００℃の雰囲気下でも形状変化等
の劣化がないことから、リンを含む非晶質シリコン半導
体層を２００℃〜３００℃の比較的高温で堆積できるた
めに、非晶質シリコン半導体層との良好なオータックコ
ンタクトが得られて、その信頼性向上がはかれる。また
ポリイミドは液晶により溶解されないために、液晶に対
するチャンネル部の保護としても有効である。In addition, since polyimide does not undergo deterioration such as shape change even in an atmosphere of 300°C, an amorphous silicon semiconductor layer containing phosphorus can be deposited at a relatively high temperature of 200°C to 300°C. Good auto-tack contact with the layer can be obtained, improving its reliability. Furthermore, since polyimide is not dissolved by liquid crystal, it is also effective in protecting the channel portion against liquid crystal.
さらに、従来のＴＰＴの第２の絶縁層として使用した窒
化シリコン、酸化シリコン等の無機物質の被着方法より
もポリイばド等の有機薄膜の方がより容易であるために
コストダウン、製作量産性にすぐれる。Furthermore, since organic thin films such as polyide are easier to deposit than inorganic materials such as silicon nitride and silicon oxide used as the second insulating layer of conventional TPT, costs can be reduced and mass production is possible. Excellent sex.
次に本発明の他の実施例について説明する。この実施例
では前述の実施例で使用したポリイミドの代わりに感光
性の日本合成ゴム（株）製ＪＳＲを用いる。本実施例に
よれば、ＪＳＨの必要以外の部分の除去工程においてレ
ジストを使用する必要がない。従って、前述の実施例に
加えてレジストの塗布および除去工程を簡略化できる利
点を有する。Next, other embodiments of the present invention will be described. In this example, photosensitive JSR manufactured by Japan Synthetic Rubber Co., Ltd. is used in place of the polyimide used in the previous example. According to this embodiment, there is no need to use resist in the process of removing unnecessary portions of JSH. Therefore, in addition to the above-described embodiments, this embodiment has the advantage that the resist coating and removal steps can be simplified.
第４図は本発明の他の実施例であるＴＰＴの要部構成断
面図である。本実施例は、図に示すごとく、有機薄膜層
であるポリイミド１６をゲート電極２と同一の形状で被
着形成することにより、チャンネル部におけるソース・
ドレイン電極２８ａ。FIG. 4 is a sectional view of the main part of a TPT according to another embodiment of the present invention. In this embodiment, as shown in the figure, a polyimide layer 16, which is an organic thin film layer, is deposited in the same shape as the gate electrode 2, so that the source and
Drain electrode 28a.
２８ｂとゲート電極２との重なりによって生じる奇生容
量を減少させるのに有効であり、その結果、ＴＦＴのス
イッチ動作特性が向上する。This is effective in reducing the parasitic capacitance caused by the overlap between the gate electrode 28b and the gate electrode 2, and as a result, the switching characteristics of the TFT are improved.
なお、以上実施例は半導体層として非晶質シリコンを用
いたＴＰＴを中心に説明したが、本発明は微結晶シリコ
ン、多結晶シリコン、単結晶シリコン等のシリコン全般
を半導体層として用いたＴＰＴに適用できる。Although the above embodiments have mainly been described with respect to TPTs using amorphous silicon as the semiconductor layer, the present invention is applicable to TPTs using any type of silicon such as microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. as the semiconductor layer. Applicable.
発明の効果
以上述べてきたように、本発明は不純物を含む半導体層
の除去工程等におけるＴＰＴのチャンネル部保護に液晶
等に溶は出すことがなく、又耐熱性を有する有機薄膜を
用いることにより、そのエツチング液に有機溶剤の使用
が可能となり、従って、半導体層のピンホールなどをと
おしてエツチング液が浸入して第１の絶縁層を腐食しゲ
ートバス配線を切断することなく良好なＴＰＴを作製で
きる効果を有する。また、誘電率の小さい有機薄膜を使
用することにより、ソース・ドレイン電極とゲート電極
の重なりによる奇生容量が小さくなり、ＴＰＴのスイッ
チ動作特性を向上させる効果をも有する。Effects of the Invention As described above, the present invention protects the channel portion of TPT during the process of removing semiconductor layers containing impurities by using an organic thin film that does not dissolve into liquid crystals and has heat resistance. , it is now possible to use an organic solvent in the etching solution, and therefore a good TPT can be obtained without the etching solution penetrating through pinholes in the semiconductor layer, corroding the first insulating layer, and cutting the gate bus wiring. It has an effect that can be created. Furthermore, by using an organic thin film with a low dielectric constant, the parasitic capacitance caused by the overlap between the source/drain electrode and the gate electrode is reduced, which also has the effect of improving the switching characteristics of the TPT.
第１図、第４図は本発明の実施例におけるＴＰＴの要部
構成断面図、第２図（ａ）〜（５）はそのＴＰＴの工程
断面図、第３図は従来のＴＰＴの構造断面図である。
１・・・・・・ガラス基板、２・・・・・・ゲート電極
、３・・・・・・絶縁薄膜層、４，４１・・・・・・非
晶質シリコン半導体層、５，５１．５２，１５．２５・
・・・・・不純物を含む非晶質シリコン半導体層、６，
６１．１６・・・・・・有機薄膜層、７ａ 、７ｂ 、
２Ｔ＆ 、２７ｂ−山−・ソース・ドレイン電極、８・
・・・・・第２の絶縁層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名ＣＪ
、６ ０
憾 ｄ 、
−へ 寸ｑFigures 1 and 4 are cross-sectional views of the main parts of a TPT according to an embodiment of the present invention, Figures 2 (a) to (5) are process cross-sectional views of the TPT, and Figure 3 is a structural cross-section of a conventional TPT. It is a diagram. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Gate electrode, 3... Insulating thin film layer, 4, 41... Amorphous silicon semiconductor layer, 5, 51 .52, 15.25・
...Amorphous silicon semiconductor layer containing impurities, 6,
61.16...Organic thin film layer, 7a, 7b,
2T&, 27b-mountain-source/drain electrode, 8.
...Second insulating layer. Name of agent: Patent attorney Toshio Nakao and one other person CJ, 60 d,
-to sizeq
Claims (5)
され、絶縁薄膜層を介してシリコンを主成分とする第１
の半導体層が前記第１の導電体層と一部重り合う様に選
択的に形成され、有機薄膜層が前記第１の導電体層と前
記第１の半導体層とに一部重り合う様に選択的に形成さ
れ、第２の導電体層が不純物を含むシリコンを主成分と
する第２の半導体層を介して前記有機薄膜層と前記第１
の半導体層と一部重り合う様に選択的に形成されている
ことを特徴とする薄膜電界効果トランジスタ。(1) A first conductor layer is selectively formed on one main surface of the substrate, and a first conductor layer mainly composed of silicon is formed through an insulating thin film layer.
a semiconductor layer is selectively formed so as to partially overlap the first conductor layer, and an organic thin film layer is formed so as to partially overlap the first conductor layer and the first semiconductor layer. A second conductive layer is formed selectively and connects the organic thin film layer and the first semiconductor layer through a second semiconductor layer mainly composed of silicon containing impurities.
A thin film field effect transistor characterized in that it is formed selectively so as to partially overlap with a semiconductor layer.
る特許請求の範囲第１項記載の薄膜電界効果トランジス
タ。(2) The thin film field effect transistor according to claim 1, wherein the organic thin film layer has heat resistance.
る特許請求の範囲第１項記載の薄膜電界効果トランジス
タ。(3) The thin film field effect transistor according to claim 1, wherein the organic thin film layer is photosensitive.
の形状の一部と整合して形成されていることを特徴とす
る特許請求の範囲第１項記載の薄膜電界効果トランジス
タ。(4) The thin film field effect transistor according to claim 1, wherein the organic thin film layer is formed to match a part of the shape of the selectively formed first conductor layer. .
と、全面に第１の絶縁薄膜層、第１の半導体層、有機薄
膜層を順次形成する工程と、前記第１の導電体層の一部
とに重なる様に前記有機薄膜層を選択的に残し他を除去
する工程と、全面に不純物を含む半導体層を形成する工
程と、残存している前記有機薄膜層を含む前記半導体層
および前記不純物を含む半導体層とを島状に形成する工
程と、前記残存している有機薄膜層の一部と前記不純物
を含む半導体層の一部に重なり合う様に第２の導電体層
を選択的に被着形成する工程と、前記有機薄膜層上に被
着している前記不純物を含む半導体層を除去する工程と
を有する薄膜電界効果トランジスタの製造方法。(5) a step of selectively forming a first conductor layer on the substrate; a step of sequentially forming a first insulating thin film layer, a first semiconductor layer, and an organic thin film layer on the entire surface; The method includes a step of selectively leaving the organic thin film layer so as to overlap with a part of the conductor layer and removing the others, a step of forming a semiconductor layer containing impurities on the entire surface, and a step of removing the remaining organic thin film layer. forming the semiconductor layer and the impurity-containing semiconductor layer into an island shape; and forming a second conductor so as to overlap a part of the remaining organic thin film layer and a part of the impurity-containing semiconductor layer. A method for manufacturing a thin film field effect transistor, comprising the steps of selectively depositing a layer and removing the impurity-containing semiconductor layer deposited on the organic thin film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59269087A JPH0695574B2 (en) | 1984-12-19 | 1984-12-19 | Method of manufacturing thin film field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59269087A JPH0695574B2 (en) | 1984-12-19 | 1984-12-19 | Method of manufacturing thin film field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61145870A true JPS61145870A (en) | 1986-07-03 |
| JPH0695574B2 JPH0695574B2 (en) | 1994-11-24 |
Family
ID=17467484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59269087A Expired - Fee Related JPH0695574B2 (en) | 1984-12-19 | 1984-12-19 | Method of manufacturing thin film field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0695574B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4956680A (en) * | 1986-12-22 | 1990-09-11 | Seiko Instruments Inc. | Thin film transistor |
| JPH02118954U (en) * | 1989-03-10 | 1990-09-25 | ||
| JPH03295275A (en) * | 1990-04-13 | 1991-12-26 | Fuji Xerox Co Ltd | Thin film transistor |
| KR100529569B1 (en) * | 1997-12-09 | 2006-02-08 | 삼성전자주식회사 | Manufacturing method of thin film transistor for liquid crystal display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212177A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
| JPS5954270A (en) * | 1982-09-21 | 1984-03-29 | Sanyo Electric Co Ltd | Field effect transistor |
| JPS59113667A (en) * | 1982-12-20 | 1984-06-30 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS59136971A (en) * | 1983-01-26 | 1984-08-06 | Toshiba Corp | Manufacture of thin-film field-effect transistor |
-
1984
- 1984-12-19 JP JP59269087A patent/JPH0695574B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212177A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
| JPS5954270A (en) * | 1982-09-21 | 1984-03-29 | Sanyo Electric Co Ltd | Field effect transistor |
| JPS59113667A (en) * | 1982-12-20 | 1984-06-30 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS59136971A (en) * | 1983-01-26 | 1984-08-06 | Toshiba Corp | Manufacture of thin-film field-effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4956680A (en) * | 1986-12-22 | 1990-09-11 | Seiko Instruments Inc. | Thin film transistor |
| JPH02118954U (en) * | 1989-03-10 | 1990-09-25 | ||
| JPH03295275A (en) * | 1990-04-13 | 1991-12-26 | Fuji Xerox Co Ltd | Thin film transistor |
| KR100529569B1 (en) * | 1997-12-09 | 2006-02-08 | 삼성전자주식회사 | Manufacturing method of thin film transistor for liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0695574B2 (en) | 1994-11-24 |
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| LAPS | Cancellation because of no payment of annual fees |