JPS61145846A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61145846A
JPS61145846A JP27011184A JP27011184A JPS61145846A JP S61145846 A JPS61145846 A JP S61145846A JP 27011184 A JP27011184 A JP 27011184A JP 27011184 A JP27011184 A JP 27011184A JP S61145846 A JPS61145846 A JP S61145846A
Authority
JP
Japan
Prior art keywords
hole
ion beam
electrode material
focused ion
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27011184A
Other languages
Japanese (ja)
Inventor
Satoshi Hirose
広瀬 諭
Shigeru Takahara
茂 高原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP27011184A priority Critical patent/JPS61145846A/en
Publication of JPS61145846A publication Critical patent/JPS61145846A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To bury simply a through hole with electrode material according to the depth of the hole and to reduce surface step difference after the burying of the hole, by utilizing focused ion beam deposition in a process for burying the though hole with the electrode material. CONSTITUTION:Focused ion beam deposition is a method that can ionize material, that is, electrode material in a vacuum or under a low gas pressure, focus the ion beam with an electromagnetic lens and irradiate it selectively on a semiconductor substrate to be deposited. Since the focused ion beam deposition can freely alter energy focusing density and set selectively it, range, speed and thickness, etc., of electrode material deposition can be arbitrarily controlled. Accordingly, by applying the focused ion beam deposition, energy focusing density and irradiation time of the ion beam can be controlled to bury a through hole with electrode material flatly according to the depth and area of the hole.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関し、特に多層構造
三次元半導体回路素子などにあって、上層、下層の各回
路素子相互間のコンタクト形成方法に係るものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming contacts between upper and lower layer circuit elements in multilayer three-dimensional semiconductor circuit elements. This is related to.

〔従来の技術〕[Conventional technology]

従来例によるこの種の2層構造半導体回路装置の概要構
成を第3図に示す、すなわち、この第3図構成において
、符号lはP形シリコン半導体基板、2a 、 2bは
フィールド酸化膜、絶縁酸化膜であり、3はソース領域
となるN形半導体層、4はドレイン領域となるN形半導
体層、5はゲート電極であって、配線材料層(例えばド
ープドポリシリコンM)6と共に、ご覧ではNO; )
ランジスタとしての下層の回路素子Aを形成している。
FIG. 3 shows a schematic configuration of a conventional two-layer semiconductor circuit device of this type. In the configuration shown in FIG. 3 is an N-type semiconductor layer which becomes a source region, 4 is an N-type semiconductor layer which becomes a drain region, 5 is a gate electrode, and together with a wiring material layer (for example, doped polysilicon M) 6, as shown in FIG. NO;)
It forms a lower layer circuit element A as a transistor.

そしてまた7は層間絶縁膜(例えばSiO□M)、8は
絶縁酸化膜、8はP形シリコン半導体層であり、10は
ソース領域となるN形半導体層、11はドレイン領域と
なるN形半導体層、12はゲート電極で、配線材料層(
例えばAl1.fi) 13と共に、同様にNO9)ラ
ンジスタとしての上層の回路素子日を形成しており、か
つ各配線材料層Ill、13の相手間は、層間絶縁膜7
のスルーホール14を通して埋込んだ導電材料層15と
、この導電材料層15へのコンタクト孔1Bを通した配
線材料層部分13aとにより接続させている。
Further, 7 is an interlayer insulating film (for example, SiO□M), 8 is an insulating oxide film, 8 is a P-type silicon semiconductor layer, 10 is an N-type semiconductor layer that becomes a source region, and 11 is an N-type semiconductor that becomes a drain region. The layer 12 is a gate electrode, and the wiring material layer (
For example, Al1. fi) Together with 13, similarly NO9) forms an upper layer circuit element as a transistor, and between each wiring material layer Ill, 13 is an interlayer insulating film 7.
A conductive material layer 15 buried through a through hole 14 is connected to a wiring material layer portion 13a through a contact hole 1B to the conductive material layer 15.

こ−でこの従来例構成の場合には、下層の回路素子Aを
形成させた上で、層間絶縁lI!7を形成して平坦化処
理し、ついで上層の回路素子Bを形成させ、その後、R
間絶縁膜7に配線材料層6に達するスルーホール14を
深く形成し、このスルーホール14に導電材料層15を
埋込み接続させてパターニングし、続いて絶縁酸化膜8
を堆積させると共に、この絶縁酸化W18に浅いコンタ
クト孔1Bをあけ、さらに配線材料層13を堆積させ、
かつその配線材料層部分13aでコンタクト孔IBを埋
込み接続させて構成するのである。
In the case of this conventional configuration, the lower layer circuit element A is formed and then the interlayer insulation lI! 7 is formed and planarized, then the upper layer circuit element B is formed, and then R
A through hole 14 reaching the wiring material layer 6 is deeply formed in the interlayer insulating film 7, a conductive material layer 15 is buried in the through hole 14 and connected and patterned, and then an insulating oxide film 8 is formed.
At the same time, a shallow contact hole 1B is formed in this insulating oxide W18, and a wiring material layer 13 is further deposited.
In addition, the contact hole IB is embedded and connected in the wiring material layer portion 13a.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながらこのような従来例方法の場合、上層、下層
の各回路素子間のスルーホールコンタクトのために、一
方では、深くあけられたスルーホールへの導電材料層の
堆積による埋込みと、そのパターニングのための写真製
版工程を経たエツチング工程とを必要として、製造工程
数が増加し、他方では、この深くあけられたスルーホー
ルへの導電材料層の接続とは異なる堆積条件、つまり比
較的浅いコンタクト孔への堆積による配線材料層の接続
をなさなければならず、また前者導電材料層の埋込みに
関しては、一様の厚さに堆積させることから、第4図に
見られるように、スルーホールの上部での導電材料層の
厚さが、エツチング後に表面段差となって残されて了う
などの1種々の問題点を有するものであった。
However, in the case of such a conventional method, in order to make through-hole contact between each circuit element in the upper layer and the lower layer, on the one hand, it is necessary to bury the deeply drilled through hole by depositing a conductive material layer and pattern it. This increases the number of manufacturing steps by requiring a photolithography process followed by an etching process, and on the other hand, the connection of the conductive material layer to this deep through hole requires different deposition conditions, i.e., a relatively shallow contact hole. The wiring material layer must be connected by the deposition of the conductive material layer, and since the former conductive material layer is deposited to a uniform thickness, as shown in Fig. 4, the upper part of the through hole is The conductive material layer has various problems, such as the thickness of the conductive material layer, which remains as a surface step after etching.

この発明方法は従来のこのような問題点を改善させるた
めになされたものであって、その目的とするところは、
例えば多層構造三次元半導体回路素子などにあって必要
とされるところの、場所により深さが大きく異なるスル
ーホールとしての穴への、電極材料による埋込みを、穴
の深さ対応に行なわせて、その形成を簡略化させると共
に、併せて形成後の表面段差を軽減し得るようにした半
導体装置の製造方法を提供することである。
This invention method was made to improve these conventional problems, and its purpose is to:
For example, through-holes, which are required in multi-layer three-dimensional semiconductor circuit elements, have a depth that varies greatly depending on the location, and are filled with electrode material in accordance with the depth of the hole. It is an object of the present invention to provide a method for manufacturing a semiconductor device that not only simplifies its formation, but also reduces surface steps after formation.

〔問題点を解決するための手段〕[Means for solving problems]

この発明方法においては、スルーホールへの電極材料の
穴埋めの光めの工程に、集束イオンビームデポジション
法を利用するものである。
In the method of this invention, a focused ion beam deposition method is used in the process of filling the through holes with electrode material.

この集束イオンビームデポジション技術は、物質、こへ
では電極材料物質を真空中、または低ガス圧下にあって
イオン化させ、この原子状のイオンビームを電磁レンズ
により集束し、半導体基板上に選択的に照射して堆積さ
せ得るもので、エネルギの集束密度を自由に変更して選
択設定できることから、電極材料堆積のための範囲、速
度、厚さなどのそれぞれを任意に制御し得るという利点
を有しており、この種の電極材料の堆積に好適する。因
みにこの集束イオンビームデポジションに関しては、解
説記事r高木俊宜・応用物理、U。
This focused ion beam deposition technology ionizes a substance, here the electrode material, in vacuum or under low gas pressure, and focuses this atomic ion beam using an electromagnetic lens to selectively deposit it onto a semiconductor substrate. The electrode material can be deposited by irradiating the electrode material, and the energy concentration density can be freely changed and set, so it has the advantage that the range, speed, thickness, etc. for electrode material deposition can be controlled arbitrarily. and is suitable for depositing this type of electrode material. By the way, regarding this focused ion beam deposition, please refer to the explanatory article r Toshiyoshi Takagi/Applied Physics, U.

P、 1070〜(1972)Jがある。P, 1070-(1972) J.

〔作   用〕[For production]

従ってこの発明方法においては、この集束イオンビーム
デポジション法を適用することで、スルーホールコンタ
クトの穴の深い部分だけに、選択的に電極材料を厚く堆
積できる。すなわち、イオンビームのエネルギ集束密度
、照射時間を制御して、コンタクトの穴の深さ、広さに
対応し、かつ堆積後の表面が平坦になるように、電極材
料の埋込みをなし得るのである。
Therefore, in the method of the present invention, by applying this focused ion beam deposition method, it is possible to selectively deposit a thick electrode material only in the deep portion of the hole of the through-hole contact. In other words, by controlling the energy focus density and irradiation time of the ion beam, it is possible to embed the electrode material in a manner that corresponds to the depth and width of the contact hole and that the surface after deposition is flat. .

〔実 施 例〕〔Example〕

以下この発明に係る半導体装置の製造方法の一実施例に
つき、第1図および第2図を参照して詳細に説明する。
An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIGS. 1 and 2.

第1図はこの実施例方法を適用した2層構造半導体回路
装置の概要構成を、前記第3図従来例方法に対応して表
わした断面図である。これらの各図において、同一符号
は同一または相当部分を示しており、この実施例方法で
は、前記従来例方法での上層、下層の各回路素子A、B
間のコンタクトのための、スルーホール14への導電材
料層15の堆積による埋込みに代え、下層の回路素子A
の配線材料層6に対する上層の回路素子Bの配線材料層
13の接続を、集束イオンビームデポジション法によっ
て、スルーホール14に埋込み堆積される導電材料層!
7を介してなすようにしたものである。
FIG. 1 is a sectional view showing a schematic structure of a two-layer semiconductor circuit device to which this embodiment method is applied, corresponding to the conventional method shown in FIG. 3. In each of these figures, the same reference numerals indicate the same or corresponding parts, and in this embodiment method, each of the upper layer and lower layer circuit elements A and B in the conventional method
Instead of embedding the through holes 14 by depositing a layer of conductive material 15 for contact between the underlying circuit elements A
The connection of the wiring material layer 13 of the circuit element B in the upper layer to the wiring material layer 6 of the conductive material layer is buried and deposited in the through hole 14 by the focused ion beam deposition method.
7.

こ−でさきに前記従来例方法で詳細に述べたように、コ
ンタクトのために電極材料を埋込んで堆積させなければ
ならない穴の深さは、それぞれの部分により異なってい
る。つまり下層の回路素子Aにおける電位をとるための
コンタクトの穴は深く、これに対して上層の回路素子B
での電位をとるためのコンタクトの穴は浅い。
As previously described in detail in connection with the prior art method, the depth of the hole in which the electrode material must be buried and deposited for the contact differs from part to part. In other words, the contact hole for obtaining the potential in the lower layer circuit element A is deep, whereas the upper layer circuit element B
The contact hole for obtaining the potential at is shallow.

従ってこの実施例方法においては、このために集束イオ
ンビームデポジション法を用い、深い穴への埋込みは厚
く、かつ浅い穴への埋込みは相対的に薄くさせて、それ
ぞれに堆積させるようにする。すなわち、このようにコ
ンタクトの穴への電極材料の埋込みを制御させることで
、第2図に見られるように、スルーホール部分のみに1
表面段差を充分に抑制させた状態で、この電極材料を容
易かつ簡単に堆積できるのである。そしてまたこの場合
には、従来例方法とは異なって、写真製版工程、および
これに伴なうエツチング工程などの煩雑な手段を必要と
せず、電極形成用のパターニングも不要になるもので、
例えばこの集束イオンビームは、ビーム径を0.1pm
程度まで、照射位置を±0.5終■範囲内まで制御でき
るため、これに対応して2〜3終履以上の径のスルーホ
ールの内部にのみ電極材料を堆積させることすら可能で
ある。
Therefore, in the method of this embodiment, a focused ion beam deposition method is used for this purpose, and the oxide is deposited thickly in deep holes and relatively thinly in shallow holes. In other words, by controlling the embedding of the electrode material into the contact hole in this way, as shown in Figure 2, 1.
This electrode material can be easily and easily deposited with surface steps sufficiently suppressed. Furthermore, in this case, unlike the conventional method, there is no need for complicated means such as a photolithography process and an accompanying etching process, and there is no need for patterning for electrode formation.
For example, this focused ion beam has a beam diameter of 0.1 pm.
Since the irradiation position can be controlled to within a range of ±0.5 mm, it is even possible to deposit electrode material only inside a through hole having a diameter of 2 to 3 mm or more.

なお、前記実施例方法においては、2層構造半導体回路
装置について述べたが、3層構造以上の多層構造の場合
には、スルーホールの穴の深さの所在位置による差異が
、さらに大きくなるために一層効果的である。
In the above embodiment method, a two-layer structure semiconductor circuit device was described, but in the case of a multilayer structure of three or more layers, the difference in the depth of the through hole depending on the location becomes even larger. is even more effective.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明方法によれば、半導体装置
のスルーホールコンタクト部への電極材料の埋込み堆積
に、集束イオンビームデポジション法を適用し、コンタ
クトの穴の深さに対応して電極材料の堆積レートを選択
設定し得るようにしたので、写真製版工程などの一連の
煩雑な工程を省略でき、また電極堆積後の表面段差を効
果的に軽減できるなどの特長を有するものである。
As detailed above, according to the method of the present invention, the focused ion beam deposition method is applied to the buried deposition of electrode material in the through-hole contact portion of a semiconductor device, and the electrode material is deposited in accordance with the depth of the contact hole. Since the deposition rate of the material can be selected and set, a series of complicated steps such as photolithography can be omitted, and the surface level difference after electrode deposition can be effectively reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明方法の一実施例を適用した2層構造半
導体回路装置の概要構成を示す断面図。 第2図は同上スルーホールコンタクト部への電極材料の
埋込み堆積状態を示す断面説明図であり、また第3図は
従来例方法を適用した同上装置の概要構成を示す断面図
、第4図は同上スルーホールコンタクト部への電極材料
の埋込み堆積状態を示す断面説明図である。 1・・・・シリコン半導体基板、2a 、 2b・・・
・フィールド酸化膜、絶縁酸化膜、A・・・・下層回路
素子。 6・・・・下層回路素子の配線材料層、7・・・・層間
絶縁膜、8・・・・絶縁酸化膜、9・・・・シリコン半
導体層、B・・・・上層回路素子、13・・・・上層回
路素子の配線材料層、14・・・・スルーホール、17
・・・・集束イオンビームデポジション法で堆積された
導電材料層。
FIG. 1 is a sectional view showing the general structure of a two-layer semiconductor circuit device to which an embodiment of the method of the present invention is applied. FIG. 2 is an explanatory cross-sectional view showing the state of buried and deposited electrode material in the through-hole contact portion of the above, FIG. 3 is a cross-sectional view showing the general structure of the above device to which the conventional method is applied, and FIG. FIG. 3 is an explanatory cross-sectional view showing a state in which electrode material is buried and deposited in a through-hole contact portion same as the above. 1... Silicon semiconductor substrate, 2a, 2b...
- Field oxide film, insulating oxide film, A...lower layer circuit element. 6... Wiring material layer of lower layer circuit element, 7... Interlayer insulating film, 8... Insulating oxide film, 9... Silicon semiconductor layer, B... Upper layer circuit element, 13 ...Wiring material layer of upper layer circuit element, 14...Through hole, 17
...A conductive material layer deposited by focused ion beam deposition.

Claims (1)

【特許請求の範囲】[Claims] 多層構造三次元半導体回路素子などの製造において、ス
ルーホールコンタクトの穴に、集束イオンビームデポジ
ション法により、電極材料を埋込んで堆積させることを
特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device, which is used to manufacture a multilayer three-dimensional semiconductor circuit element, and the method comprises embedding and depositing an electrode material into a through-hole contact hole by a focused ion beam deposition method.
JP27011184A 1984-12-19 1984-12-19 Manufacture of semiconductor device Pending JPS61145846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27011184A JPS61145846A (en) 1984-12-19 1984-12-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27011184A JPS61145846A (en) 1984-12-19 1984-12-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61145846A true JPS61145846A (en) 1986-07-03

Family

ID=17481688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27011184A Pending JPS61145846A (en) 1984-12-19 1984-12-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61145846A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441239A (en) * 1987-08-06 1989-02-13 Nec Corp Thin film manufacturing equipment and manufacture of metallic wiring thereby

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441239A (en) * 1987-08-06 1989-02-13 Nec Corp Thin film manufacturing equipment and manufacture of metallic wiring thereby

Similar Documents

Publication Publication Date Title
KR920020671A (en) Manufacturing Method of Semiconductor Device with Gold Structure
US5459100A (en) Method for forming metal wiring of semiconductor device
KR930009023A (en) Contact filling method by two-step deposition of selective tungsten thin film
KR960001595B1 (en) Diamond-coated sintered body excellent in adhesion and the
JPS61145846A (en) Manufacture of semiconductor device
US20030064553A1 (en) Method of producing semiconductor device and its structure
JPH0226024A (en) Manufacture of semiconductor device
JPH08316312A (en) Production of semiconductor device
KR100214556B1 (en) Method for fabricating multi-layer mosfet
JP2604487B2 (en) Semiconductor device and manufacturing method thereof
JPH03268328A (en) Wiring formation
JPS62293716A (en) Manuafcture of semiconductor device
JPS6276535A (en) Semiconductor device
JPS62150851A (en) Formation of multilayer interconnection
JPS57141937A (en) Wiring structure for semiconductor device
JPH01307244A (en) Manufacture of semiconductor device
JPH0797583B2 (en) Method for forming interlayer insulating film
JPH10135151A (en) Manufacture of semiconductor device
JPS6381833A (en) Manufacture of semiconductor device
JPS59154072A (en) Semiconductor device and manufacture thereof
JPS6226843A (en) Formation of electrode metal wiring pattern
JPH0487339A (en) Semiconductor device and its manufacture
JPH01186651A (en) Manufacture of semiconductor device
JPH0430451A (en) Method of forming electric connection and integrated circuit by use thereof
JPS60246655A (en) Formation of wiring in semiconductor device