JPS61145466A - Apparatus for evaluating ic - Google Patents

Apparatus for evaluating ic

Info

Publication number
JPS61145466A
JPS61145466A JP59269093A JP26909384A JPS61145466A JP S61145466 A JPS61145466 A JP S61145466A JP 59269093 A JP59269093 A JP 59269093A JP 26909384 A JP26909384 A JP 26909384A JP S61145466 A JPS61145466 A JP S61145466A
Authority
JP
Japan
Prior art keywords
evaluation
board
packages
ics
lead wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59269093A
Other languages
Japanese (ja)
Inventor
Toshihiro Kanetani
敏宏 金谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59269093A priority Critical patent/JPS61145466A/en
Publication of JPS61145466A publication Critical patent/JPS61145466A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To attain to simplify the evaluation of IC, by providing a plurality of IC packages to an IC evaluation board. CONSTITUTION:Two IC sockets 1, 2 capable of individually mounting ICs having different shapes are fixed to an upper substrate 3 and connected in parallel by using lead wires 4 to provide the contact parts with ICs. Lead wires 4 are also arranged to a lower substrate 5 to provide the contact part of an IC tester. By this method, two different IC packages having the equal function can be evaluated without replacing the evaluation board.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、多種類のパッケージで封止されているＩＣを
一つのボードでテスター評価することができるＩＣ評価
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an IC evaluation device that can perform tester evaluation of ICs sealed in various types of packages using a single board.

従来の技術 近年、ＩＣのパッケージは多種類化の方向にあり、その
評価も多様化している。従って一つのＩＣでも幾種類か
のパッケージによって組み立てられるということがある
。BACKGROUND OF THE INVENTION In recent years, IC packages have become more diverse, and their evaluations have also become more diverse. Therefore, even one IC may be assembled using several types of packages.

以下に従来のＩＣ評価装置について説明する。A conventional IC evaluation device will be explained below.

第２図は従来のＩＣ評価ボードを示すもので、ＩＣソケ
ット１、上基板３、リード線４および下基板６をそなえ
たものである。評価の際はこのようなボードを用いてテ
スターとＩＣとを結合させる。FIG. 2 shows a conventional IC evaluation board, which includes an IC socket 1, an upper board 3, lead wires 4, and a lower board 6. During evaluation, such a board is used to connect the tester and the IC.

発明が解決しようとする問題点 しかしながら上記のような構成では、一種類のＩＣを多
種類のパッケージに適応しようというとき、評価ボード
もパッケージに合わせ、て同数、準備しなければならな
いという問題点を有していた。Problems to be Solved by the Invention However, with the above configuration, when one type of IC is to be applied to many types of packages, the same number of evaluation boards must be prepared depending on the package. had.

本発明は上記従来の問題点を解消するもので、ＩＣを評
価する際に用いる評価ボードの合理的活用が可能なＩＣ
評価装置を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and provides an IC that allows rational use of evaluation boards used when evaluating ICs.
The purpose is to provide an evaluation device.

問題点を解決するための手段 本発明は単数のボードとパッケージ形状の異なったＩＣ
を個々に装着し得る複数のＩＣソケットとを備えたＩＣ
評価装置である。Means for Solving the Problems The present invention provides a single board and ICs with different package shapes.
IC with multiple IC sockets that can be individually mounted
It is an evaluation device.

作用 本発明の構成によると、複数のＩＣソケットの各対応端
子をリード線で並列接続させることによシ、評価ボード
の変換することなしに、多種類のパッケージＩＣを評価
することができる。According to the configuration of the present invention, by connecting the respective corresponding terminals of a plurality of IC sockets in parallel using lead wires, it is possible to evaluate various types of packaged ICs without converting the evaluation board.

実施例 第１図は本発明の実施例におけるＩＣ評価装置を示すも
のである。第１図において、上基板３上にパッケージ形
状の単なるＩＣを個々に装着し得る二つのＩＣソケット
１，２を固定し、それをリード線４を用いて並列接続し
、ＩＣとの接触部を設定する。一方、下基板５へもリー
ド線を配してＩＣテスターとの接触部を設ける。なお、
各リード線４は中間のターミナル６の位置でその信号量
を検出できるようにするのも有効である。Embodiment FIG. 1 shows an IC evaluation apparatus in an embodiment of the present invention. In FIG. 1, two IC sockets 1 and 2, into which simple package-shaped ICs can be mounted individually, are fixed on an upper substrate 3, and are connected in parallel using lead wires 4, so that the contact portion with the IC is fixed. Set. On the other hand, lead wires are also arranged on the lower substrate 5 to provide a contact portion with the IC tester. In addition,
It is also effective to enable the signal amount of each lead wire 4 to be detected at the intermediate terminal 6 position.

以上のように本実施例によれば、同等の機能をもつ異な
ったパッケージＩＣ二個を評価ボードの取り替えなしに
評価することができる。As described above, according to this embodiment, two different packaged ICs having equivalent functions can be evaluated without replacing the evaluation board.

ところで、第１図の構成と異なるのは、二個のパッケー
ジを上基板上に二個設けた点である。Incidentally, the difference from the configuration shown in FIG. 1 is that two packages are provided on the upper substrate.

なお、この実施例において、上基板上に二個のパッケー
ジを設けるとしたが、上基板上に三個あるいはそれ以上
設けるとしてもよい。In this embodiment, two packages are provided on the upper substrate, but three or more packages may be provided on the upper substrate.

発明の効果 本発明は、ＩＣ評価ボードに複数のパッケージＩＣを設
けることにより、ＩＣの評価を簡潔化することができる
優れたＩＣ評価ボードを実現できるものである。Effects of the Invention The present invention makes it possible to realize an excellent IC evaluation board that can simplify IC evaluation by providing a plurality of packaged ICs on the IC evaluation board.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明実施例におけるＩＣ評価ボードの側面図
、第２図は従来のＩＣ評価ボードの側面図である。 １・・・・・・ＩＣソケットＡ、２・・・・・・ＩＣソ
ケットＢ１３・・・・・・上基板、４・・・・・・リー
ド線、６・・・・・・下基板、６・・・・・・ターミナ
ル。FIG. 1 is a side view of an IC evaluation board according to an embodiment of the present invention, and FIG. 2 is a side view of a conventional IC evaluation board. 1...IC socket A, 2...IC socket B13...upper board, 4...lead wire, 6...lower board, 6...Terminal.

Claims (1)

【特許請求の範囲】[Claims] 基板上に、同品種でかつパッケージ形状の異なるＩＣを
個々に装着し得る複数個のＩＣソケットを配し、ターミ
ナルを介してリード線を配線し、汎用評価ボードとの結
合を可能にしたＩＣ評価装置。IC evaluation with multiple IC sockets on the board that can individually mount ICs of the same type but with different package shapes, and lead wires routed through terminals to enable connection to a general-purpose evaluation board. Device.
JP59269093A 1984-12-19 1984-12-19 Apparatus for evaluating ic Pending JPS61145466A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59269093A JPS61145466A (en) 1984-12-19 1984-12-19 Apparatus for evaluating ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59269093A JPS61145466A (en) 1984-12-19 1984-12-19 Apparatus for evaluating ic

Publications (1)

Publication Number Publication Date
JPS61145466A true JPS61145466A (en) 1986-07-03

Family

ID=17467572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59269093A Pending JPS61145466A (en) 1984-12-19 1984-12-19 Apparatus for evaluating ic

Country Status (1)

Country Link
JP (1) JPS61145466A (en)

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