JPS61144929A - Phase synchronous oscillating circuit - Google Patents

Abstract

PURPOSE:To decrease the adjusting time and to improve the accuracy by receiving a built-in oscillator output or its frequency dividing output, comparing the phase with that of a reference signal at a phase comparator and controlling the oscillating frequency of the oscillator with its output. CONSTITUTION:When a reference signal fref is logical H, an FF, FF1 is set, an output Q1 goes to logical H, a transistor (TR) TR1 is turned on, and a ring oscillator OSC is oscillated at a frequency higher than that of the reference signal fref. An oscillation output fout falls down without fail during one period of the reference signal fref. When the oscillation output iout descends, an FF, FF2 is set, an output Q2 goes to H to reset the FF, FF1. Further, the output Q1 goes to H to reset the FF, FF2. The output Q1 goes to L, the TR, TR1 is turned off, the ring oscillator OSC is oscillated at a frequency lower than that of the reference signal fref and the oscillated output fout is not arisen during one period of the reference signal fref. The FF, FF1 is set tat the leading of the next reference signal fref, the TRTR1 is turned on, the ring oscillator OSC is oscillated at a frequency higher than that of the reference signal fref.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is a circuit built in an oscillator and has seven frequency adjustment terminals, in which a reference signal is applied from the outside.
The purpose is to provide a means for adjusting the frequency of the oscillator by fJJ.

[Conventional technology]

Conventional testing of integrated circuits that have a built-in oscillator and require frequency adjustment? If you do this, you have to manually adjust the ratio using variable resistors, etc.

[Problem that the invention attempts to solve]

The conventional method described above takes time to adjust and is difficult to adjust accurately. Furthermore, when conventional methods are applied to the selection of mass-produced integrated circuits, costs increase.

The purpose of the present invention is to automate what has conventionally been done manually, reduce adjustment time, and improve accuracy.

[Friendly means to solve the problem] The built-in oscillator output or fc of the phase locked circuit according to the present invention
The phase of the frequency-divided output is compared with a reference signal using a phase comparator, and the output is used to obtain a phase-locked circuit that controls the oscillation frequency of the oscillator.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows one embodiment of the present invention. It is a nine-semiconductor integrated circuit that has a ring excavator O8C which is obtained by an I"L inverter in the engineering C1. FF1 and FF2 are D with reset.
Type 7 lipflop, G1t! Inverter, 02
~G7 is I”L inverter, R2, R8 are resistors,
Tri *Tr2 hNP N-type transistor 5Tr3
+Tr4 indicates a PNP type transistor. Adjustment of the frequency of the ring oscillator O8C in the conductor integrated circuit IC1 is performed in conjunction with adjustment of the injector current, and it is generally known that the larger the injector current, the higher the oscillation frequency. A reference voltage Vref is applied to the base of the transistor Tr2, and the emitter is fixed to a constant voltage applied to the adjustment terminal. Adjustment terminal C0NT
A constant voltage is achieved by adjusting the resistor R2 or R3't'' connected to this terminal C0NT. When the voltage of the adjustment terminal C0NT changes, the collector current of the transistor Tr2 changes, and the transistor Tr3 + Tr4 is formed. Ring oscillator 0b via current mirror circuit?
Change the injector current of the I"L inverter that constitutes C2. By changing this injector current, the ring oscillator 01
The oscillation frequency of C is adjusted. The resistor fL3 is set to oscillate at a frequency sufficiently lower than the t-th reference signal fref for synchronization t. Furthermore, the resistor R+2 is set to oscillate at a frequency sufficiently higher than the reference signal fref when the transistor Tr1 is ONE.

The flip-flop FF1i detects the rising edge 9 of the reference signal fref, turns the transistor Trx ONL, and causes the ring oscillator 01ci reference signal fref 9 to also oscillate at a high frequency. The clip flop FF2 detects the fall of the output of the oscillator 08C as v, and outputs the clip 70-tube FF1i.
The ring oscillator O8C'ilH is reset and the transistor Trlt'' is turned off to cause the ring oscillator O8C'ilH to oscillate at a low frequency.

These operations will be explained using the timing chart of FIG. First, the reference signal fref and the oscillation output fo
It is assumed that both ut and ut are at a low level (hereinafter abbreviated as "L#"). When the reference signal fref becomes a high level (hereinafter abbreviated as 1H"), the clip-flop FF1 is set, the output Q1 becomes 1H#9, and the transistor Trl becomes ONL.
The IJ song oscillator 08C oscillates at a higher frequency than the reference signal fref. The oscillation output font always falls in one cycle of the reference signal fref. When the oscillation output fout falls, the slip flop FF2 is set and the output Q
2 becomes 'H#' and resets the flip 70-tube FF. Furthermore, the output Q1 becomes 'H#' and resets the flip-flop FF2. The output Q1 becomes 1L#, the transistor Tr1 becomes 0FFL, the IJ song oscillator 08C oscillates at a lower frequency than the reference signal fref, and the oscillation output fout does not rise within one cycle of the reference signal fref. At the next rising edge of the reference signal fref, the seven lip-flop FF1 is set, the transistor Tr1 is turned on, and the ring oscillator oses the reference signal fref 9 again to oscillate at a high frequency.

By repeating the above operation, the oscillation output fout becomes the reference signal f.
Fully synchronized to ref. Further, as shown in FIG. 3, a divider 1) IVI, DIV2' is built into the IC, and the divided output r clock fo1. When used as a signal generator, it is also possible to synchronize the f-clock fuc with the reference signal frefk by providing a frequency divider V1 and DIV2' after the raising output foutO. The timing chart is shown in FIG.

When using a branching device in this way, the reference signal frefk
The oscillator's frequency f can also be set to a low value, ensuring stable synchronization. In addition, when performing a funky test using a digital tester or the like, the number of clock pulses of the rainbow signal fref can be reduced by seven by using the frequency division as described above.

〔Effect of the invention〕

As explained above, the present invention has a built-in oscillator and can fully automate the frequency adjustment of semiconductor integrated circuits, etc.
If applied to the sorting process for TA products, it will significantly reduce the number of man-hours. Further, when performing a funk eye test using an L8I tester or the like, it is possible to completely synchronize with the clock of the tester, and accurate testing can be performed using a test pattern.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of one embodiment of the present invention, and Fig. 2 is a block diagram of an embodiment of the present invention.
The timing chart is shown in the figure. FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. 4 is a timing chart of FIG. 3. FF1lFF2...D type slip 70 knobs, Gl
...Inverter, 02~Gf...I"L inverter, Tr 1 m Tr2...NPN type transistor, "f3 w Tr4...P to P type transistor, R
1-几3...Resistor, fref...Reference signal input terminal, fout...Oscillator output terminal, CENT...Adjustment end VOO...source, Vref...reference source, 08
C...Ring oscillator, IC1...Semiconductor integrated circuit,
DIVI, DIV2... Frequency divider No. 21! r

Claims (1)

[Claims] an oscillation circuit having a frequency adjustment terminal and an output terminal, means for changing the oscillation frequency of the oscillation circuit, a comparison circuit for comparing an external reference signal and the output of the oscillator, and an output of the comparison circuit for adjusting the oscillation frequency. A phase synchronized oscillation circuit characterized by having means for driving the changing means.