JPS61144879A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the step interruption on the cell section of the Al wiring and control gate wiring by burying a floating gate in the semiconductor substrate. CONSTITUTION:An N type source region 32 and a draion region 33 are formed in a P type Si substrate 31. A dent section 34 shallower than the source region 32 andthe drain region 33 is formed on the surface of the substrate 31 betweenthe regions 32 and 33 to bury a floating gate 36 of polycrystalline Si inside of the dent 34 through an insulation film 35. A polycrystalline control gate 38 is formed on the gate 36 through the insulation film 37, and then, an Al wiring 40 is formed on the gate through an insulation film 39. The wiring 40 is connected to the source region 33 and the drain region 33 through the contact hole 41 provided on the film 39. The gate 236 is buried in the substrate 31 to that the difference in the step on the contact section is reduced, thereby preventing the step interruption of the control gate wiring and the Al wiring.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device having a floating gate, and particularly relates to an E P ROM (J, rasable J:
rograiable Jlead-Ω-nly M
The present invention relates to a semiconductor device used in a semiconductor device.

[Technical Background of the Invention] Typically, an EPROM cell (memory element) uses a MOS transistor having an electrically floating conductive gate.

FIG. 3 shows a typical conventional structure of this MOS transistor. That is, this transistor includes, for example, a P-type silicon substrate 11 and an N-type source region 12.
A conductive gate 15 and a control gate 16 made of polycrystalline silicon or the like are stacked between these regions with an insulating film (SiO2) 14 interposed therebetween. Roughly, an A1 wiring 18 is formed thereon via an interlayer insulating film 17 made of CVD5iOz, etc.
1 wiring 18 is connected to source region 12 and drain region 13 via contact hole 19.

[Problems with the Background Art] As mentioned above, in the conventional EPROM, two conductive gates, the floating gate 15 and the control gate 16, are stacked vertically, so there is a large step difference in the contact hole 19 area. will occur.

At present, as the integration of memories progresses, the gate width, gate contact interval, A1 wiring 18 width, etc. are all becoming finer, and the above-mentioned large step difference becomes a major obstacle in process design.

In other words, since a large level difference induces step breakage in the A1 wiring 18, a technology is required to provide a taper in the contact hole 19 to prevent this, and this, combined with the occurrence of short circuit with the adjacent control gate 16, requires the development of this technology. is not easy. It is desirable to make the height difference in the vertical direction of the A1 wiring 18 as small as possible from the viewpoint of improving yield.

Furthermore, FIG. 4 is a cross-sectional view of the EPROM shown in FIG. 3 from the width direction. That is, a 70-inch gate 15 and a control gate 16 are stacked in two layers on an insulating film 14 extending up to a field oxide film 20 separating devices. Since the control gate 16 also serves as a wiring, a step is also formed at the end of the floating gate 15.
Due to the shape of the fifth end and the instability of the etching conditions during formation of the control gate 18, breakage often occurs as in the case of the A1 wiring 18.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a semiconductor device that can prevent the occurrence of step breaks in the cell portion of the AI wiring and control gate wiring layer. It is in.

[Summary of the Invention] The present invention embeds floating gates, which were conventionally free on a semiconductor substrate, in the semiconductor substrate in order to reduce the level difference in EFROM, and the control gate and A1 wiring can be formed smoothly. It was designed to be carried out.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, for example, in a P-type silicon substrate 31, N
A source region 32 and a drain region 33 are formed. On the surface of the silicon substrate 31 between the source region 32 and the drain region 33, a recess 34 is formed which is shallower than the source region 32 and the drain region 33. The formed floating gate 36 is embedded.

Furthermore, an insulating film 3 is provided on this floating gate 36.
A control gate 38 also made of conductive polycrystalline silicon is formed via 7. On this control gate 38, an A1 wiring @40 is formed with a glabella insulating film 39 interposed therebetween. This A1 arrangement a.

is connected to the source region 32 and drain region 33 via a contact hole 41 provided in the interlayer insulating film 39.

In the EPROM cell with the above structure, since the floating gate 36 is embedded in the silicon substrate 31, the level difference in the contact portion is greatly reduced compared to the conventional structure cell, and the level difference in the peripheral circuit transistors, etc. It is about the same.

Note that since the source region 32 and the drain region 33 are diffused deeper than the lower end of the floating gate 39, they can operate as an EFROM in exactly the same way.

FIG. 2 shows a cross-sectional structure of the EPROM cell shown in FIG. 1 viewed from the width direction. There is no step difference at all, and it is safe to say that there is no break in the control gate 40.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor device that can prevent disconnection of the control gate wiring due to a step difference and can significantly reduce disconnection of the A1 wiring.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view showing the cell structure of an EPROM according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the structure shown in FIG. 1 viewed from the width direction, and FIG. FIG. 4 is a sectional view showing the cell structure of a conventional EPROM. FIG. 4 is a sectional view of the structure of FIG. 1 viewed from the width direction. 31... Silicon substrate, 32... Source region, 33
... Drain region, 34... Concavity, 35... Insulating layer, 36... Floating gate, 37... Insulating layer, 38... Control gate, 39... Interlayer insulating film, 40...・A1 wiring.

Claims (1)

[Claims] a semiconductor substrate of one conductivity type, a source region and a drain region of the opposite conductivity type and provided spaced apart within the same substrate, a recess provided between the source region and the drain region of the substrate; 1. A semiconductor device comprising: a floating gate provided in a recess with an insulating layer interposed therebetween; and a control gate provided on the floating gate with an insulating layer interposed therebetween.