JPS61144047A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61144047A
JPS61144047A JP26796384A JP26796384A JPS61144047A JP S61144047 A JPS61144047 A JP S61144047A JP 26796384 A JP26796384 A JP 26796384A JP 26796384 A JP26796384 A JP 26796384A JP S61144047 A JPS61144047 A JP S61144047A
Authority
JP
Japan
Prior art keywords
lead
package
semiconductor device
bent
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26796384A
Other languages
Japanese (ja)
Inventor
Makoto Shimanuki
嶋貫 誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26796384A priority Critical patent/JPS61144047A/en
Publication of JPS61144047A publication Critical patent/JPS61144047A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
    • H05K3/308Adaptations of leads

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To eliminate the deterioration in a package by providing a bent at the upper position inserted into a lead substrate of the center, thereby alleviating the impact due to cutting and bending of the lower end of leads extended downward of a printed board without adverse influence to the package. CONSTITUTION:A central lead 22 if formed with a forward bent 22a at the upper position of a printed board 7, and the lower portion is inserted to into an inserting hole 8. The lead 22 is cut at the excess portion of the lower end by pressing means and bent. The lead 22 is applied with an impact by cutting and bending the lower end, but the transmission into a package 2 is alleviated by the upper bent 22a of the printed board 7. Thus, an automatic insertion of a semiconductor device 21 into the board 7, cutting of leads and bending by an automatic mounting machine can be performed without adverse influence to the package 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、パッケージから下方に複数本のリードが引
出され、基板に差込まれるようにした半導体装置に関し
、特にリードの改良に係る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a plurality of leads are drawn out downward from a package and inserted into a substrate, and particularly relates to improvements in the leads.

〔従来の技術〕[Conventional technology]

例えばトランジスタなど、半導体チップ部を封止したパ
ッケージから下方に3本のリードが出された、従来の半
導体装置は、第3図に斜視図で示すようセなっていた0
(1)はトランジスタなどの半導体装置で、パッケージ
(2)から3本のリード(3)。
For example, a conventional semiconductor device, such as a transistor, in which three leads are protruded downward from a package in which a semiconductor chip is sealed, has a three-lead configuration, as shown in the perspective view in Figure 3.
(1) is a semiconductor device such as a transistor, and has three leads (3) from the package (2).

(4)が下方に引出されている0これらのうち、中央の
リード(4)は直線状に出され、両側のリード(3)は
外側に間隔を広げるため折曲げ部(3a)で折曲げてb
る0 このように形成された多数の半導体装置(1)を、リボ
ン状の台紙(5)に各リード+3) 、 (4)の下端
部を当て、接着テープ(6)で張着け、搬送するように
している。(5a)は台紙(6)の送り兼用の位置決め
穴である。このように多数の半導体装置(1)を台紙(
5)による縦形テーピング包装とし、プリント基板への
装着工程にかける。
(4) is pulled out downward 0 Among these, the center lead (4) is pulled out in a straight line, and the leads (3) on both sides are bent at the bending part (3a) to widen the gap outward. teb
0 A large number of semiconductor devices (1) formed in this way are placed on a ribbon-shaped mount (5) with the lower ends of each lead +3) and (4), pasted with adhesive tape (6), and transported. That's what I do. (5a) is a positioning hole that also serves as a feed for the mount (6). In this way, a large number of semiconductor devices (1) are mounted on a mount (
It is packaged with vertical taping according to 5) and subjected to the mounting process on a printed circuit board.

第3図のようにテーピング包装されてて搬送された半導
体装置(1)は、第4図及び第5図に示すようにプリン
ト基板(7)に装着される0まず、第4図(a)及び(
b)に正面断面図及び側面断面図で示すように1半導体
装置(1)の各リード(3)。
The semiconductor device (1) wrapped and transported with taping as shown in FIG. 3 is mounted on a printed circuit board (7) as shown in FIGS. 4 and 5. First, as shown in FIG. as well as(
Each lead (3) of one semiconductor device (1) as shown in the front sectional view and side sectional view in b).

(4)が、自動装着機械(図示は略す)によりプリント
基板(7)の各挿入穴(8)K挿入され、下端部が下方
に出される0そとで、両側のリード(3)はプレス手段
の固定刃(9)と、移動刃a〔の矢印A、B方向の移動
により折断される。同時に中央のリード(4)は固定刃
(9)と、移動刃(ロ)の矢印C方向の移動によシ折断
される。
(4) is inserted into each insertion hole (8)K of the printed circuit board (7) by an automatic mounting machine (not shown), and the lower end is brought out downward.The leads (3) on both sides are pressed. It is broken by movement of the fixed blade (9) of the means and the movable blade a in the directions of arrows A and B. At the same time, the central lead (4) is broken by the movement of the fixed blade (9) and the movable blade (b) in the direction of arrow C.

このとき、第5図(a)及び(b)に正面断面図及び側
面断面図で示すように1各リード(3)の下端は切落さ
れるとともに、プリント基板(7)下に残った端は矢印
A、B方向に側方に折曲げられる。同時にリード(4)
の下端は切落されるとともに、プリント基板(7)下に
残った端は、矢印C方向に前方に折曲げられる。こうし
て、プリント基板(7)下に折曲げられた各リード+3
) e (4)の端は、基板(7)の配線にろう付は接
続される。
At this time, as shown in the front sectional view and side sectional view in FIGS. 5(a) and 5(b), the lower end of each lead (3) is cut off, and the end remaining under the printed circuit board (7) is cut off. is bent laterally in the direction of arrows A and B. Lead at the same time (4)
The lower end of is cut off, and the end remaining under the printed circuit board (7) is bent forward in the direction of arrow C. In this way, each lead +3 bent under the printed circuit board (7)
) e The end of (4) is connected to the wiring of the board (7) by brazing.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の半導体装置では、中央のリード(4
)には、切断、切曲げによる衝撃が直接パッケージ内に
伝わ夛、劣化させるおそれがあった。
In the conventional semiconductor device as described above, the central lead (4
), there was a risk that the impact from cutting or bending would be transmitted directly into the package and cause it to deteriorate.

この発明は、このような問題点を解決するためになされ
たもので、パッケージから出された中央部のリードがプ
リント基板に挿入され、先端部の切断、折曲げによる衝
撃がパッケージ部内へ伝達するのを緩和し、パッケージ
内の劣化をなくする半導体装置を得ることを目的として
いる0(問題点を解決するだめの手段〕 この発明にかかる半導体装置は、中央部のリ−。
This invention was made to solve this problem.The central lead coming out of the package is inserted into the printed circuit board, and the impact caused by cutting or bending the tip is transmitted into the package. A semiconductor device according to the present invention aims to provide a semiconductor device which alleviates the problems caused by the problem and eliminates deterioration inside the package.

ドの基板に挿入される上方位置に湾曲部を設けたもので
ある。
A curved portion is provided at an upper position to be inserted into the board of the card.

〔作用〕[Effect]

この発明においては、パッケージから出された中央部の
リードがプリント基板に挿入され、下端部の切断、折曲
げによる衝撃が湾曲部により緩衝され、パッケージ部内
への悪影響を防ぐ0〔実施例〕 第1図はこの発明による半導体装置の一実施例を示す斜
視図で、図は多数個が縦形テーピング包装された状態を
示し、t2) 、 (3) 、 (3a) 、 (51
、(5a) 。
In this invention, the central lead coming out of the package is inserted into the printed circuit board, and the impact caused by cutting or bending the lower end is buffered by the curved part, thereby preventing any adverse effects on the inside of the package. FIG. 1 is a perspective view showing an embodiment of the semiconductor device according to the present invention, and the figure shows a state in which a large number of semiconductor devices are wrapped vertically with taping.
, (5a).

(6)は上記従来装置と同一のものであるo彰υはトラ
ンジスタなどからなる半導体装置で、パッケージ(2)
から下方に両側のリード(3)と、中央のリード(2)
とが引出されている。この中央のリードυには、上方に
前方に湾曲部(22a)を設けである。
(6) is the same as the conventional device mentioned above. o 2 is a semiconductor device consisting of a transistor, etc., and the package (2)
From downwards, the leads on both sides (3) and the lead in the center (2)
is drawn out. This central lead υ is provided with a curved portion (22a) at the upper and front side.

この↓導体装置+1)をプリント基板に載せた状態を、
第2図に断面図で示す。中央のリード(2)はプリント
基板(7)の上方位置に前方への湾曲部(22a)が設
けられ、その下方が挿入穴(8)K通されている0この
リード(イ)は下端部の余分の部分が、上記第4図、第
5図と同様にしてプレス手段で切断され、第2図に鎖線
で示すように折曲げられる。
The state in which this ↓ conductor device +1) is placed on the printed circuit board is
It is shown in cross section in FIG. The center lead (2) has a forward curved part (22a) above the printed circuit board (7), and the lower part thereof is passed through the insertion hole (8) K. This lead (A) has a lower end. The excess portion is cut off by a press in the same manner as in FIGS. 4 and 5 above, and is bent as shown by the chain line in FIG.

リード(イ)は下端部の切断、折曲げにより衝撃が加わ
るが、プリント基板(7)の上方の湾曲部(22a)に
よりパッケージ(2)内への伝達が緩衝される。こうし
て、自動装着機械(図示は略す)による半導体装R@の
プリント基板(7)への自動挿入、リード切断、折曲げ
が、パッケージ(2)部に悪影響を及ぼすことなく行え
る。
Although a shock is applied to the lead (A) by cutting and bending the lower end, the impact is damped by the upper curved portion (22a) of the printed circuit board (7) into the package (2). In this way, automatic insertion of the semiconductor device R@ into the printed circuit board (7), lead cutting, and bending by an automatic mounting machine (not shown) can be performed without adversely affecting the package (2) portion.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、パッケージから出さ
れた中央のリードに、プリント基板に対する上方位置に
湾曲部を設けたので、プリント基板の下方に出たリード
の下端部の切断、折曲げKよる衝撃が、パッケージ部に
悪影響を及ぼすことなく緩和され、パッケージ内の劣化
がなくされる。
As described above, according to the present invention, since the central lead extending from the package is provided with a curved portion at a position above the printed circuit board, the lower end of the lead extending below the printed circuit board can be cut and bent. The impact caused by K is alleviated without adversely affecting the package portion, and deterioration within the package is eliminated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明による半導体装置の一実施例を示す縦
形テーピング包装した状態の斜視図、第2図は第1図の
半導体装置の中央のリードをプリント基板に挿入した状
態を示す側面断面図、第3図は従来の半導体装置を示す
縦形テーピング包装した状態の斜視図、第4図及び第5
図は第3図の半導体装置のブ11ント基板に挿入したリ
ードの下端部を切断、折曲げする状態を順に示し、t4
4図(a)は正面断面図、第4図(1))は第4図(a
)の11線における断面図、第5図(IL)は正面断面
図、第5図(1))は第5図(a)のv−v線における
断面図である。 2・・・パッケージ、3・・・リード、3a・・・折曲
げ部、7・・・プリント基板、21・・・半導体装置、
22・・・+7 +ド、g2a・・・湾曲部 なお、図中同一符号は同−又は相当部分を示す。
FIG. 1 is a perspective view showing an embodiment of the semiconductor device according to the present invention in a vertical taping packaged state, and FIG. 2 is a side cross-sectional view showing the state in which the central lead of the semiconductor device shown in FIG. 1 is inserted into a printed circuit board. , FIG. 3 is a perspective view of a conventional semiconductor device wrapped in vertical tape packaging, and FIGS. 4 and 5 are
The figures sequentially show the state in which the lower ends of the leads inserted into the printed circuit board of the semiconductor device shown in Fig. 3 are cut and bent.
Figure 4(a) is a front sectional view, Figure 4(1)) is a front sectional view, Figure 4(a) is a
5(IL) is a front sectional view, and FIG. 5(1)) is a sectional view taken along line v-v in FIG. 5(a). 2... Package, 3... Lead, 3a... Bent part, 7... Printed circuit board, 21... Semiconductor device,
22...+7 +d, g2a...curved portion Note that the same reference numerals in the drawings indicate the same - or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] パッケージの下方から中央と両側とのリードが出され、
これら両側のリードは上部で外側方に折曲げられ下端部
が上記中央のリードとは間隔が広げられてあり、これら
のリードがプリント基板に挿入され、下方に出た下端部
が切断され残りが折曲げられるようにした半導体装置に
おいて、上記中央のリードに、上記プリント基板に対す
る上方位置に湾曲部を設けたことを特徴とする半導体装
置。
Leads from the center and both sides come out from the bottom of the package,
The leads on both sides are bent outward at the top, and the lower ends are spaced apart from the center lead.These leads are inserted into the printed circuit board, the lower ends protruding downwards are cut off, and the remaining ends are cut off. A semiconductor device which is bendable, characterized in that the central lead is provided with a curved portion at a position above the printed circuit board.
JP26796384A 1984-12-17 1984-12-17 Semiconductor device Pending JPS61144047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26796384A JPS61144047A (en) 1984-12-17 1984-12-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26796384A JPS61144047A (en) 1984-12-17 1984-12-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61144047A true JPS61144047A (en) 1986-07-01

Family

ID=17452023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26796384A Pending JPS61144047A (en) 1984-12-17 1984-12-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61144047A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367192A (en) * 1987-04-22 1994-11-22 Sgs-Thomson Microelectronics S.R.L. Package for integrated devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367192A (en) * 1987-04-22 1994-11-22 Sgs-Thomson Microelectronics S.R.L. Package for integrated devices

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