JPS5963751A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5963751A
JPS5963751A JP17503182A JP17503182A JPS5963751A JP S5963751 A JPS5963751 A JP S5963751A JP 17503182 A JP17503182 A JP 17503182A JP 17503182 A JP17503182 A JP 17503182A JP S5963751 A JPS5963751 A JP S5963751A
Authority
JP
Japan
Prior art keywords
leads
external
semiconductor device
external lead
led out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17503182A
Other languages
Japanese (ja)
Inventor
Katsuhiko Tsuura
克彦 津浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP17503182A priority Critical patent/JPS5963751A/en
Publication of JPS5963751A publication Critical patent/JPS5963751A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • H01L23/49555Cross section geometry characterised by bent parts the bent parts being the outer leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor

Abstract

PURPOSE:To obtain a device which can be easily mounted on a substrate by having linear external leads led out from a sealed outer shell and external leads with tips bent rectangularly before the most tip of the linear form. CONSTITUTION:The leads 9-11 led out of the sealed outer shell 1 have the linear parts 14-16, and the leads 12 and 13 have the parts 17 and 18 bent rectangularly. The leads 9-11 are inserted into through holes of the substrate 5, and thus mounted on the substrate 5 with the bent parts of the leads 12 and 13 as stoppers. This constitution does not lose stopper function even when the lead width is reduced; therefore the number of leads which can be led out of a package of a specific size increases, and accordingly an IC device of a substantially high integration degree can be loaded. This constitution can be applied to any one of a dual line type and single-in-line type packages, and remarkable miniaturization can be realized by the reduction of lead center intervals.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、システム回路の高集積化ならびに高密度実装
に対応できるパッケージの小型化を実現し、しかも、高
密度配線基板への装着が容易な半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a semiconductor that achieves high integration of system circuits and miniaturization of packages that can accommodate high-density packaging, and that can be easily mounted on high-density wiring boards. Regarding equipment.

従来例の構成とその問題点 映像機器あるいは音響機器などでは、その6機能の向上
をはかるだめの取り組みとともに、機器そのものの小型
軽量化をはかるための取シ組みがなされている。そして
、後者の取シ込みでは、システム回路の小型化ならびに
軽量化に力が注がれており、中でも、回路の集積化なら
びに、これを実現する半導体集積回路のパッケージの小
型化をはかることに力が注がれている。ことに、半導体
集積回路では、その集積度が増大すると、通常は外部リ
ード数が増し、パッケージの大型化が避けられないとこ
ろとなる。このことは、上記の取り組みに相反する。
Conventional configurations and their problems In video equipment, audio equipment, and the like, efforts are being made not only to improve the six functions of the equipment, but also to make the equipment itself smaller and lighter. In order to address the latter, efforts are being made to make system circuits smaller and lighter.In particular, efforts are being made to increase the integration of circuits and to miniaturize the packages of semiconductor integrated circuits that make this possible. Power is being poured into it. In particular, as the degree of integration of semiconductor integrated circuits increases, the number of external leads usually increases, making it inevitable to increase the size of the package. This contradicts the above efforts.

また、システム回路の製作にあたり、プリント基板に半
導体装置を取り付ける場合、プリント基板に形成したリ
ード挿通孔に外部リードを差し込み、半田付けによって
固定する方法、あるいは、プリント基板の配線層に外部
リードを直接半田付けする方法のいずれかの方法が採用
されている。
In addition, when attaching a semiconductor device to a printed circuit board when manufacturing a system circuit, there are two methods: inserting the external leads into lead insertion holes formed on the printed circuit board and fixing them by soldering, or directly attaching the external leads to the wiring layer of the printed circuit board. One of the methods of soldering is used.

しかしながら、前者の方法では、プリント基板に半導体
装置の外部リードと同数のり一ド挿通孔を形成する必要
があシ、この挿通孔の間隔の制約によって、半導体装置
のリード間隔にも自ら制約が課せられるところとなシ、
パッケージの小型化をはかることのできるリード間隔を
実現することができなかった。一方、後者の方法では、
プリント基板にリード挿通孔を形成する必要がないため
、これに取9つける半導体装置のリード間隔を狭くでき
、パッケージの小型化をはかること、システム回路の高
集積化と高密度実装化をはかることな、どが実現できる
。しかしながら、この方法では、プリント基板の配線層
形成面側のみが利用されるため、半導体装置を取9つけ
る場合に、これを固定する必要がある。特に、取υ付け
を自動的に行う場合には、固定手段を設け、これによっ
て、半導体装置を固定しなければならなかった。
However, in the former method, it is necessary to form the same number of glued insertion holes as the external leads of the semiconductor device on the printed circuit board, and the restrictions on the spacing between these insertion holes also impose restrictions on the spacing between the leads of the semiconductor device. Where can I get it?
It was not possible to achieve a lead spacing that would allow for miniaturization of the package. On the other hand, in the latter method,
Since it is not necessary to form lead insertion holes in the printed circuit board, the lead spacing of the semiconductor device mounted on this board can be narrowed, allowing for smaller packages and higher integration and higher density packaging of system circuits. What can be achieved? However, in this method, only the wiring layer formation side of the printed circuit board is used, and therefore, when mounting the semiconductor device, it is necessary to fix it. In particular, when mounting is performed automatically, it is necessary to provide a fixing means and use this to fix the semiconductor device.

第1図は、概知のデュアルインライン形パッケージ構造
の半導体集積回路の外部リードをプリント基板に形成し
たリード挿通孔に差し込んだ状態を示す図である。図示
するように、封止外殻1から外部に導出された外部リー
ド2,3および4は、その先端部が幅狭く形成されてお
り、この部分がプリント基板5の外部リード挿通孔6,
7および8に差し込まれ、この先端部と幅の広いリード
部分との連繋部Aが差し込み深さを規定するためのスト
ッパ部として働く。このストッパ部Aをなくすならば、
外部リードの幅をその全長にわたって狭くして外部リー
ドのピッチを小さくすることができ、パッケージの小型
化が実現されるが、ストッパ部をなくすと封止外殻1の
下面がプリント基板面に当接するところとなり、半田3
 +Jけ時に溶融した半田が毛管現象で当接面間にまで
拡がり、このため短絡事故の生じるおそれがあった。こ
のような不都合を抑圧するには、上記のストッパ部をも
つ外部リード形状とすることが大切であり、したがって
、外部リードのピッチを小さくすることには限界があシ
、このことが、パッケージの小型化を阻む主要因となっ
ていた。
FIG. 1 is a diagram showing a state in which external leads of a semiconductor integrated circuit having a known dual in-line package structure are inserted into lead insertion holes formed in a printed circuit board. As shown in the figure, the external leads 2, 3, and 4 led out from the sealing shell 1 have narrow tip portions, and these portions are connected to the external lead insertion holes 6 and 4 of the printed circuit board 5, respectively.
7 and 8, and the connecting portion A between this tip and the wide lead portion serves as a stopper portion for regulating the insertion depth. If this stopper part A is eliminated,
The pitch of the external leads can be reduced by narrowing the width of the external leads over their entire length, making the package more compact. This is where it touches, solder 3
During +J, the melted solder spreads between the contact surfaces due to capillary action, which may cause a short circuit accident. In order to suppress such inconveniences, it is important to have an external lead shape that has the above-mentioned stopper part.Therefore, there is a limit to reducing the pitch of the external leads, and this causes problems with the package. This was the main factor hindering miniaturization.

発明の目的 本発明は、以上説明してきた問題点を排除してシステム
回路の高集積化ならびに高密度実装化をはかることので
きる構造の半導体装置の提供を目的とするものである。
OBJECTS OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a structure that eliminates the problems described above and allows high integration and high-density packaging of system circuits.

発明の構成 本発明の半導体装置は、封止外殻から外部へ導出される
複数の外部リードが、プリ9ント基板に穿設された外部
リード挿通孔に挿通される直状部分を少くとも先端部に
持つ第1の外部リードと、同第1の外部リードの直状部
分の最先端部に達することのない位置で、この直状部分
の導出方向とほぼ直交する方向へ折り曲げられた先端部
分をもつ第2の外部リードとを含んで構成されたもので
あり、第1の外部リードのプリント基板の外部リード挿
通孔への差し込みで、半導体装置の固定をなし、一方、
第2の外部リードの折り曲げられた先端部分で第1の外
部リードのプリント基板の外部リード挿通孔への差し込
み深さを規制することが行われる。
Composition of the Invention In the semiconductor device of the present invention, a plurality of external leads led out from a sealed outer shell have at least a straight portion inserted into an external lead insertion hole formed in a printed circuit board at the tip thereof. a first external lead held in the body; and a distal end portion that is bent in a direction substantially perpendicular to the leading direction of the straight portion at a position that does not reach the distal end of the straight portion of the first external lead. The semiconductor device is fixed by inserting the first external lead into the external lead insertion hole of the printed circuit board;
The bent tip portion of the second external lead regulates the insertion depth of the first external lead into the external lead insertion hole of the printed circuit board.

実施例の説明 第2図は、本発明の一実施にかかるデュアルインライン
形半導体集積回路の構成を示す斜視図であシ、封止外殻
の両側面から所定数の外部リードが導出されている。図
では、一方の側面から導出される外部リード9,10,
11.12および13が明示されている。ところで、外
部リード9−11は、その導出方向に対してほぼ直角に
折り曲げられた直状部分14.15および16を持ち、
一方、外部リード12と13は、外部リード9〜11の
直状部分に対して直交する方向へ17u)曲げられた部
分17と18を持っている。そして、これらの外部リー
ドの幅は、その全長にわたって同じ幅とされている。
DESCRIPTION OF EMBODIMENTS FIG. 2 is a perspective view showing the configuration of a dual in-line semiconductor integrated circuit according to an embodiment of the present invention, in which a predetermined number of external leads are led out from both sides of a sealed outer shell. . In the figure, external leads 9, 10,
11, 12 and 13 are clearly indicated. By the way, the external lead 9-11 has straight portions 14, 15 and 16 bent approximately at right angles to the direction in which the external lead is led,
On the other hand, the external leads 12 and 13 have portions 17 and 18 that are bent (17u) in a direction perpendicular to the straight portions of the external leads 9-11. The widths of these external leads are the same over their entire length.

このような外部リードをもつ本発明の半導体装置を取り
つけることのできるプリント基板は5.外部リード9〜
11と対応させて裏面側に第1の配線が形成されるとと
もに、外部リード12と13と対応させて表面側にも第
2の配線層が形成された構造のものである。
The printed circuit board to which the semiconductor device of the present invention having such external leads can be attached is 5. External lead 9~
In this structure, a first wiring layer is formed on the back surface side corresponding to 11, and a second wiring layer is also formed on the front surface side corresponding to external leads 12 and 13.

第3図は、第2図で示したプーアルインライン形半導体
集積回路を上記の構造のプリント基板へとりつけた状態
を示す図であり、第2図のX−X線に沿って切断して示
している。図中、19.20はプリント基板5の裏面側
に形成した配線層、21、.22は表面側に形成した配
線層、23゜24.25および26は外部リードを配線
層へ固着するだめの半田である。図示するように、半導
体装置の封止外殻1から導出される外部リードの中で、
直状部分15,150をもつ外部リード1゜100がプ
リント基板6の外部リード挿通孔を貫通し、配線層19
と20へ半田23. 、24によって固着され、一方、
折り曲げ部分18,180をもつ外部リードは、その折
シ曲げ部分がプリント基板5の表面側に形成した配線層
21と22に当接し、半田25.26によって固着され
ている。
3 is a diagram showing a state in which the Puar in-line type semiconductor integrated circuit shown in FIG. 2 is attached to a printed circuit board having the above structure, and is shown cut along the line There is. In the figure, 19, 20 are wiring layers formed on the back side of the printed circuit board 5, 21, . Reference numeral 22 denotes a wiring layer formed on the front side, and 23, 24, 25 and 26 denote solder for fixing external leads to the wiring layer. As shown in the figure, among the external leads led out from the sealing outer shell 1 of the semiconductor device,
An external lead 1°100 having straight portions 15 and 150 passes through the external lead insertion hole of the printed circuit board 6 and connects to the wiring layer 19.
and 20 to solder 23. , 24, while
The external leads having bent portions 18 and 180 come into contact with wiring layers 21 and 22 formed on the front surface of the printed circuit board 5, and are fixed with solders 25 and 26.

このような取り付は構造によれば、プリント基板5の外
部リード挿通孔を貫通する外部リードによって、実装時
の固定機能が発揮され、また、折り曲げ部分をもつ外部
リードによって実装時のストッパ機能が発揮されるとこ
ろとなる。
According to the structure of this type of installation, the external leads that pass through the external lead insertion holes of the printed circuit board 5 perform a fixing function during mounting, and the external leads with bent portions perform a stopper function during mounting. This is where it will be demonstrated.

第4図は、本発明の他の実施例にかかるシングルインラ
イン形半導体集積回路を示す斜視図であり、外部リード
27.2B 、29.30および31は直状に導出され
、一方、外部リード32.33゜34および35は、そ
の先端部に、導出方間に対してほぼ直角に折シ曲げられ
た折り曲げ部分36゜37.38および39を備えてい
る。このシングルインライン形半導体集積回路でも、プ
リント基板への実装に際して、82図で示したデュアル
インライン形半導体集積回路と同等の機能が発揮される
FIG. 4 is a perspective view showing a single in-line type semiconductor integrated circuit according to another embodiment of the present invention, in which external leads 27.2B, 29.30 and 31 are led out straight, while external lead 32 .33.degree. 34 and 35 are provided with bent portions 36.degree. 37.38 and 39 at their tips, which are bent approximately at right angles to the leading direction. This single in-line type semiconductor integrated circuit also exhibits the same function as the dual in-line type semiconductor integrated circuit shown in FIG. 82 when mounted on a printed circuit board.

ところで、デュアルインライフ型半導体集積回路の外部
リードの中心線間隔(外部リードピッチ)は、MIL規
格では2.54Mとされている。第2→で示した本発明
のデュアルインライン形半導体集積回路では、各外部リ
ードそのものの幅を異らせてストッパ機能を付与する必
要はなく、外部リードの幅はその全長にわたシブリント
基板の外部リード挿通孔に差し込み可能な幅であってよ
いため、外部リード9と10.10と11の中心線間隔
を上記の2.54Mに定め、さらに、これらの間に外部
リード12と13を配置することができた。
By the way, the center line spacing (external lead pitch) of external leads of a dual-in-life type semiconductor integrated circuit is set at 2.54M according to the MIL standard. In the dual in-line semiconductor integrated circuit of the present invention shown in 2nd→, it is not necessary to provide a stopper function by varying the width of each external lead, and the width of the external lead is extended over its entire length to the outside of the syblint board. Since it may have a width that allows insertion into the lead insertion hole, the center line spacing between external leads 9 and 10, 10 and 11 is set to 2.54M, and external leads 12 and 13 are arranged between them. I was able to do that.

このような外部リード配置としたときの外部リードの中
心線間隔は、実質的には1.27鴎となり、従来のもの
の2分の1となる。したがって、パッケージの大幅な小
型化がはかられる。
When such an external lead arrangement is adopted, the center line spacing of the external leads is substantially 1.27 mm, which is one half of that of the conventional one. Therefore, the package can be significantly downsized.

発明の効果 本発明の半導体装置では、上記のように、外部リード線
の幅を従来にくらべて狭くしても、プリント基板への実
装時に外部リードの差し込み深きを規制するストッパ機
能が失われず、このため、外部リードの導出ピッチを小
さくしてパッケージの小型化をはかることが可能になる
。また、外部リードがプリント基板の外部リード挿通孔
に差し込まれる構造部分が残されているため、実装時に
半導体装置を固定するだめの手段を特に設ける必要がな
く、プリント基板への自動装着も可能となる。さらに、
本発明によれば、特定の大きさのパッケージから導出が
可能な外部リードの数が増すため、パッケージの大きさ
が特定された場合には、これに封入することのできる半
導体集積回路素子が高集積化されたものであってよく、
実質的に画集積度の半導体集積回路を実現することがで
きる。
Effects of the Invention In the semiconductor device of the present invention, as described above, even if the width of the external lead wire is narrower than that of the conventional one, the stopper function for regulating the insertion depth of the external lead when mounted on a printed circuit board is not lost. Therefore, it is possible to make the package smaller by reducing the lead-out pitch of the external leads. In addition, since there is still a structural part where the external leads are inserted into the external lead insertion holes of the printed circuit board, there is no need to provide any special means to secure the semiconductor device during mounting, and automatic mounting to the printed circuit board is possible. Become. moreover,
According to the present invention, the number of external leads that can be led out from a package of a specific size is increased, so when the size of the package is specified, the semiconductor integrated circuit elements that can be enclosed in the package are of high quality. It may be integrated,
It is possible to realize a semiconductor integrated circuit with substantially the same degree of integration.

このことは、システム回路の高集積化、高密度実装にも
繋ることであり、このシステム回路を含む機器の小型軽
量化をはかる効果をもたらす。
This leads to higher integration and higher density packaging of system circuits, and has the effect of reducing the size and weight of equipment including this system circuit.

なお、以上実施例をもって示した本発明の半導体装置で
は、外部リードの形状を父互に異るものとしているが、
この実施例の外部リード配置に限られるものではない。
Note that in the semiconductor devices of the present invention shown in the examples above, the shapes of the external leads are different from each other;
The arrangement of the external leads is not limited to that of this embodiment.

すなわち、実装時に外部リードの差し込み深さを規制す
る機能を発揮する外部リードと、プリント基板への一時
的な固定のだめの機能を発揮する外部リードとが共存し
ていれば所期の目的を達成することができる。
In other words, if the external leads that function to regulate the insertion depth of the external leads during mounting and the external leads that function as temporary fixing to the printed circuit board coexist, the intended purpose will be achieved. can do.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、既知のデュアルインライン形半導体集積回路
の外部リード形状と、この外部リードをプリント基板の
外部リード挿通孔に差し込んだ状態を示す図、第2図は
、本発明の〜実施例にかかるデュアルインライン形半導
体集積回路を示す斜視図、第3図は、第2図で示すデュ
アルインライン形半導体集積回路をプリント基板へ取シ
つけた状態を示す図、第4図は、本発明の他の実施例に
かかるシングルインライン形半導体集積回路を示す斜視
図である。 1・・・・・・封止外殻、2〜4,9〜13.27〜3
5.100・・・・・・外部リード、5・・・・・・プ
リント基板、6〜8・・・・・・外部リード挿通孔、1
4〜16゜150・・・・・・直状部分、17,18.
36〜39゜180・・・・・・折シ曲げ部分、19〜
22・・・・・・配線層、23〜26・・・・・・半田
。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第3図 第4図
FIG. 1 is a diagram showing the external lead shape of a known dual in-line semiconductor integrated circuit and the state in which the external lead is inserted into the external lead insertion hole of a printed circuit board. FIG. 3 is a perspective view showing such a dual in-line semiconductor integrated circuit, FIG. 3 is a view showing the dual in-line semiconductor integrated circuit shown in FIG. 2 mounted on a printed circuit board, and FIG. FIG. 1 is a perspective view showing a single in-line semiconductor integrated circuit according to an embodiment of the present invention. 1...Sealing outer shell, 2-4, 9-13.27-3
5.100... External lead, 5... Printed circuit board, 6-8... External lead insertion hole, 1
4-16°150... Straight portion, 17, 18.
36~39°180...Bending part, 19~
22...Wiring layer, 23-26...Solder. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 (1)封止外殻から導出される複数本の外部リードが、
実装用基板の外部リード挿通孔に挿通される直状部分を
少くとも先端部に持つ第1の外部リードと、同外部リー
ドの直状部分の最先端部に達することのない位置で、同
直状部分の導出方向とほぼ直交する方向へ折シ曲げられ
た先端部分を持つ第2の外部リードで構成されているこ
とを特徴とする半導体装置。 (2)外部リードの幅が、その全長にわたシ一定である
ことを特徴とする特許請求の範囲第1項に記載の半導体
装置。 (3)外部リードが封止外殻の対向する2側面から導出
されたデュアルインライン形パッケージ構造であること
を特徴とする特許請求の範囲第」項に記載の半導体装置
。 (4)外部リードが封止外殻の1面から整列して導9出
されたシングルインライン形パッケージ構造であること
を特徴とする特許請求の範囲第1項に記載の半導体装置
。 (6)第1の外部リードと第2の外部リードの配列が・
交互になされていることを特徴とする特許請求の範囲第
1項に記載の半導体装置。
[Claims] (1) A plurality of external leads led out from the sealing outer shell are
A first external lead having at least a straight part at its tip to be inserted into the external lead insertion hole of the mounting board, and a first external lead having a straight part inserted into the external lead insertion hole of the mounting board at a position that does not reach the leading edge of the straight part of the first external lead. 1. A semiconductor device comprising a second external lead having a tip portion bent in a direction substantially perpendicular to a direction in which the shaped portion is led out. (2) The semiconductor device according to claim 1, wherein the width of the external lead is constant over its entire length. (3) The semiconductor device according to claim 1, wherein the semiconductor device has a dual in-line package structure in which the external leads are led out from two opposing sides of the sealing shell. (4) The semiconductor device according to claim 1, wherein the semiconductor device has a single in-line package structure in which the external leads are aligned and led out from one surface of the sealing shell. (6) The arrangement of the first external lead and the second external lead is
2. The semiconductor device according to claim 1, wherein the semiconductor device is arranged alternately.
JP17503182A 1982-10-04 1982-10-04 Semiconductor device Pending JPS5963751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17503182A JPS5963751A (en) 1982-10-04 1982-10-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17503182A JPS5963751A (en) 1982-10-04 1982-10-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5963751A true JPS5963751A (en) 1984-04-11

Family

ID=15989004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17503182A Pending JPS5963751A (en) 1982-10-04 1982-10-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5963751A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6176993U (en) * 1984-10-25 1986-05-23
US5105261A (en) * 1989-03-30 1992-04-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package having particular lead structure for mounting multiple circuit boards
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5528760A (en) * 1991-01-31 1996-06-18 Samsung Electronics Co., Ltd. Data transmission/receive system and control method using dummy data to signify transmission/reception state and to detect transmission error
EP0862213A2 (en) * 1997-02-27 1998-09-02 Oki Electric Industry Co., Ltd. Semiconductor apparatus, circuit board and combination thereof
CN104576588A (en) * 2015-01-20 2015-04-29 深圳希格玛和芯微电子有限公司 Electrical equipment, integrated circuit loop of electrical equipment and circuit connection method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6176993U (en) * 1984-10-25 1986-05-23
US5105261A (en) * 1989-03-30 1992-04-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package having particular lead structure for mounting multiple circuit boards
US5528760A (en) * 1991-01-31 1996-06-18 Samsung Electronics Co., Ltd. Data transmission/receive system and control method using dummy data to signify transmission/reception state and to detect transmission error
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
EP0862213A2 (en) * 1997-02-27 1998-09-02 Oki Electric Industry Co., Ltd. Semiconductor apparatus, circuit board and combination thereof
EP0862213A3 (en) * 1997-02-27 1999-09-22 Oki Electric Industry Co., Ltd. Semiconductor apparatus, circuit board and combination thereof
US6054757A (en) * 1997-02-27 2000-04-25 Oki Electric Industry Co., Ltd. Semiconductor apparatus, circuit board and combination thereof
KR100407751B1 (en) * 1997-02-27 2004-03-20 오끼 덴끼 고오교 가부시끼가이샤 Semiconductor device
CN104576588A (en) * 2015-01-20 2015-04-29 深圳希格玛和芯微电子有限公司 Electrical equipment, integrated circuit loop of electrical equipment and circuit connection method

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