JPH01309359A - Package of semiconductor element - Google Patents

Package of semiconductor element

Info

Publication number
JPH01309359A
JPH01309359A JP63141230A JP14123088A JPH01309359A JP H01309359 A JPH01309359 A JP H01309359A JP 63141230 A JP63141230 A JP 63141230A JP 14123088 A JP14123088 A JP 14123088A JP H01309359 A JPH01309359 A JP H01309359A
Authority
JP
Japan
Prior art keywords
lead
package
semiconductor element
width
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63141230A
Other languages
Japanese (ja)
Inventor
Fushimi Yamauchi
山内　節美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63141230A priority Critical patent/JPH01309359A/en
Publication of JPH01309359A publication Critical patent/JPH01309359A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize a minute pitch by making the width of a lead smaller than a thickness. CONSTITUTION:A package of a semiconductor element is constituted of a package main body 1 and a lead 2 extracted from this main body. The lead 2 is formed in such a way that a lead width W is smaller than a lead thickness (t). A soldering operation is executed in such a way that a solder 5 is connected to sides of the lead 2 and that the solder is connected to a land 3 of a printed- circuit board 4. By this setup, a minute pitch can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体パッケージ、特に電子機器に使用され
る半導体素子パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor package, and particularly to a semiconductor element package used in electronic equipment.

〔従来の技術〕[Conventional technology]

従来の半導体素子パッケージは第３図に示すように構成
されリード２′が第４図に示すようにリード２′の幅Ｗ
よりもリード２′の厚さｔの方がより大きくなっていた
。A conventional semiconductor device package is constructed as shown in FIG. 3, and the lead 2' has a width W of the lead 2' as shown in FIG.
The thickness t of the lead 2' was larger than that of the lead 2'.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、このような上述した従来の半導体素子パ
ッケージは、リードの幅が厚さよりも大きいため細かい
ピッチ間隔のパッケージをつくれないという欠点がある
。However, the above-mentioned conventional semiconductor device package has a drawback in that it is not possible to manufacture packages with fine pitch intervals because the width of the leads is larger than the thickness.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体素子パッケージはリードの幅が厚さより
も小さくなって構成される。The semiconductor device package of the present invention is configured such that the width of the leads is smaller than the thickness.

〔実施例〕〔Example〕

次に、本発明の実施例について、図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を示す部分斜視図、第２図は
第１図に示す実施例の半田付状態を示す側面図である。FIG. 1 is a partial perspective view showing one embodiment of the present invention, and FIG. 2 is a side view showing the embodiment shown in FIG. 1 in a soldered state.

第１図に示す半導体素子パッケージはパッケージ本体１
とこれから引き出されたリード２とを含んで構成される
。The semiconductor element package shown in Figure 1 is a package body 1.
and a lead 2 drawn out from it.

このリード２は、リード幅Ｗがリード厚さｔより小さく
することで半田付はり−ド２の側面に半田５が接続しプ
リント配線板４のランド３と接続されることとなる。By making the lead width W smaller than the lead thickness t, the lead 2 is connected to the land 3 of the printed wiring board 4 by connecting the solder 5 to the side surface of the soldering beam 2.

〔発明の効果〕〔Effect of the invention〕

本発明の半導体素子パッケージは、リード幅を細くする
ことで細いピッチを実現できるという効果がある。The semiconductor element package of the present invention has the effect that a narrow pitch can be realized by narrowing the lead width.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す部分斜視図、第２図は
第１図に示す実施例の半田付状態を示す側面図、第３図
は従来の一例を示す部分斜視図、第４図は第３図に示す
リードの拡大斜視図である。 １・・・・・・パッケージ本体、２．２’・・・・・・
リード、３・・・・・・ランド、４・・・・・・プリン
ト配線板、５・・・・・・半田、Ｗ・・・・・・幅、ｔ
・・・・・・厚さ。 代理人　弁理士　　内　原　　　音 茅　１　閃 第　２　凹 茶　４　図FIG. 1 is a partial perspective view showing an embodiment of the present invention, FIG. 2 is a side view showing the soldered state of the embodiment shown in FIG. FIG. 4 is an enlarged perspective view of the lead shown in FIG. 3. 1...Package body, 2.2'...
Lead, 3... Land, 4... Printed wiring board, 5... Solder, W... Width, t
······thickness. Agent Patent Attorney Uchihara Otokyo 1 Sendai 2 Kocha 4 Diagram

Claims (1)

【特許請求の範囲】[Claims] 　パッケージ本体と、このパッケージ本体から引き出さ
れ幅が厚さよりも薄く側面に半田付するためのリードと
を含むことを特徴とする半導体素子パッケージ。1. A semiconductor element package comprising a package body and a lead drawn out from the package body and having a width thinner than a thickness and for soldering to a side surface.
JP63141230A 1988-06-07 1988-06-07 Package of semiconductor element Pending JPH01309359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63141230A JPH01309359A (en) 1988-06-07 1988-06-07 Package of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63141230A JPH01309359A (en) 1988-06-07 1988-06-07 Package of semiconductor element

Publications (1)

Publication Number Publication Date
JPH01309359A true JPH01309359A (en) 1989-12-13

Family

ID=15287137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63141230A Pending JPH01309359A (en) 1988-06-07 1988-06-07 Package of semiconductor element

Country Status (1)

Country Link
JP (1) JPH01309359A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444905B1 (en) * 1998-12-24 2002-09-03 Hitachi, Ltd. Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444905B1 (en) * 1998-12-24 2002-09-03 Hitachi, Ltd. Semiconductor device
US6541702B2 (en) 1998-12-24 2003-04-01 Hitachi, Ltd. Semiconductor device
US6553657B2 (en) 1998-12-24 2003-04-29 Hitachi, Ltd. Semiconductor device
US6777262B2 (en) 1998-12-24 2004-08-17 Renesas Technology Corp. Method of packaging a semiconductor device having gull-wing leads with thinner end portions

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