JPS61144025A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the yield, by preventing a polymeric film from being formed by a gas used in the dry etching process and reducing the overetching of gallium arsenide, GaAs providing a substrate. CONSTITUTION:According to the present dry etching process, products obtained from a gas containing nitrogen trifluoride, NF3 are a fluoride (e.g., ReF) and a nitride (e.g. NF<+>2), which are all volatile materials. Therefore, the substrate can be uniformly etched without formation of an inactive film, which would be formed as a carbonic polymeric film if a conventional carbon fluoride is used. Further, since no inactive film is formed, it is not required additional oxygen during the etching process and therefore the overetching of GaAs can be substantially reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the manufacture of semiconductor devices using rhenium (Its) as a heat-resistant gate material for gallium arsenide field effect transistors (hereinafter referred to as G&Ms FETs). It is about the method.

Conventional technology GaAsFET has an electron mobility of 6 compared to silicon.
Due to its excellent characteristics of being ~6 times larger, it has been put into practical use as an ultra-high-speed device. In recent years, self-alignment methods using heat-resistant gates have been developed as a method to reduce parasitic resistance in order to further improve high-speed performance.
t method (hereinafter abbreviated as SM method) has been proposed.

An example of a method for manufacturing a semiconductor device by the SA method using the above-mentioned conventional heat-resistant gate will be described below with reference to the drawings.

FIGS. 2a, b, c, d, and e, FIGS. 3 and 4 show each step of a conventional method for manufacturing a semiconductor device.

In Figure 2 a, b, c, d, e, Figure 3, Figure 4,
1 is a gallium arsenide (GaAs) semi-insulating substrate.

2 is the active layer that becomes the channel of G & Mus FICT, 2
1L is an over-etched part of the active layer that has been dry-etched, 3 is a high-melting point metal material film that becomes the gate of the G&Ms FIT, and 3a is a high-melting-point metal material film 3 that has been dry-etched using an etching mask 4. 3b is an etched recess formed by the inert film 9 generated during the dry etching, 6 is an n+ implanted part into which selective ions are implanted, and 6 is a part where the n+ implanted part 6 is selectively formed. 7 is a cap used for final annealing to activate the n+ layer 6&, and 8 is a cap used for the final annealing to activate the n+ layer 6&. ! These are ohmic electrodes that serve as the source and drain electrodes of FICT.

A method of manufacturing the semiconductor device configured as described above will be described below.

First, tungsten (
W) and titanium tungsten silicide (Ti/W
A high melting point metal material film 3 such as 5 ilicle) is formed, and an etching mask 4 that serves as a mask during etching of the high melting point metal material film 3 is formed of silicon dioxide (SiO□) or the like (FIG. 2a). Next, using the etching mask 4, the high melting point metal material film 3 is patterned by dry etching with a gas containing carbon fluoride to form a heat-resistant film).
32L (Figure 2b). Next, the n-type implanted portion 6, which will become the source and drain of the GaAs FICT, is formed by the SM method, which involves selective ion implantation of silicon using an ion implantation mask 6 formed of the heat-resistant gate 3 and an insulating film, etc. (FIG. 2). C). Furthermore, after removing the ion implantation mask 6, a cap 7 made of a silicon oxide film is formed on the entire surface, and then annealing is performed at approximately SOO° C. for approximately 20 minutes to activate the silicon implanted into the n-implanted region 6. to form an n+ layer 6a (FIG. 2d). Note that the n layer 51L
become the sheath and drain of the GaAsFKT.

Next, a mu-Go based ohmic electrode 8 is formed on the n+ layer 51L to serve as the source and drain electrodes of the G&M FKτ (FIG. 2e). (for example.

Written by Yokoyama (N, τOKOYAM) et al., IKICKT
r&n5actions on Electron D
evices.

VOL, KD-29, No. 10. PP1541-15
47 (1es2) 8th edition). As described above, by the SM method using a heat-resistant gate, a source/drain can be formed near the gate without mask alignment, parasitic resistance is reduced, and the characteristics of GaASF ICT are improved.

Problems to be Solved by the Invention However, in the above configuration, the refractory metal material film 3 is patterned by dry etching using a gas containing carbon fluoride, as explained using FIG. 3&, in dry etching using a gas consisting only of carbon fluoride, as shown in FIG. The film 9 is partially formed, slowing down the etching speed, and becoming non-uniform, creating etching recesses 3b, making it difficult to detect the end point of etching. When about 6% oxygen (02) is mixed into the carbon fluoride to remove the film 9, the etching rate of GaAs is high and an over-etched area 2a as shown in FIG. 4 is produced. It had a point.

In view of the above-mentioned problems, the present invention is aimed at eliminating the formation of an inert film by the gas of the dry etching when rhenium (Re), which is a high-melting metal material, is used to form a heat-resistant gate by dry etching. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that reduces overetching of gallium oxide (GILA!), has good reproducibility, and improves yield.

Means for Solving the Problems In order to solve the above-mentioned problems, the method for manufacturing a semiconductor device of the present invention uses rhenium (R) on gallium arsenide (GaAs).
e) Layer or layer = Ram aluminum alloy (ReA
, lx, O < x < 40) layer;
A step of forming a gate mask pattern on the rhenium (Re) layer or the aluminum alloy (R・M1X, O<1<40> layer) and nitrogen trifluoride (NF3
) by dry etching using a gas containing

Depending on the mask pattern, the rhenium (Re) layer may be formed of a rhenium-aluminum alloy (ReAlx).

0<X<40) layer.

Effect of the present invention With the above-described configuration, the product of gas containing nitrogen trifluoride (IF) in dry etching is fluoride (Nium fluoride ReF etc.) and nitride (For example I
F2+, etc.) Since all of them are volatile substances, an inert film (9 in Figure 3), which is probably a carbon-based polymer film by using carbon fluoride as shown in the conventional example, is formed. Uniform etching is performed without any unevenness. Furthermore, since the inert film is not formed, there is no need to mix oxygen into the etching gas (over-etching of GaAs can be reduced).
This results in an improvement in yield.

EXAMPLE Hereinafter, a method for manufacturing a semiconductor device according to an example of the present invention will be described with reference to the drawings. Figure 1 a, b, c, a
, e indicate each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

In Figure 1 ' I bl ' l d l ', 2
1 is a gallium arsenide (GaAs) semi-insulating substrate, 22 is a G
23 is a rhenium (Re) layer which is the gate material of G&55FIT;
is etched by etching the rhenium (Re) layer 23.
A second etching mask 26 is used to form the AsFICT heat-resistant gate 23L and the etching mask 24 using the SM method.

Formed by selective ion implantation? An implantation part, 26° 26 & is a silicon oxide film mask and a photoresist mask, respectively, which serve as masks for forming the n+ implantation part 26, and 27 is a mask for activating the n+ implantation part 26 and forming an n layer 252.
The cap 28 used for annealing, which is carried out during annealing, is a mu-Go based ohmic electrode that becomes the source and drain electrodes of the GaAs F IET.

A method of manufacturing a semiconductor device configured as described above will be described below with reference to FIGS. 1a, b, c, a, and e.

First, gallium arsenide (
(GaAs) selective ion implantation into the semi-insulating substrate 21 (implanted ions: 29S Tsuji, acceleration voltage 120KeV).

Injection volume: 6 x 1012dose/cI and 850
'C20 minute annealing f), GALA! ! F'
An active layer 22 that will become a channel for ET is formed, and then the substrate temperature is set to about 180° C., and rhenium (Re) is evaporated with an electron beam [B] to form a rhenium (Re) layer 23 with a thickness of about 0.26 μm. Further, by a lift-off method, rhodium (Rh) is formed to a thickness of about 0.2 μm on the gate pattern of the GaAsF ICT, and this is used as an etching mask 24 for the rhenium (Re) layer 23 (FIG. 1a). Next, a mixed gas of 5,500 M of nitrogen trifluoride (IF3) gas and 205 CCM of argon (MR) gas was added at a pressure of about 60
m Torr, generate a gas plasma of the above mixed gas by high frequency (13.5 eMHz), and high frequency power 1
1 reactive ion etch (RKACTIVE I) at 60W
ON ETCH, (RIE)) El.

Using the etching mask 24, the rhenium layer 2 is
3 dry etching for about 8 minutes, heat-resistant gate 23
& (Fig. 1b). The dry etching device used was DEM451 manufactured by Ichiden Anelva. l shown in Figure 1.

The side etch length when forming the heat-resistant gate 23& is about 0.06 μm, and the degree of anisotropy (side etch length l/etching depth) is about 0.2, indicating good anisotropic etching. I was able to do it.

Furthermore, the existence of the side etching length l makes the gate length of the heat-resistant gate 231L shorter than that of the etching mask 24 formed by the lift-off method.
This will lead to improvement of the high frequency characteristics of the F IET, and will also serve as the source and drain of the GaAs F RT. By slightly isolating the injection layer 26 and the heat-resistant gate 23&, the effect of improving the gate breakdown voltage can also be obtained (
(See Figure 1).

Next, reduced pressure CV D ([heimical Tape
After forming a silicon oxide film by the rDeposition method, the silicon oxide film was etched using a photoresist mask 2 (51L) formed by photolithography to form a silicon oxide film mask 26.

2834+ was etched at 150Ke by the SA method using the etching mask 24 and the heat-resistant gate 23 as masks.
An n+ implantation layer 25 is formed by selectively implanting ions at V, 5x1o dose/cnL (FIG. 1C).

Next, after removing the photoresist mask 261L and the silicon oxide film mask 26, heat treatment is performed in 350'C hydrogen (4) for one hour. Thereafter, using a silicon oxide film cap 27 formed by sputtering, annealing is performed at 750° C. for 20 minutes to activate the + n injection layer 25 and form an n + layer 251L (first
Figure d).

Next, after removing the cap 27, a 5U-Go based ohmic electrode 28 is formed on the sand layer 251L, and the GaA
This is used as the source-drain electrode of gFET (Fig. 1e).

Each gas composition in the conventional example and the above-mentioned embodiment of the present invention was used. Rhenium (Re) and gallium arsenide (GaA
The etching speed in the dry etching of s) is shown in the table.

Table In the conventional example of the etching rate table, only the gas composition is calculated using carbon tetrafluoride (OF4).
) Gas alone or a mixed gas of hydrogen tetrafluoride (CF4) and oxygen (02, s%) was used, and the dry etching conditions (high frequency power, gas pressure, and equipment used) were the same as those described in the present invention. This is the same as that shown in the first embodiment. From the table, as mentioned in the conventional example, if only the carbon tetrafluoride gas (OF4) is used, the etching rate varies greatly, and the carbon tetrafluoride (CF4) and oxygen (O2
, sX), the etching rate is stabilized, but the etching rate of gallium arsenide (GaAs) increases. In contrast, it can be seen that one embodiment of the present invention has excellent effects in that the etching rate is significantly stable and the etching rate of gallium arsenide (GaAs) can be lowered.

In the above embodiment, the etching mask 24 was made of rhodium (Rh), but the etching mask 24 had sufficient adhesion to the heat-resistant gate 23&.

Any material that is stable at 1v (approximately 750' (15 minutes) and serves as a mask for dry etching1) may be used.For example, iridium (Ir), osmium (O8), etc.
etc. can be used. Although the heat-resistant gate 231L is made of rhenium (Ra), it may be made of an alloy of rhenium (Re) and aluminum (Mul) (ReA$, O<)C<40). However, ReA
When lx, 40≦X, annealing causes σaAS
Good Schottky characteristics as a FlcT gate could not be maintained. Furthermore, in the above embodiment, the gas used for dry etching is nitrogen trifluoride (NF3) gas ssc.
Although the mixed gas of cM and argon (Ar) gas 20 SCCM was used, the dry etching conditions and anisotropy may vary, but any gas containing nitrogen trifluoride (Ir3) gas may be used. It is also possible to use a mixed gas with helium (He) gas or the nitrogen trifluoride (NF3) gas alone.

Effects of the Invention As described above, the present invention includes a step of forming a rhenium (Re) layer or a rhenium-aluminum alloy (ReAgx, O<X<40) layer on gallium arsenide (GaAs), and layer or rhenium-71
v Milam alloy (ReAlx, O<X<40
) layer, and by dry etching using a gas containing nitrogen trifluoride (NF3), the rhenium (
Re) Ni'[, <Halenium O aluminum alloy (R
By including the step of selectively etching the layer (ehlx, 0<x<40), there is no formation of a polymer film due to the dry etching gas, and there is less over-etching of gallium arsenide (GaAs), which serves as the substrate, making it easy to reproduce. It has good properties and improves yield. A GzAsFET can be manufactured by the SA method using a heat-resistant gate material.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device, and FIGS. FIG. 1.21... Gallium arsenide (GaAs) semi-insulating substrate, 2,22... Active layer, 3...
High melting point metal material film, 23... Rhenium (Re)
Layer, 3a, 23! L... Heat resistant gate, 4
, 24...Etching mask, 51L, 25&
......n ten layers, 7.27...cap,
8.28...Ohmic electrode, 9...
Inert membrane. Name of agent: Patent attorney Toshio Nakao and 1 other person22
... S7 J Dano) 41st layer 23...1121st layer? 4...Etching mask 0,...,,work,-1 25...Rutshi master layer//'1 Fig. 1 27...No.1 z5oL-n+i9? 8...Omi tsuku sare 1 murmur i 3...Otsuv voice sakura material binding 4...1...Noden 7'' square 2 Fig. 2 Fig. 3 Fig. 3...Takasoe Eimaro Genus Ha〃Isaki 3b...Engineering/Sochin 2゛Concave p 9...Iji +, Ikuto Rin 4 Figure 2a, - Oberue Sochingu Iku Δ Procedural amendment (method) % formula % 2 Name of the invention Semiconductor Relationship with the Case of Person Who Amends Device Manufacturing Method 3 Patent Application Address 1006 Oaza Kadoma, Kadoma City, Osaka Name
(582) Matsushita Electric Industrial Co., Ltd. Representative Yama
Toshihiko Shimo 4 Agent 571 Address 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 6 Amendment Order Date 7, Details of Amendment, Page 4, Line 18 to Page 6, Line 1 'II
EKE...Reference" will be corrected as follows. [Institute of Electrical and Electronics Engineers, Meeting on Electronic Devices, Vol. 29, No. 10, pp. 1541-1547, 198
2nd year reference (IKKICTTransactionson
IC1ectron Devices, VoI,,
HD-29, No. 10, PP1541-1547 (1982))
”

Claims (1)

[Claims] When manufacturing gallium arsenide field effect transistors, a rhenium (Re) layer or a rhenium-aluminum alloy (ReAlx, 0<x<4
0) layer forming step, and the step of forming the rhenium (Re) layer or rhenium-aluminum alloy (ReAlx, 0<x
<40) By forming a gate mask pattern on the layer and dry etching using a gas containing nitrogen trifluoride (NF_3), the rhenium (Re) layer or the rhenium-aluminum alloy ( A method for manufacturing a semiconductor device, comprising the step of selectively etching a ReAlx (0<x<40) layer.