JPS61143841A - トランスフアゲ−トを用いた論理回路 - Google Patents

トランスフアゲ−トを用いた論理回路

Info

Publication number
JPS61143841A
JPS61143841A JP59265609A JP26560984A JPS61143841A JP S61143841 A JPS61143841 A JP S61143841A JP 59265609 A JP59265609 A JP 59265609A JP 26560984 A JP26560984 A JP 26560984A JP S61143841 A JPS61143841 A JP S61143841A
Authority
JP
Japan
Prior art keywords
circuit
transfer
transfer gate
transfer gates
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59265609A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0421890B2 (enExample
Inventor
Kazumitsu Takeda
武田　和光
Kenji Maehara
健二 前原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59265609A priority Critical patent/JPS61143841A/ja
Publication of JPS61143841A publication Critical patent/JPS61143841A/ja
Publication of JPH0421890B2 publication Critical patent/JPH0421890B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
JP59265609A 1984-12-17 1984-12-17 トランスフアゲ−トを用いた論理回路 Granted JPS61143841A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59265609A JPS61143841A (ja) 1984-12-17 1984-12-17 トランスフアゲ−トを用いた論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59265609A JPS61143841A (ja) 1984-12-17 1984-12-17 トランスフアゲ−トを用いた論理回路

Publications (2)

Publication Number Publication Date
JPS61143841A true JPS61143841A (ja) 1986-07-01
JPH0421890B2 JPH0421890B2 (enExample) 1992-04-14

Family

ID=17419509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59265609A Granted JPS61143841A (ja) 1984-12-17 1984-12-17 トランスフアゲ−トを用いた論理回路

Country Status (1)

Country Link
JP (1) JPS61143841A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0253135A (ja) * 1988-08-17 1990-02-22 Toshiba Corp 加算器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0253135A (ja) * 1988-08-17 1990-02-22 Toshiba Corp 加算器

Also Published As

Publication number Publication date
JPH0421890B2 (enExample) 1992-04-14

Similar Documents

Publication Publication Date Title
US5656948A (en) Null convention threshold gate
US6535902B2 (en) Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability
US5664211A (en) Null convention threshold gate
EP0097779A1 (en) Logic circuit
US6900658B1 (en) Null convention threshold gate
Thoidis et al. The circuit design of multiple-valued logic voltage-mode adders
JPH0716158B2 (ja) 出力回路およびそれを用いた論理回路
JP3247114B2 (ja) しきい値式によって表わすことができる論理エレメントを実現するための回路装置
Lu et al. Evaluation of two-summand adders implemented in ECDL CMOS differential logic
US8306178B2 (en) vMOS multi-valued counter unit
US6066978A (en) Partial product generating circuit
US4536855A (en) Impedance restoration for fast carry propagation
US7298171B2 (en) Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices
JPS61143841A (ja) トランスフアゲ−トを用いた論理回路
JPH01166128A (ja) キャリィルックアヘッド回路
Lu A safe single-phase clocking scheme for CMOS circuits
JP3741280B2 (ja) 桁上げ先見回路およびこれを用いた加算回路
Andreev et al. Tapered transmission gate chains for improved carry propagation
JP3137629B2 (ja) 桁上げ‐セーブ算術演算機構に対する加算器セル
JP2539006B2 (ja) 加算器
US6219686B1 (en) Method and apparatus for an N-NARY sum/HPG adder/subtractor gate
JP3135471B2 (ja) デジタルオペランドフォーマッティング回路
Shahrin et al. Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology
US6219687B1 (en) Method and apparatus for an N-nary Sum/HPG gate
US6567836B1 (en) Multi-level carry-skip adder