JPS61141116A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPS61141116A
JPS61141116A JP26336484A JP26336484A JPS61141116A JP S61141116 A JPS61141116 A JP S61141116A JP 26336484 A JP26336484 A JP 26336484A JP 26336484 A JP26336484 A JP 26336484A JP S61141116 A JPS61141116 A JP S61141116A
Authority
JP
Japan
Prior art keywords
thin film
substrate
composition
xgex
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26336484A
Other languages
Japanese (ja)
Inventor
Hiroyuki Oshima
弘之 大島
Hideaki Iwano
岩野　英明
Hiroshi Komatsu
博志 小松
Yoshifumi Tsunekawa
吉文 恒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26336484A priority Critical patent/JPS61141116A/en
Publication of JPS61141116A publication Critical patent/JPS61141116A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To contrive the improvement in crystallizability of a Ge thin film by alleviating the mismatching of the lattice by changing a composition ratio x of the Si1-xGex, which is arranged between an Si substrate and a Ge thin film as a buffer layer, from x=0 to x=1 continuously and monotonously from the Si substrate side toward the Ge thin film. CONSTITUTION:On an Si substrate 101, an Si1+xGex thin film 102 which is to be a buffer layer is formed and a Ge thin film 103 and a GaAs thin film 104 are formed on that. A composition ratio x of the Si1-xGex thin film is x=0, i.e., the composition of Si in the position where it contacts with the underlying Si substrate 101, and x=1, i.e., the composition of Ge in the position where it contacts with the Ge thin film 103 above. Between them, a value of x changes continuously and monotonously from 0 to 1 and the mismatching between Si and Ge is alleviated. The Si1-xGex thin film can be formed by a reduced CVD method using monosilane gas and german gas. As the composition ratio x is controlled by a flow ratio of the gas, it can be changed as it is desired by changing a gas flow ratio continuously and monotonously.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、化合物半導体デバイス用の半導体基板忙関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor substrates for compound semiconductor devices.

〔従来の技術〕[Conventional technology]

近年、０（Ｌ　ＡＡＩを始めとする化合物半導体材料を
用い定デバイスの研究が活発に行な、われている。In recent years, research on fixed devices using compound semiconductor materials such as LAAI has been actively conducted.

これｋは、高純度で欠陥密度の小ざい単結晶半導体基板
が不可欠である。This k requires a single crystal semiconductor substrate of high purity and low defect density.

従来、化合物半導体の単結晶基板としては、ＧＩＺ　１
８や工ｎｐが用いられているが、基板サイズが小さい上
に高価であるという難点を抱えている危め、Ｓｉ単結晶
基板上にＧａＡ＆の単結晶薄膜をエピタキシャル成長プ
せ、これを化合物半導体デバイス用の単結晶基板として
用いようとする試入が行なわれている（例えば、ＷＺｔ
ｇｎｄａｄ　ｋｂ８ｔｒａｃｔ８０ｆ　ｔｈｅ　１６ｔ
ｈ（１９８４Ｉｎｔｅｒｎａｔｉｏｎａｌ、ｌ　　０ｏ
ｎｆｔｒｅｎｃｅ　　ｏｎｓｏｌｉｄ。Conventionally, GIZ 1 has been used as a single crystal substrate for compound semiconductors.
8 and NPs have been used, but they have the disadvantages of small substrate size and high cost. Therefore, a single crystal thin film of GaA and silicon is grown epitaxially on a Si single crystal substrate, and this is used for compound semiconductor devices. (For example, WZt
gndad kb8tract80f the 16t
h (1984 International, l 0o
nftrence on solid.

８ｔａｔｔ　Ｄｅｖｉｃｅｓ　ａｎｄ　Ｍａｔｅｒｉａ
ｌｓ、ｐ、　１１５．１９８４）ｆａ２図は、この従来
の半導体基板の構成を示す断面図である。Ｂｉ単結晶基
板２０１上ＩＣＧｅ薄膜２０２が形成され、メら忙該Ｇ
ｅ薄膜上ＶｃＧｎ、に８薄膜が形成メれている。8tatt Devices and Materia
ls, p, 115.1984) FA2 is a sectional view showing the structure of this conventional semiconductor substrate. An ICGe thin film 202 is formed on a Bi single-crystal substrate 201.
Eight thin films were formed on the VcGn thin film.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、このよ’＋に構成ばれ友従来の半導体基板は次
のような欠点を有している。すなわち、下の表ＩＶＣ示
すよ）に、ＧｅとＧ（Ｌ　Ａｌ１の格子定数及び線膨張
係数は非常建良く一致し、極めて良好な結晶成長が可卵
であるが、８ｉとＧｅは格子定数ｈ’−約４％、線膨張
係数が約１．８倍、それぞれ異なるため、Ｓｉ上のＧｅ
薄膜のエビタキクヤル成長は極めて困難である。このた
め、Ｓｉ上のＧｅ中には多くの転位ｈ′−存在し、界面
準位密度も高い。こｈらは表　　　１ Ｇｅ　Ｊ：に形成されるＧσＡ８薄膜の結晶性にも悪影
響を与え、欠陥密度の低い良質なＣｋｎ、ｋＳ薄陣を実
現することｈζ困難であった。However, conventional semiconductor substrates having such a structure have the following drawbacks. In other words, as shown in Table IVC below, the lattice constants and linear expansion coefficients of Ge and G (L Al1 agree very well, and extremely good crystal growth is possible, but 8i and Ge have a lattice constant h ' - about 4%, and the linear expansion coefficient is about 1.8 times different, so Ge on Si
It is extremely difficult to grow thin films. Therefore, many dislocations h'- exist in Ge on Si, and the density of interface states is high. These also adversely affected the crystallinity of the GσA8 thin film formed in Table 1 Ge J:, making it difficult to realize a high-quality Ckn, kS thin film with low defect density.

未発明はこのよ５な従来の問題点を解決するものであり
、その目的とするところはＳｉ基板上に結晶性の良好な
ＧＱ、　ＡＳＳ薄紫有する半導体基板を提併するところ
にある。The present invention is intended to solve these five conventional problems, and its purpose is to provide a semiconductor substrate having good crystallinity of GQ and ASS light purple on a Si substrate.

ｒ問題点を解決するための手段〕 本発明は前記Ｓｉ基板と前記Ｇｅ薄膜の間に。rMeans for solving problems] The present invention is provided between the Si substrate and the Ge thin film.

Ｓｊ、、　Ｇｅ　ｘ薄膜を７９７７層として設けたこと
を特徴とする。また、ｌｌｆ　Ｓｊ、、　Ｃｋｅ　Ｚ薄
膜の組成比χをｓｉ基板側からＧｅ薄１ｔｉ忙向けて、
ｘ＝０からＸ＝１まで連続的かつ単調に変化させたこと
ｔｔ％微とする。It is characterized by having 7977 layers of Sj, Ge x thin films. In addition, the composition ratio χ of the llf Sj, Cke Z thin film is directed from the Si substrate side to the Ge thin 1ti layer,
It is assumed that the value is changed continuously and monotonically from x=0 to x=1 by tt%.

〔作用〕[Effect]

本発明の上記の構成によれば、格子不整合の大きいＳｉ
基板とＧｅ薄膜の間忙１両者の中間的な性質を有する５
ｉ１−エａｅ　Ｚ薄膜を設けるため、格子不整合が緩和
謬れる。また、組成比２を連続的１ｃ変化させること罠
より、Ｓｉの組成からＧｅの組成に至るまで５ｉ１−エ
ａｅ　Ｚ薄膜の組成がなめらかに変化し、より一層、格
子不整合を緩和することができる。このため、Ｓｉ上に
形成；れｆｌ−（１ｇ薄膜の結晶性を著しく改善するこ
とができる。According to the above configuration of the present invention, Si with large lattice mismatch
Between the substrate and the Ge thin film 1 Has intermediate properties between the two 5
Since the i1-air ae Z thin film is provided, the lattice mismatch can be alleviated. In addition, by continuously changing the composition ratio 2 by 1c, the composition of the 5i1-air Z thin film changes smoothly from the Si composition to the Ge composition, which further alleviates the lattice mismatch. can. Therefore, the crystallinity of a 1g thin film formed on Si can be significantly improved.

〔実施例〕〔Example〕

第１図は１本発明の実施例における半導体基板１の断面
図である。Ｓ＜基板１０１上に、バー１７ア層となるｓ
ｉ、、ｚａｅ　Ｚ薄膜１０２が形成されてかり、その上
にＧｅ薄膜１０３とＧＡ　Ａ＆薄膜１０４が形成されて
いる。ま友ｇｉ、、　ａｅ　ｒ；薄膜の組成比２け、下
のＳｉ基板１０１と接する位置でけｚ＝０、ナなわちＳ
ｉの組成となっており、十のＧｅ薄＠１０３と接する位
置でけｘ＝１．すなわちＧｅの組成とｔ「つている。FIG. 1 is a sectional view of a semiconductor substrate 1 in an embodiment of the present invention. S<s to become the bar 17a layer on the substrate 101
A Z thin film 102 is formed, and a Ge thin film 103 and a GA A& thin film 104 are formed thereon. Mayugi,, ae r; The composition ratio of the thin film is 2 digits, and the position in contact with the lower Si substrate 101 is z=0, that is, S
The composition is x=1. In other words, t is similar to the composition of Ge.

その間では、Ｘの値け０から１まで連続的かつ単調に変
化し、ＳｉとＧｅ間の不整合を緩和している。In between, the value of X changes continuously and monotonically from 0 to 1, thereby alleviating the mismatch between Si and Ge.

上述のＳｔ、１−ｚ　Ｇｖ　ｚ　ｉ９膜は、例えばモノ
シラン（Ｂｉ　Ｈ４）ガスとゲルマン（ＧｅＨ４）ガス
を用いて減圧０ＶＤ（化学気相成長）法忙より形成する
ことｈｔできる。組成比Ｘけそり、ぞｈのガスの流量比
により制御でれガス流量比を連続的かつ単調に変化シせ
ることにより組成比Ｘ″１ｒ＋’５ｉ望辿９忙賓えるこ
とができる。The above-mentioned St, 1-z Gv z i9 film can be formed by a low pressure 0VD (chemical vapor deposition) method using, for example, monosilane (BiH4) gas and germane (GeH4) gas. By continuously and monotonically changing the gas flow rate ratio, which can be controlled by the gas flow rate ratio of the composition ratio X, the composition ratio X''1r+'5i can be adjusted.

第３図は、本発明による半導体基板における格子定数の
深情分布を模式的忙示すグラフである。FIG. 3 is a graph schematically showing the deep distribution of lattice constants in a semiconductor substrate according to the present invention.

縦軸は格子定数であり、横軸は深さ方向の位置を表わし
ているつ点ＡけＳｉ基板とＳｉ、−エＧ４　Ｚ　　薄膜
との界面を１点ＢはＳＳｉ１−２Ｇ　Ｚ薄膜とＧｅ薄膜
との界面を、点ＣけＧｅ薄膜とＧ（Ｌ　ＡＩ９薄嗅との
界面をそれぞれ示している。図より明らかなよへに、Ｓ
ｉ基板の格子定数とＧｅ薄膜の格子定数の差を、バ・・
）７層のＳｉ、、ＧＩＺ薄模が徐ＡＫ緩和している。The vertical axis is the lattice constant, and the horizontal axis is the position in the depth direction. Point A is the interface between the Si substrate and the Si, -G4 Z thin film. Point B is the interface between the SSi1-2G Z thin film and the Ge thin film. Point C indicates the interface between the Ge thin film and G(LAI9).As is clear from the figure, S
The difference between the lattice constant of the i-substrate and the lattice constant of the Ge thin film is
) 7-layer Si, GIZ thin pattern exhibits gradual AK relaxation.

従来は、バッファ層となるｓ７．−πＧｖ　ｚ薄膜が存
在しなかつたために、ｌｐＡと点Ｂが一致しており、格
子定数が不連続ＶＣ！化し、Ｇｅ薄膜とＧｃｙ、Ａｓ薄
膜の結晶性に悪影４ｔを及ぼして（／にた。Conventionally, s7. -πGv z Since there was no thin film, lpA and point B coincide, and the lattice constant is discontinuous VC! , which has a negative impact on the crystallinity of Ge thin films, Gcy, and As thin films.

〔発明の効果〕〔Effect of the invention〕

本発明は以下忙述べるよ５な効果を有している。 The present invention has five effects as described below.

第１Ｔ／Ｃ１Ｓｉ基板上忙結晶性の優れたａａ　１ｇ薄
膜を形成することができる。これは、剪述の如く、バ・
Ｈ７ァ層と【７てｅｉ、４　ａｓ　ｚ薄膜を設けたこと
Ｋよる。これによりＥ４ｉ＄板上のＧｅ薄膜の結晶性が
改善ばれ、この結果、欠陥密度の小ざい良好なａａＡｓ
薄膜を形成することができる。An aa 1g thin film with excellent crystallinity can be formed on the first T/C1Si substrate. This is, as stated above,
This is due to the fact that the H7a layer and the [7tei, 4asz thin film were provided. This improves the crystallinity of the Ge thin film on the E4i$ plate, resulting in a good aaAs film with a small defect density.
A thin film can be formed.

第２に、　上記に伴って、ｓｉ基板上Ｋ　５（ＬｋＢを
用いた化合物半導体デバイスを形成することがで舞る。Second, along with the above, it is possible to form a compound semiconductor device using K5 (LkB) on a Si substrate.

このようなデバイスとしては、半導体レーザなどの発光
デバイスや、トランジスタなどの高速デバイスミｔ挙げ
られる。発光デバイスでは、ＧＣＬｋ８薄膜中の結晶欠
陥は非発光再結合中心となる定め効率の骨減（出力の減
少）やしきい値電流の増大などの悪影響を及ぼす。高速
デバイスでは、ＧＩＺＡＳ薄膜中の結晶欠陥はキャリア
の散乱源となるため移動度の減少（動作速度の低下）な
どの悪影響を及ぼす。本発明によれば、結晶欠陥の少な
いＧＣＬＡＲ薄１＠に＊現で＾る友め、Ｓｉ基板上に高
性能な化合物半導体デバイス、を実現中ることｈｉでき
る。Such devices include light emitting devices such as semiconductor lasers and high speed devices such as transistors. In light emitting devices, crystal defects in the GCLk8 thin film become non-radiative recombination centers and have negative effects such as loss of efficiency (reduction in output) and increase in threshold current. In high-speed devices, crystal defects in the GIZAS thin film become a source of carrier scattering, resulting in negative effects such as a decrease in mobility (decreased operating speed). According to the present invention, it is now possible to realize a high-performance compound semiconductor device on a Si substrate using a thin GCLAR with few crystal defects.

第３に、安価で大面積の半導体基板を提供することがで
きる。ｓ７１仮は、大量の需要を背景として、直径５イ
ンチとい）大面積基板が極めて安価に供給されている。Thirdly, it is possible to provide an inexpensive, large-area semiconductor substrate. Due to the large demand for s71, large-area boards (5 inches in diameter) are being supplied at extremely low prices.

しかも公害や資源枯渇の心配／）；　ｒ（い。このよ’
ＩＫ恵まれたＳｉ基板上にＧａＡ、９薄嘆が形成でき、
化合物半導体デバイスを実現できることは極めて大会す
長所である。Moreover, there are concerns about pollution and resource depletion.
GaA, 9-thickness can be formed on the IK-rich Si substrate,
The ability to realize compound semiconductor devices is an extremely advantageous feature.

以上述べ几よ５に１本発明は数多〈の優れた効果を有す
るものである。As stated above, the present invention has numerous excellent effects.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による半導体基板の構造を示す断面図で
ある。 第２図は従来の半導体基板の構造を示＋断面図である。 第３図は本発明の半導体基板忙おける格子定数の深ζ方
向変化？示ナグラフである。 １０１゜２０１川・・・Ｂｉ単結晶基板１０２−曲５ｆ
ｆｌ、−，Ｇｅ　ｘ　＠膜１０３　、２０２　・−・−
・・ａｔｔ　＠嗅１ｎ４　、２０３　・−−−−・Ｇａ
　Ａａ薄模以　　上 出履人　株式会社　諏訪精工舎 第２図 第３図FIG. 1 is a sectional view showing the structure of a semiconductor substrate according to the present invention. FIG. 2 is a sectional view showing the structure of a conventional semiconductor substrate. Figure 3 shows the change in the lattice constant in the depth ζ direction in the semiconductor substrate of the present invention. This is a graph. 101゜201 River...Bi single crystal substrate 102-curve 5f
fl, −, Gex @ film 103, 202 ・−・−
・・att@olfactory1n4, 203 ・----・Ga
Aa thin model or above, Suwa Seikosha Co., Ltd. Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）Ｓｉ単結晶基板上にＳｉ＿１＿−＿ｘＧｅ＿ｘを
有し、該Ｓｉ＿１＿−＿ｘＧｅ＿ｘ薄膜上にＧｅ薄膜を
有し、該Ｇｅ薄膜上にＧａＡＳ薄膜を有することを特徴
とする半導体基板。(1) A semiconductor substrate comprising Si_1_-_xGe_x on a Si single crystal substrate, a Ge thin film on the Si_1_-_xGe_x thin film, and a GaAS thin film on the Ge thin film. （２）前記Ｓｉ＿１＿−＿ｘＧｅ＿ｘ薄膜の組成比ｘを
、膜厚方向に対して、ｘ＝０からｘ＝１まで連続的かつ
単調に変化させたことを特徴とする特許請求の範囲第１
項記載の半導体基板。(2) The composition ratio x of the Si_1_-_xGe_x thin film is continuously and monotonically changed from x=0 to x=1 in the film thickness direction.
Semiconductor substrate described in Section 1.
JP26336484A 1984-12-13 1984-12-13 Semiconductor substrate Pending JPS61141116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26336484A JPS61141116A (en) 1984-12-13 1984-12-13 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26336484A JPS61141116A (en) 1984-12-13 1984-12-13 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS61141116A true JPS61141116A (en) 1986-06-28

Family

ID=17388457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26336484A Pending JPS61141116A (en) 1984-12-13 1984-12-13 Semiconductor substrate

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JP (1) JPS61141116A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334994A (en) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp Photoelectric integrated circuit device and manufacture thereof
KR100516339B1 (en) * 2001-12-11 2005-09-22 샤프 가부시키가이샤 Semiconductor device and production process thereof
JP2010225981A (en) * 2009-03-25 2010-10-07 Fujitsu Ltd Optical semiconductor device, integrated element and method of manufacturing optical semiconductor device
JP2011014896A (en) * 2009-06-05 2011-01-20 Sumitomo Chemical Co Ltd Optical device, semiconductor substrate, optical device producing method, and semiconductor substrate producing method
JP2011114160A (en) * 2009-11-26 2011-06-09 Sumitomo Chemical Co Ltd Semiconductor substrate, electronic device and method of manufacturing the semiconductor substrate
US8686472B2 (en) 2008-10-02 2014-04-01 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate
JP2014197669A (en) * 2013-03-08 2014-10-16 キヤノン株式会社 Photoconductive element, method for manufacturing photoconductive element, and terahertz time domain spectral device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334994A (en) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp Photoelectric integrated circuit device and manufacture thereof
KR100516339B1 (en) * 2001-12-11 2005-09-22 샤프 가부시키가이샤 Semiconductor device and production process thereof
US8686472B2 (en) 2008-10-02 2014-04-01 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate
JP2010225981A (en) * 2009-03-25 2010-10-07 Fujitsu Ltd Optical semiconductor device, integrated element and method of manufacturing optical semiconductor device
JP2011014896A (en) * 2009-06-05 2011-01-20 Sumitomo Chemical Co Ltd Optical device, semiconductor substrate, optical device producing method, and semiconductor substrate producing method
JP2011114160A (en) * 2009-11-26 2011-06-09 Sumitomo Chemical Co Ltd Semiconductor substrate, electronic device and method of manufacturing the semiconductor substrate
JP2014197669A (en) * 2013-03-08 2014-10-16 キヤノン株式会社 Photoconductive element, method for manufacturing photoconductive element, and terahertz time domain spectral device

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