JPS61136618U - - Google Patents
Info
- Publication number
- JPS61136618U JPS61136618U JP1865285U JP1865285U JPS61136618U JP S61136618 U JPS61136618 U JP S61136618U JP 1865285 U JP1865285 U JP 1865285U JP 1865285 U JP1865285 U JP 1865285U JP S61136618 U JPS61136618 U JP S61136618U
- Authority
- JP
- Japan
- Prior art keywords
- gates
- elements
- circuit
- former
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は本考案の回路、第２図は差動増幅器、
第３図は不平衡出力とした差動増幅器、第４図は
共通ソース抵抗を零とした増幅器、第５図イは共
通ソースを定電流化した差動回路、同図ロはＦＥ
Ｔの特性、第６図イは本考案の直線性の説明のた
めの図、同図ロはその特性、第７図と第８図は本
考案の実施例である。
Figure 1 shows the circuit of the present invention, Figure 2 shows the differential amplifier,
Figure 3 shows a differential amplifier with unbalanced output, Figure 4 shows an amplifier with zero common source resistance, Figure 5 A shows a differential circuit with a constant current common source, and Figure 5 B shows an FE.
The characteristics of T, FIG. 6A is a diagram for explaining the linearity of the present invention, FIG. 6B is the characteristic, and FIGS. 7 and 8 are examples of the present invention.
補正 昭６１．５．８
考案の名称を次のように補正する。
考案の名称 ＦＥＴ増幅回路
実用新案登録請求の範囲、図面の簡単な説明を
次のように補正する。Amendment May 8, 1981 The name of the invention is amended as follows. Title of invention FET amplifier circuit The scope of the utility model registration claims and the brief description of the drawings are amended as follows.
【実用新案登録請求の範囲】
Ｎチヤンネル複合型ＦＥＴとＰチヤンネル複合
型ＦＥＴとの、それぞれの第１素子のソース同士
、同じく第２素子のソース同士、前者の第１素子
と後者の第２素子とのゲート同士、及び前者の第
２素子と後者の第１素子とのゲート同士を、それ
ぞれ接続し、これらの２つのゲート接続部に入力
電圧を印加し、互いにゲート同士が接続されてい
る素子の２つのドレインの１組または２組から出
力電流差または出力電圧差を取りだすようにして
なるＦＥＴ増幅回路。 [Claims for Utility Model Registration] The sources of the first elements of the N-channel composite FET and the P-channel composite FET, the sources of the second elements, the first element of the former and the second element of the latter and the gates of the second element of the former and the first element of the latter are respectively connected, and an input voltage is applied to these two gate connections, and the gates of the elements are connected to each other. An FET amplifier circuit configured to extract an output current difference or an output voltage difference from one or two sets of two drains.
【図面の簡単な説明】
第１図は本考案の基本構成を示す回路図、第２
図は同回路の特性を示すグラフ、第３図及び第４
図はそれぞれ本考案の１実施例を示す回路図、第
５図から第８図はそれぞれ従来技術による回路を
示す図である。[Brief explanation of the drawings] Figure 1 is a circuit diagram showing the basic configuration of the present invention, Figure 2 is a circuit diagram showing the basic configuration of the present invention.
The figures are graphs showing the characteristics of the same circuit, Figures 3 and 4.
Each figure is a circuit diagram showing one embodiment of the present invention, and FIGS. 5 to 8 are diagrams showing circuits according to the prior art, respectively.
Claims (1)
型ＦＥＴを用いて、両者の第１素子の夫々ソース
同士、両者の第２素子の夫々ソース同士、前者の
第１素子と後者の第２素子の夫々ゲート同士、前
者の第２素子と後者の第１素子の夫々ゲート同士
を各々接続することによつて構成した回路で、こ
れら２つのゲート接続点に入力電圧を加え、互い
にゲート同士が接続されている素子の２つのドレ
インの１組又は２組から出力電流差又は出力電圧
差を取り出すことによつて、優れた直線性、優れ
た温度特性及び入出力回路の平衡、不平衡の自由
度を有することを特徴とする増幅回路。 Using an N-channel composite FET and a P-channel composite FET, the respective sources of the first elements of both are connected to each other, the respective sources of the second elements of both are connected to each other, and the respective gates of the first element of the former and the second element of the latter are connected to each other. , a circuit configured by connecting the gates of the second element of the former and the first element of the latter, respectively, and by applying an input voltage to the connection point of these two gates, the gates of the elements are connected to each other. By extracting the output current difference or output voltage difference from one or two sets of two drains, it is possible to have excellent linearity, excellent temperature characteristics, and flexibility in balancing and unbalance of the input/output circuit. Characteristic amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985018652U JP2514066Y2 (en) | 1985-02-13 | 1985-02-13 | FET amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985018652U JP2514066Y2 (en) | 1985-02-13 | 1985-02-13 | FET amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61136618U true JPS61136618U (en) | 1986-08-25 |
| JP2514066Y2 JP2514066Y2 (en) | 1996-10-16 |
Family
ID=30507488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985018652U Expired - Lifetime JP2514066Y2 (en) | 1985-02-13 | 1985-02-13 | FET amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2514066Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122951A (en) * | 1978-03-17 | 1979-09-22 | Kenjirou Shionoya | Differential matrix |
| JPS57133707A (en) * | 1981-02-13 | 1982-08-18 | Sony Corp | Bias circuit for power amplifier |
-
1985
- 1985-02-13 JP JP1985018652U patent/JP2514066Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122951A (en) * | 1978-03-17 | 1979-09-22 | Kenjirou Shionoya | Differential matrix |
| JPS57133707A (en) * | 1981-02-13 | 1982-08-18 | Sony Corp | Bias circuit for power amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2514066Y2 (en) | 1996-10-16 |
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