JPS5926652Y2 - Dual tracking bias circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a dual tracking bias circuit particularly suitable for power amplifiers using power FETs.

2. Description of the Related Art Conventionally, a power amplifier configured as shown in FIG. 1 is known as a power amplifier using a power FET (high power field effect transistor).

That is, this is a drive transistor Q1 whose one side is connected to the signal input terminal IN and the other side is connected to the constant current source I5□.
゜Bias circuit D for the drive stage between both bases of Q2
B1 is provided, and a resistor REI,
Power FET via RE2) transistor Q3゜Q4
In order to bias the power, a single power stage bias circuit PB consisting of 11.RGG is provided.

In this case, each bias voltage VDB, VGG of the drive stage and the power stage 1 is VDB=I](RGG+RE1+RE2), assuming that the idle current is 1.

VGG=11・Rcc becomes.

And to change the bias voltage Vcc of the power stage 1, use the RG
If G is constant, it is necessary to change the idle current ■1 of the drive stage.

Also, for RGG, ■1 is normally small and a few mA, so in order to set Vcc to an appropriate value (usually about 20 to 30 V), several KQ
It is necessary to make a selection.

On the other hand, in reality, the power FET must be driven with as low an impedance as possible in consideration of its junction capacitance.

That is, when considering that distortion characteristics deteriorate in high frequencies, it is necessary to make the value of RGG as small as possible.

Therefore, the configuration of the bias circuit as shown in FIG. 1 cannot satisfy the two requirements mentioned above.

For this reason, the impedance of the second
As shown in the figure, bias circuit DB2. is equivalently represented by a battery. It is possible to use PB2.

However, in this case, the bias voltage of the drive stage ■8
If tracking is not taken between □ and the power stage bias voltage ■8□, the drive stage transistor Ql has a low impedance.

Q2 had the inconvenience of being destroyed by excessive current flowing through it.

Therefore, this invention was made in view of the above points, and the purpose is to provide an extremely good dual tracking bias circuit that can obtain a bias voltage with sufficient tracking.

An embodiment of this invention will be described in detail below with reference to the drawings.

That is, as shown in FIG. 3, transistors Q1. An appropriate number of diode series circuits D1. D2 and resistor R8□, RB.

A first bias circuit DB3 serving as a bias circuit for the drive stage is connected through the first bias circuit DB3.

This first bias circuit DB3 includes the resistors R, B1 . R
A transistor Q5 whose collector and emitter are connected correspondingly to one end of B2, a Zener diode ZD1 connected between the base and collector of this transistor Q5 with the polarity shown, and a resistor 1Ro1 connected between the base and emitter. Consists of.

Further, a second bias circuit PB3 serving as a power single-stage bias circuit, which will be described later, is connected between the emitters of the drive transistors Ql and Q2 via resistors REI and RE2.

This second bias circuit PB3 is connected to the resistors RE□, RE
A Zener diode ZD2 of the illustrated polarity, a variable resistor VR1, and a resistor R62 are connected in series to one end of each of the resistors 2 and 2,
A collector and an emitter are connected to one end of each of the resistors REI and RE2, and the variable resistor VR□
and a transistor Q6 whose base is connected to the sliding terminal of the transistor Q6.

Here, the collector and emitter of the second bias circuit PB3 are connected to the power F constituting one stage of complementary power.
ET) transistor Q3. A sash is connected to the gate of Q4.

Furthermore, the first and second bias circuits DB3. P.B.
A tracking circuit TC is interposed between the three.

This tracking circuit TC1 is connected to the first and second bias circuits DB3. First and second differential pair transistors Q7. with corresponding opposite ends of PB3 connected to respective input ends (bases). It consists of Q8 and Q9°QIO.

Here, each differential pair transistor Q7. Q8 and Q9. Q
The corresponding collectors of the IOs that are on the second bias circuit PB3 side are connected in common, and the corresponding collectors that are on the first bias circuit DB3 side are connected to the transistor Q.
The collector-emitter of IS2.5 is cross-connected to the collector-emitter of IS2. Connected to IS3.

Note that the drive stage transistor Q1. Each collector of Q2 is a positive power supply terminal■.

The other end of the constant current source IS2 is connected to the positive power source +VCCI, and the other ends of the constant current sources ■5□ and ■53 are connected to the negative power source −VCCI.
Connected to VCCI.

Also, the power single-stage transistor Q3. The drains of Q4 are respectively connected to the positive power supply +VcC2 and the negative power supply VCC2, and the sources are commonly connected to the load RL.

In the above configuration, first, the single-stage power transistor Q3. The second bias circuit PB depends on the variation in Q4.
In order to change the bias voltage Vcc of No. 3, that is, to raise or lower the setting value of JVGG by the amount of the change, the variable resistor R1 is adjusted.

For example, if this ■Go changes in a large direction, each differential pair transistor Q7 of the tracking circuit TC1. Among Q8 and Q9+Q10, the base-emitter voltages of transistors Q8+Q10 on the second bias circuit PB3 side become smaller, and the current 2 flowing through their common collectors decreases.

On the other hand, the current 1 due to constant current source ■8□ and IS3. , I'□
Since each differential pair transistor Q7 . in the tracking circuit TC1 has a constant current. Q8 and Q9 + Q 10
Of these, the transistor Q7 on the first bias circuit DB3 side
．． Each collector current of Q9■'2. ■″2 is 'Vcc = l I 2 RB□+l I '2R
B2, each differential pair transistor Q7
．． Q8 and Q9 + Q 10 balance.

This causes the first and second bias circuits DB3. P
The bias voltages V DB and V GG of B3 are now tracked.

Here I, = I',, R,, = RB□=Ra
and JI ``2'' J I ``2''' I ''
'2, A Vcc=2 I '2RB.

Furthermore, the current I4 flowing through the transistor Q5 in the first bias circuit DB3 is in the relationship JI4=■3-AI'2 when the constant current from the constant current source ISI is assumed to be ■3, and the current flowing through the input terminal IN is ■When it is 5, l3=I5, so in the end, ■'2. ■It is possible to drive the (input) signal with a constant current regardless of ``2''.

According to the dual low tracking bias circuit as described above, each bias circuit (especially the second bias circuit)
DB3. PH1 is the active transistor Q5. Q
Since the operating impedance is determined by step 6, the impedance can be made sufficiently low.

Also, the first and second bias circuits DB3. PB3 bias voltage ■D8. ■If G is kept the same, the bias of the drive stage will be V BE / RE C However, RE1 = RE
2=RE, VBE(Q1) -VBE(Q2)=VB
Since the bias voltage of the power stage 1 can be set regardless of the bias voltage of the drive stage, the circuit can be made resistant to the influence of FET variations in the power stage 1.

Note that in the above description, the transistor (power FET) is, for example, a vertical FET or MOSFET represented by current unsaturated characteristics (triode characteristics).

Therefore, as described in detail above, according to this invention, it is possible to provide an extremely good dual tracking bias circuit that can obtain a bias voltage with sufficient tracking.

[Brief explanation of the drawing]

Fig. 1 is a circuit wiring diagram showing a conventional power amplifier using power FETs, Fig. 2 is a circuit configuration diagram showing a basic example of this invention, and Fig. 3 is an example of a universal tracking bias circuit according to this invention. FIG. 2 is a circuit connection diagram showing a case where the present invention is applied to a power amplifier using a power FET. Ql, Q2...Drive stage transistor, Dl
. D2...Diode series circuit, RB work, RB□
...Resistance, DB3. PH1...bias circuit, TCl...tracking circuit, Q3.
Q4...Power single stage transistor, Q5~QIO
...Transistor, ■5□~Is3... Constant current source, RE engineering, RE2... Resistor.

Claims (1)

[Scope of utility model registration request] Between the first and second bias circuits provided in the base circuit and the emitter circuit of the drive transistor, two sets of differentials are established to balance the corresponding ends of the first and second bias circuits as respective differential inputs. A dual tracking bias circuit characterized by interposing a dynamic circuit.