JPS61136289A - Multilayer interconnection board - Google Patents
Multilayer interconnection boardInfo
- Publication number
- JPS61136289A JPS61136289A JP25853284A JP25853284A JPS61136289A JP S61136289 A JPS61136289 A JP S61136289A JP 25853284 A JP25853284 A JP 25853284A JP 25853284 A JP25853284 A JP 25853284A JP S61136289 A JPS61136289 A JP S61136289A
- Authority
- JP
- Japan
- Prior art keywords
- board
- layer
- copper foil
- multilayer wiring
- inner layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線基板の構造に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a multilayer wiring board.
従来、１に号ｊ輌寺のプリ７トを配された基板ｔ、多数
積層する場せ、第３図の如く最上面及び破下面以外の内
層基板３（信号層３＆をＭする）は、その積層前の時点
で、信号層３ａの版数を基板３の片面に表示Ａ（１２３
４−３）の如くエツチング形成していた。Conventionally, in the case of laminating a large number of substrates t on which a printed circuit board No. 1 is arranged, as shown in FIG. Before the lamination, the version number of the signal layer 3a is displayed on one side of the substrate 3 A (123
It was formed by etching as shown in 4-3).
しかし、上記表示Ａは基板３の積層前には確認できても
、積層後の確認は不可能となり、版数の相違による回路
の不都合が発生してもこｔ′Ｌを発見するまでに多大の
工数及び期間をａｔするという問題点がめった。However, even if the above display A can be confirmed before the board 3 is laminated, it is impossible to confirm it after the board 3 is laminated, and even if a circuit inconvenience occurs due to a difference in version number, it will take a lot of time before the problem is discovered. The problem of determining the number of man-hours and the period was frequently encountered.
〔問題点の７％火手段〕
本発明は上記問題Ａを解決したものであり、大々信号層
又は電源・グランド層を有する複数の配線基板を積層し
てなる多層配線基板において、内層となる基板のエッジ
部に、前記信号層又は電源・グランド層の版数と対応す
る個数の銅箔・臂ノドを設け、前記積層時にその端面よ
ジ該銅箔ノ譬ソド全確認できるようＫしたものである。[7% of the problems] The present invention solves the above problem A, and in a multilayer wiring board formed by laminating a plurality of wiring boards each having a signal layer or a power supply/ground layer, the inner layer A number of copper foil/arm edges corresponding to the number of versions of the signal layer or power supply/ground layer are provided on the edge of the board, and the edges of the copper foil can be fully confirmed during lamination. It is.
次に、その実施例を第１図、第２図と共に説明する。 Next, an example thereof will be explained with reference to FIGS. 1 and 2.
第１図及び第２図は夫々本発明に係る多層配線基板の積
層状感の斜視図、及びその内層基板の斜視図であり、各
図中、第３図と同一部分には同一符号を付す。1 and 2 are a perspective view of a laminated structure of a multilayer wiring board according to the present invention, and a perspective view of an inner layer board thereof, respectively. In each figure, the same parts as in FIG. 3 are denoted by the same reference numerals. .
同図中、多層配線基板は、四枚の基板１〜４を積層した
ものであり、基板１．４は外層基板、基板２．３は内層
基板である。In the figure, the multilayer wiring board is a stack of four boards 1 to 4, with board 1.4 being an outer layer board and board 2.3 being an inner layer board.
ここで、内層基板３は、従来と同体に版数の表示Ａ （
１２３４−３） を肩するが、それ以外に版数と対応し
た個数の銅箔パッド３ｂが、基板３のエッジ部に配され
ている。内層基板２についても同様である。Here, the inner layer substrate 3 displays the version number A (
1234-3), and a number of copper foil pads 3b corresponding to the number of plates are arranged on the edge portion of the substrate 3. The same applies to the inner layer substrate 2.
従って、本発明を用いれば、基板１，２，３゜４の積層
彼でも、Ｍ１図の如くその端面に見える銅箔パッド２ｂ
、３ｂの数を貌祭するだけで、容易に版数の相違が確
認でき、早期不良の発見が期待出来る。又、以上説明で
は内層信号ノー３＆について述べたが、共通層となる′
遁源・グランド１−等についても同様に逼用出釆るもの
である。Therefore, if the present invention is used, even if the substrates 1, 2, 3゜4 are laminated, the copper foil pad 2b visible on the end surface as shown in Fig.
, 3b numbers, you can easily confirm the difference in version number, and you can expect early detection of defects. Also, in the above explanation, the inner layer signal No. 3 & was described, but the common layer signal '
The same applies to Togen, Ground 1, etc.
〔幼 米」
以上説明した如く、本発明に、内層基板の基板エッジ部
に版数と対応する個数の銅箔・ギノド金設けて、基板積
層時にその端面より確認できるようにしているため、版
数の相違による回路の不都合が発生した隙、ｌＪｉちに
谷基板の版数を４４でき、手直しの１故及びＪｌ＆１３
閣を低紙できるという利点がある。[Young rice] As explained above, according to the present invention, copper foil and silver foil are provided in the edge portion of the inner layer board in a number corresponding to the number of plates so that it can be confirmed from the edge surface when laminating the boards. When there was an inconvenience in the circuit due to the difference in the number, the version number of the valley board was changed to 44, and due to rework, Jl & 13
It has the advantage that the cabinet can be made of low paper.
第１図及び８ｇ２図は夫々本発明に係る多層配線基板の
積層状態の斜視図、及びその内）一基板の斜視図、纂３
図は従来の多層配線基板のうち内層基板の斜視図である
。
１．４・・・外層基板、 ２，３・・・内層基板、３
ａ・・・信号層、 ３ｂ・・・銅箔ノット、Ａ
・・表示。Figures 1 and 8g2 are perspective views of the laminated state of the multilayer wiring board according to the present invention, and a perspective view of one of the boards, Volume 3.
The figure is a perspective view of an inner layer board of a conventional multilayer wiring board. 1.4...Outer layer substrate, 2,3...Inner layer substrate, 3
a...Signal layer, 3b...Copper foil knot, A
··display.
Claims (1)
板を積層してなる多層配線基板において、内層となる基
板のエッジ部に、前記信号層又は電源・グランド層の版
数と対応する個数の銅箔パッドを設け、前記積層時にそ
の端面より該銅箔パッドを確認できるようにしたことを
特徴とする多層配線基板。In a multilayer wiring board formed by laminating a plurality of wiring boards each having a signal layer or a power supply/ground layer, a number of copper pieces corresponding to the version number of the signal layer or power supply/ground layer is placed on the edge of the inner layer of the board. 1. A multilayer wiring board, characterized in that a copper foil pad is provided, and the copper foil pad can be confirmed from the end surface during the lamination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25853284A JPS61136289A (en) | 1984-12-07 | 1984-12-07 | Multilayer interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25853284A JPS61136289A (en) | 1984-12-07 | 1984-12-07 | Multilayer interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61136289A true JPS61136289A (en) | 1986-06-24 |
Family
ID=17321523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25853284A Pending JPS61136289A (en) | 1984-12-07 | 1984-12-07 | Multilayer interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61136289A (en) |
-
1984
- 1984-12-07 JP JP25853284A patent/JPS61136289A/en active Pending
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