JPS61136150A - Memory circuit - Google Patents

Abstract

PURPOSE:To set the initial value without wasting the capacity of an ROM by designating previously the initial value to each memory. CONSTITUTION:The 2nd gate means is used to set the initial value is set previously to each memory cell by closing a switch 5 or 6. When the initial value is set at a high level, the switches 5 and 6 are opened and closed respectively and vice versa when the initial value is set at a low level. When a control signal line 4 is set at a high level after the initial value of each memory cell is designated previously. Thus transfer gates 11 and 12 contained in the 2nd gate means II conduct. Then the initial value set previously is written to a memory part I.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to means for setting the initial state of the RAM in an integrated circuit having an FtAM in the same chip, such as a microcomputer integrated on one chip.

The initial state of each memory cell of a RAM built in a conventional integrated circuit is undefined when the power is turned on, and the initial value of each memory cell must be set as necessary.

Conventionally, in the case of a microcomputer integrated on a single chip, a built-in RO is used to set the initial state.
Initial values are set by storing the values in the ROM in advance, and after power is turned on, the values written in the ROM are sequentially read out by executing a program and written to memory cells at predetermined addresses in the RAM.

FIG. 4 shows an example of a conventional RAM memory cell.

Conventionally, a 1-bit memory cell is composed of a memory at consisting of two inverters and a first gate means for writing and reading consisting of two transfer gates. When writing data, external data is input to data signal line 1, and an inverted signal of the external data is input to data signal line 2. At this time, when the address signal line 3 of the specified memory cell is set to high level, , a transfer gate 9 of the first gate means,
10 becomes conductive, and external data input to data signal line 1 and data signal line 2 is written into storage unit 1.

Problems to be Solved by the Invention In integrated circuits such as microcomputers integrated on one chip, there is a limit to the capacity of the ROM that can be built into the same chip. In the past, great efforts have been made to compress programs. In the conventional example as mentioned above, the limited R
Wastes OM capacity. Furthermore, if there are many memory cells that require setting of initial values, it takes time to set the initial values of each memory cell.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide an integrated circuit having a function of easily setting the initial value of a memory cell.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a means for writing data into the RAM using a conventional first gate that writes data from outside the RAM into a memory cell at a specified nk address. In addition to the means, the second gate means includes a switch means for specifying an initial value to a high level or a low level for each memory cell in the RAM, and a second gate means for writing the specified initial value to the memory cell. The gate means is used to set the initial value of each memory cell.

Effect of the Invention With the above-described configuration, the present invention specifies an initial value for each memory cell within the RAM, so there is no need to store the initial value in the ROM, and the initial value of the RAM can be set without wasting the limited ROM capacity. can be done.

However, since the initial value specified for each memory cell is simultaneously written to each memory cell using the second gate means, the initial value can be set in a short time regardless of the number of memory cells that require initial value setting. I can do it.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the present invention. In FIG. 1, reference numeral 1 indicates a storage section, 2 indicates a first gate means for writing and reading, and 2 indicates a second gate means for writing.

The 1-bit memory cell of the RAM according to the present invention has a conventional arrangement consisting of two inverter gates, and a write-in memory cell consisting of two transformer gates and two switches. It has second gate means.

When writing data external to the memory section I VcRAM, the first gate means is used as in the conventional case.

That is, external data is input to the data signal line 1, and an inverted signal of the external data is input to the data signal line 2.

At this time, when the address signal line of the designated memory cell is set to a high level, the transformer 7 gates 9 and 1o of the first gate means become conductive, and the external data input to the data signal line 1 and the data signal line 2 becomes conductive. However, when setting an initial value to the storage section I written in the storage ml, the second gate means is used. In this case, specify the desired initial value for each memory cell in advance by closing either the switch 6 or the switch 6. When specifying the initial value as a high level, close the switch 6. , leave switch 5 open. Conversely, if you want to specify low level, press switch 6.
, and leave switch 6 open. FIG. 2 shows a case where the initial value is designated as high level.

As mentioned above, when the control signal line 4 is set to high level with the initial value of each memory cell specified in advance, the transfer gates 11 and 12 in the second gate means become conductive, and the initial value specified in advance is set. It is written to the storage section I.

In other words, when switch 5 is closed and a low level is specified, it is equivalent to inputting a low level from data signal line 1, and when switch 6 is closed and a low level is specified, a low level is input from data signal line 2. This is equivalent to inputting the signal, and as a result, a low level and a high level are respectively written to the storage section l.

FIG. 3 shows another embodiment of the invention.

This embodiment differs from the embodiment shown in FIG. 1 described above only in the method of specifying the initial value, and is otherwise the same.

That is, when specifying the initial value as . . . level, switch 7 is closed and switch 8 is opened.

Conversely, if you want to specify a low level, close switch 8,
Leave switch 7 open. In this case, when the control signal line 4 is set to high level and the transfer gate (11.12) in the second gate means becomes conductive, the switch 7 is closed and the data signal line is set to high level. This is equivalent to inputting a high level from the data signal line 2, and when the switch 8 is closed and a low level is specified, it is equivalent to inputting a high level from the data signal line 2. As a result, a high level and a high level are input to the memory section I, respectively. Each low level state is written.

Effects of the Invention As described above, according to the present invention, by specifying an initial value for each memory cell in advance, the initial value can be set without wasting ROM capacity.

Furthermore, since the initial values of each memory cell can be set simultaneously by simply inputting them to the control signal line, the initial values can be set in a short time regardless of the number of memory cells that need to be set.

[Brief explanation of the drawing]

FIG. 1 is a memory cell circuit diagram of a first embodiment of the present invention;
The figure is a circuit diagram of an embodiment of the present invention in which the initial value is specified as high level, Figure 3 is a memory cell circuit diagram of a second embodiment of the present invention, and Figure 4 is a memory cell circuit diagram of a conventional example. be. 1...Data signal line, 2...Data signal line, 3...Address signal line, 4...
Control signal line, 5, 6° 7.8...Switch, 9
,10,11.12・River...Transfer Gate. Name of agent: Patent attorney Toshio Nakao and one other person
f,, Dekui No. 8, 9, Fig. 3, Fig. 4

Claims (1)

[Claims] a first gate means for writing data from outside the RAM into a memory cell at a designated address; a switch means for specifying an initial value to a high level or a low level in advance for each memory cell inside the RAM; and the initial value. and a function of setting the initial state of each memory cell inside the RAM to a pre-specified high level or low level using the second gate means. A memory circuit comprising: