JPS58111170A - Chip selecting method - Google Patents

Abstract

PURPOSE:To practically increase the kinds of chips of an integrated circuit which can be simultaneously used and to increase the degree of freedom for chip selection, by incorporating a chip number changing circuit in each chip in the integrated circuit. CONSTITUTION:When a control signal CNT is turned to the high level and a switch SW is changed in the reverse direction, the uppermost bit of a chip selecting signal is inverted and the inverted signal is inputted to a decoder DEC, so that an output gate circuit is opened by a chip selecting signal of which chip number is different from the original one. Thus one chip can be activated under different chip numbers by turning the control signal CNT to the low or high level. It is also applicable to control plural bits, and in this case, the chip selecting number can be changed into many kinds of numbers.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a chip selection method, for example, when a plurality of R
The present invention relates to a chip select method for selecting an iLOM with a specified number (chi, f) from the OM (g-only memory).

(2) Technical background In general, one or more ROMs are connected to a common path using i! Continuing, each ROM
Input the chip select method along with the address signal in each ROM to the scissors! ROM specified by the 7th signal
The stored information is read from the chip vf.

For example, electronic translation machines, speech synthesis devices used in vending machines, etc. use a large number of ROMs that store various message information, and read out predetermined Metsuryu-Zo information from the designated nine-chig. Convert to audio signal.

(3) Prior Art and Problems In a conventional device, as shown in FIG. B-0, R-1, R-2, ..., R-F are commonly connected, and the chip 1 number information is sent from fa*tMPυ along with the address information in each read-only memory as a chip select method. It was sent to B. Then, in each read-only memory, if the scissor tag number information matches its own chip number, it reads the stored data at the address specified by the cough address information and sends it to the grosser via the data/dos DB. . In this way! The processor MPU is capable of reading the contents of a specified address from a desired chip.

Further, FIG. 2 shows the configuration of each read-only memory in FIG. 1. Figure 2: Glue/Do/Rememory is, for example, 16
It includes a bit counter UPC, a memory main body MH, an output ff-) circuit OG, and a decoding circuit DEC consisting of an inverter circuit INV and an AND r-) AND. The memory main body MW has a capacity of 4 bytes, and the internal address is specified by the lower 12 bits of the Azzo counter UPC. Also, ah! The top four pits of the counter UPC indicate the chip number, and one of the 16 chips
Specify the number. Further, although not shown in the figure, the uplink address UPC is connected to address passum B in FIG. 1, and data values from address passum B can be set.
This is done by sequentially counting up and f according to the clock signal CK from the set data value.

Therefore, by setting the reading start address of the main body of the main body from the MPU to a, fkakunta),
Data can be automatically extracted sequentially from the wrinkle start address.

Ah! The chip select method is set for the upper 4 pits of Kakunta UPC, and the signal system of these 4 pits, B, C
. for example,
If the chip number is "0", all the signals are 1. c,
D is input to ANDr-) via an inverter INV. Therefore, when all zeros are set in the top four pits of the Kawanta UPC, the outputs of the connected signals, B, C, and DK@ are all at a high level. Then, the output of ω becomes a high level trap and the output r
-) Circuit 0Gtf4 sends the readout output from the main body Mu to the data bus DB.

However, in the conventional type, the number of bits of the T/G select signal is limited to a maximum of 4 pits, for example, and the types of rounded read-only memories are limited to 16 bits.
However, there was an inconvenience in that it was impossible to fully meet the diverse needs of customers. For example, if chips with overlapping chip numbers are manufactured under the condition that they are not initially used at the same time, it is impossible to connect and use these chips with the same sensor later, and the As a result, the chip numbers overlapped, and it was necessary to change the chip and f numbers of one of the nine ROM chips and create a new chip with the same ROM data but a different chip number.

(4) Object of the Invention In view of the problems in the conventional example described above, an object of the present invention is to provide a chip select method in which nine chips are input into each integrated circuit chip by an external control signal. Based on the concept of providing a chip number changing circuit for changing number information, we have substantially increased the types of integrated circuits that can be used simultaneously, and
Chi, f (D
The purpose is to prevent unnecessary increases in types.

(5) Structure of the Invention According to the present invention, a chip select signal input is applied to its own integrated circuit chip, and when the chip select signal input corresponds to a chip number of 9, the integrated circuit chip is activated. In this method, a chip number changing circuit is provided which changes the chig select signal value inputted to the integrated circuit based on an external control signal, whereby when a predetermined thiazo select signal different from the own integrated circuit chip number is input, This is achieved by providing a chip select scheme characterized by activating the integrated circuit chip. □ (6) Examples of the invention The present invention will be explained in detail below using the drawings.

FIG. 3 shows a ROM chip as an example of an integrated circuit chip for implementing the method of the present invention. ROM in the same figure
The chip has a chip number changing circuit NO added to the ROM chip shown in Figure 2, and the other parts are the same as the ROM chip shown in Figure 2. It is connected to the most significant bit of the UPC and includes an input terminal INV' and a switch 8W. SW and TE 8W can be switched by a control signal CNT from an external force.

For example, the control signal CN
If T is at a low level and the switch SW is connected as shown, the circuit configuration in this case is exactly the same as the circuit in Figure 2, and therefore the operation is also exactly the same. be. In response, the control signal CNT is set to high level,
If this causes the own switch SW to be switched in the opposite direction, it will be a shame! Since the most significant bit of the select signal is inverted and input to the decoding circuit DEC, the output r-to circuit is opened by a chip select signal different from the original chip number. For example, if the chip number when the control signal CNT is at a low level, that is, the original chip number, is "0", the chip number is changed to "8" by setting the control signal CNT to a high level. Thus, one step can be activated at different Te, f numbers by bringing the control signal CNT to a low level, eg, OV, or to a high level, eg, a positive power supply voltage.

In the above, an example is shown in which only the top bits and toms of the chip select method are controlled, but it is also possible to control multiple bits and fs, in which case it is possible to control multiple bits and fs. can be changed to the type of Figure 4 shows the chip numbers when the chip select numbers are not changed for the values of the input catezo select signals (A, B, C, D).
(A) When only bits are controlled, each chi! The chip numbers that can be taken by , and the chip numbers that can be taken by each chi and f when both bits (mu) and (b) are controlled are shown. Fourth
According to the figure, if the initial chip number F11 is "0", the chip number that can be obtained by controlling the bit (mu) is "
0” and “8”, and bit (Mu) and (B
) can be controlled by rOJ, r4J, r
8J, 41[class of rcJ(-12).

FIG. 5 shows another embodiment of the chip number changing circuit that can be used in the ROMf, 7' of FIG.

In the circuit shown in the figure, two people or FD constitute the upper 4 bits of UPC. 70.
f%G1 and G2 are transistors xi, V, :/l' configured by connecting P-type and N-type MO8) Lanzostars in parallel.
-) circuit, INV 1 and INV 2 are inverters,
ANDU7:/Pr-). t'#: , Ml to M4 are connection parts, and each pin of the chip select signal (v) (AND r-) of the chip select signal is connected to the input line of Φ according to the chip number. It is actually made into a mask ROM, and the connection 2>1 is made during the step manufacturing process.

In the circuit shown in FIG. 5, when the control signal CNT is at a low level, r-)G2 is conductive, and conversely, when it is at a high level, f-
When the bit G1 becomes conductive, the polarity of the bit (A) of the chip select system is switched, and the chip number is changed.

(7) Effect of the invention According to the invention, the chip number gold prize of the same integrated circuit
! This increases the degree of freedom in chip selection and eliminates the need to manufacture integrated circuits that have the same content but differ only in chip number, thereby unnecessarily increasing the types of chips that are actually manufactured. Preventing this could substantially increase the variety of integrated circuit chips.

[Brief explanation of the drawing]

FIG. 1 is a schematic program circuit diagram showing an information processing device using a plurality of memory chips, f, and FIG. 3 is a circuit diagram showing the configuration of ROMf and 2 for carrying out the chip selection method according to an undiscovered embodiment, and FIG. 4 is a modification of the chip number. and FIG. 5 shows a chip number changing circuit used in the circuit of FIG. 3! It is a lock circuit diagram. MPU: Grossesa, R-Q, R-1,..., R-
F: memory chip, mB near address path, DB: data path, UPC near, f down kakunta, MH: main body, OG: output r-t-1 AND: and r-t, DE
C: r :I-〆, INV, INV', INV
1, INV 2: Inverter, 8W: Switch,
NC: Chiyf number fj! Picture path, Fmu, FIl, PC, F
D: Free, f70g, G1. G2: f-) circuit, Ml
, M2°M3. M4: Connection part. 4IIFF Applicant Fujitsu Co., Ltd. Patent Application Agent Patent Attorney Akira Yoiki Illustrations Kazuyuki Tate Patent Attorney Kyoo Uchida Patent Attorney Akira Yamaguchi Figure 4 Figure 5

Claims (1)

[Claims] In a chip select method that activates a wrinkled integrated circuit when a left signal input to the chip matches the chip number given to its own integrated circuit, the left signal is input to the integrated circuit based on an external control signal. Nine wrinkles
A chip number change circuit is provided to change the select signal value.
Accordingly, a chip select method is characterized in that when a predetermined chip select method different from the own integrated circuit chip number is input, the integrated circuit chip is brought into an active state.