JPS63266690A - Semiconductor memory device and memory device using it - Google Patents

Abstract

PURPOSE:To read-out it at high speed by providing a latch circuit having a function, which holds a storage information, read out from an information storage part, and transmits the held information to an external terminal, as being in an operating state independently of the information storage part, according to a control signal supplied from the external terminal. CONSTITUTION:A first address signal to be supplied at the time of a read-out operation, and the first address signal corresponding to a data held in the latch circuit FF are compared, and if they are the same addresses, a second address signal to designate respective semiconductor memory devices M0-M31 is decoded, and a read-out signal is transmitted after designating the latch circuit FF, stored in the semiconductor memory devices M0-M31. If they are the different addresses, storage parts RAM in all the semiconductor memory devices are accessed by the first address signal, and the read-out signal is transferred to the latch circuits FF respectively. Then, the second address signal is decoded, and the read-out signal is outputted from the latch circuit FF, stored in the semiconductor memory devices M0-M31, and at the same time, the first address signal at that time is fetched in an address storage circuit. Thus, an operating speed can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device and a memory device using the same, and provides a technology that is effective when used in a memory board configured on a mounting board such as a printed circuit board. It is related to.

[Conventional technology]

As a memory board serving as a main storage device in a microcomputer or the like, there is, for example, ■ Hitachi, Ltd. Showa 6 Note 2MB 0 2 User's Manual J.

[Problem that the invention seeks to solve]

Dynamic RAM, which has a large storage capacity, is used for memory boards used as main storage devices, etc., as shown in . Although such a memory board can have a large storage capacity, it has the disadvantage of slow operation speed because each semiconductor memory device is selected one by one in the readout operation of stored information.

An object of the present invention is to provide a semiconductor memory device that has a simple configuration and enables high-speed reading, and a memory device using the same.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it holds the stored information read out from the information storage section, and independently operates the information storage section in response to a control signal supplied from an external terminal, and causes the information storage section to send the held information to the external terminal. Provide a functional latch circuit. Further, address terminals and data line terminals of the plurality of semiconductor memory devices are connected in parallel to constitute a memory section, and an address corresponding to a first address signal commonly supplied to each of the semiconductor memory devices is provided. A control circuit including a storage circuit and an address comparison circuit is provided to compare a first address signal supplied during a read operation with a first address signal corresponding to data held in the latch circuit. If the address is the same, the second address signal specifying each semiconductor memory device is decoded and the latch circuit built in that semiconductor memory device is specified to send out a read signal, and if the address is different, the first address signal is used to read out the read signal. Accessing the storage section in the semiconductor memory device and transferring the read signal to each latch circuit, decoding the second address signal and outputting the read signal from the latch circuit built in the semiconductor memory device, The first address signal at that time is taken into the address storage circuit.

[For production]

According to the above-mentioned means, there is a high probability that a read signal can be sent from the above-mentioned latch circuit, which operates at a high speed, when reading from consecutive addresses or repeatedly reading within a certain address range, such as when executing a program. Therefore, it is possible to substantially improve the operating speed.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of a semiconductor memory device according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The information storage RAM is constituted by, for example, a static RAM (Random Access Memory) having a ×8 bit configuration. This static type RAM has a storage capacity of approximately 32 bytes. Therefore, the address terminal is made up of 16 bits including AO-A14 and the chip selection terminal MC3, which serves as a substantial address terminal. Further, the data terminals consist of MDO-MD7, and data is exchanged in units of 8 bits. This information storage unit RA
It is to be understood that M is a static type RAM itself whose basic configuration is x8 bit configuration.

In other words, the semiconductor memory device of this embodiment is basically a static type RAM with a known x8 focus configuration.
However, it should be understood that the following circuits are newly included.

In this embodiment, in order to speed up the read operation,
A latch circuit FF is provided. This latch circuit FF is
The information storage RAM consists of a through latch circuit.
The readout operation outputs and holds the readout signal sent from the data terminals MDO-MD7.Therefore, between the data terminals MDO-MD7 of the information storage RAM and the input terminal of the latch circuit FF, An internal bus consisting of 8 bits is provided. This latch circuit F
The output terminal Q of F is the data terminal Do- of the semiconductor memory device.
It is coupled to D7. This data terminal Do-07 is coupled to the input terminal of input buffer IB. The output terminal of this input buffer IB is coupled to the data terminals MDO to MD7 of the information storage RAM through the internal bus.

The latch circuit FF and input buffer IB are unit circuits consisting of eight pieces corresponding to the eight data terminals DO-D7 and MDO to MD7, in order to enable data transfer in units of 8 bits as described above. Consisted of.

The latch circuit FF is brought into operation independently of the information storage RAM in order to realize a high-speed read operation as described later. That is, the launch circuit FF is
An output enable signal OE from an external terminal is supplied to the output control I@child OC. As a result, the latch circuit FF independently enters an operating state in response to the output enable signal OE, and outputs the held information from the external terminal DO-07. Chip selection signal C8 supplied from external terminal
is supplied to the input control terminal G of the latch circuit FF via the inverter circuit N1. In addition, the inverter circuit N
The output signal of 1 is supplied to the information storage RAM, chip selection signal terminal MC3, and output enable signal terminal MOH via the inverter circuit N2.

In addition, a write enable signal W supplied from an external terminal
E is supplied to the enable terminal E of the input buffer IB and the write enable signal terminal MWE of the information storage RAM.

In the semiconductor memory device of this embodiment, when the chip selection signal C8 is set to a low level, the information storage section RAM becomes operational, and when the write enable signal WE is at a high level, the information is supplied from the address terminal AO-A14. A read operation of stored information corresponding to an address signal is performed. The read information is transferred to the latch circuit FF which is activated by the low level of the chip selection signal C8. At this time, if the output enable signal OE is set to low level, the read signal is sent out from the external terminals DO to D7 through the launch circuit FF. If the output enable signal OE is set to a high level, the output operation of the latch circuit FF is prohibited, so the read signal is kept held in the latch circuit FF. Such a read signal output function is useful in the following cases. For example, when reading out stored information at the same address again, the output enable signal is output without accessing the information storage RAM. Output data can be obtained immediately by simply setting OE to low level. In addition, when the microprocessor or the like that instructs the read operation is slow in reading the information storage RAM, the information storage RAM sends the data to the latch circuit by reading the data, regardless of the external control signal. It becomes unselected and enters low power consumption mode. The microprocessor or the like can obtain the data by generating the output enable signal OE at any necessary timing.

[Embodiment 2] FIG. 3 shows a block diagram of an embodiment of a memory device using the above semiconductor memory device. The storage device shown in the figure is configured on a mounting board such as a printed circuit board.

In this embodiment, although not particularly limited, 32 semiconductor memory devices are connected in parallel.

That is, the address terminals AO-A14 and data terminals DoND7 of the 32 semiconductor memory devices MO-M31 are connected to a common address bus and a common data bus. Address terminal AO of the semiconductor memory device M O-M 31
-A14 is supplied with address signals A5 to A19 supplied from the address bus.

The following memory control unit C0NT is provided for the storage unit (MO-M31) having the above configuration.

The following signals are supplied to the memory control unit C0NT. Signal AS is an address strobe signal and indicates the presence of a valid address signal on the address bus to which the storage device is coupled.

The signals UDS and LDS are the upper 8 bits D8 to D15 and the lower 8 bits (Do-D) of the 16-bit data.
This is a signal specifying 7, and is equivalent to the address signal AO because it is output from, for example, a 68000 series microprocessor and is formed from the address signal AO. These signals UDS and LDS are 8 bits (bytes) in a microprocessor with a 16-bit configuration as described above.
This is a control signal for realizing access in units.

Signal R/W is a control signal that specifies reading/writing to the storage device. Signal R3T is a reset signal. Signal CLK is a clock signal. Signal A1~
A4 is an address signal for the remaining lower bits. Further, upper address signals A5 to A19 are also supplied.

The control unit C0NT includes read control signals 5LRO to 31 and write control signals 5L as the various control signals described above.
WO~31 are formed, and each semiconductor memory device MO-
It is supplied to the output enable terminal OE and write enable terminal WE of M31.

Furthermore, the chip selection signal C3L is applied to each semiconductor memory device MO.
It is commonly supplied to the chip selection terminals CS of ~M31.

FIG. 2 shows a block diagram of an embodiment of the address comparison section included in the control section CONT.

Among address terminals A1 to A19 of the storage device, upper address signals A5 to A5 excluding address signals for specifying each semiconductor memory bag W (latch circuit FF) MO to M31
A19 is an address signal corresponding to the data stored in each of the latch circuits FF. Therefore, the address terminals A5 to A19 are coupled to the data terminals of the flip-flop circuit FFI. flip-flop circuit FF
1, the address strobe signal AS is supplied to the clock terminal. In addition, the clear terminal CLR receives a reset signal R3T and an inverted signal of the control signal R/W.
R) The output signal of gate circuit G1 is supplied. That is, the 79717071 circuit FFI is reset during the reset operation and when the write mode is designated.

The output signal of the flip-flop circuit FFI is supplied to one input terminal P of the comparator COMP. The other input terminal Q of the comparator COMP is supplied with the address signals A5 to A19. Note that in order to operate the comparator COMP substantially during the read operation, a control signal R/W is connected to one input terminal P side of the comparator COMP.
is supplied. Corresponding to this, the other input terminal Q side is constantly connected to the power supply voltage Vcc (high level) via a resistor.
is supplied. As a result, when a read mode in which the control signal R/W is set to high level is specified, a coincidence signal (P-Q) is output, and the operation of the comparator COMP is substantially enabled. Become something.

The coincidence output (PQ) outputs a low-level inverted signal LEQ when both signals match. This inverted signal LQ
E is outputted as a non-inverted signal LEQ via an inverter circuit N1. This signal LEQ (LEQ) is applied to the 32 memory devices provided in the 32 semiconductor memory devices MO-M31.
The signal is output as a signal indicating that data corresponding to the designated address exists in one of the launch circuits FF.

For example, when data at a specified address exists in the latch circuit FF, a signal DATCK is output in synchronization with the high level of the signal LEQ to instruct the microprocessor to end the read operation of the storage device. Furthermore, if the data at the specified address does not exist in the launch circuit FF, reading is performed from the information storage RAM, so the end of the above operation is micro-clocked according to a delay time formed by a counter circuit (not shown), etc. A signal DATCK for instructing the processor is output.

An outline of the read operation of the storage device having the above configuration will be described below.

A program for information processing, etc. is written into each semiconductor memory device MO to M31. During this write operation, no write is performed in the latch circuit FF due to the low level of the control signal R/W. That is,
Chip selection signal C3L formed by control unit C0NT
The information storage section R of all the semiconductor storage devices MO to M31 is
AM is activated, but the lower address signal Δ0
(UDS, LDS) In response to write control signals st, wo to 31 specified by A4, for example, only the input buffer IB of one semiconductor memory device MO becomes active, so 1 byte is supplied from the system bus. The data is written to the information storage RAM of the semiconductor memory device MO.

At this time, if the chip selection signal CSL is maintained at a low level and the lower address signals AO to A4 are switched, the write control signals 5LW1 to 31 are generated one after another, and the inputs of the semiconductor memory bags WM1 to M31 are generated. Buffers IB are sequentially activated. Therefore, the information storage section R
Data is written without changing the AM address. In other words, a maximum of 32 bytes of data can be written.
Information storage section RA in each semiconductor memory device MO-M31
Since the address selection operation for M can be performed essentially once, high-speed writing is also possible.

The semiconductor memory bag mentioned above? ! After a program is stored in MO-M31, when executing the program, for the sake of simplicity, it is assumed that reading after an instruction is performed sequentially from the first address of semiconductor memory devices MO to M31.

In such a first read, since no valid data is stored in the launch circuit FF, a read operation is performed from the information storage RAM of all semiconductor memory devices MO to M31. That is, the address signal of the lower 5 bits is transmitted to 32 semiconductor memory devices (launch circuit FF).
) is used to specify MO-M31, so 32
One byte of information is read in parallel from the information storage RAM of each semiconductor memory device, and is transferred to each latch circuit FF. Of the 32 semiconductor memory devices (launch circuit FF) MO to M31, address signals AO (UDS, LDS) and address signals A1 to
Read selection signal 5LRO~31 formed by A4
One of the selection signals 5LRO becomes low level, and the data of the latch circuit FF of the semiconductor storage bag WMO is outputted from the data terminal Do-D7 coupled to the system bus. In parallel with this, the address signals A5 to A19 resulting from the memory access are sent to the flip-flop circuit FF of FIG.
It is stored in I.

Therefore, when reading the next address, among the lower bit address signals AO to A4, only address No. 13 AO changes, so the remaining upper bit address signals A5 to A19 remain the same. . The comparator COMP detects this and generates the one-defeat signal LEQ. As a result, the read selection signal 5LRI is set to low level, and the latch circuit FF of the semiconductor memory device M1
The stored information held in is output. When reading 32 bytes in sequence by incrementing the address signal, the remaining 31 bytes of information are output from the latch circuits FF of each semiconductor memory bag y1MI to M31, except for the first 1 byte read operation. In this way, since the address selection operation of the memory circuit is not required every time each data is output, the read operation can be made faster.

Then, for example, when the 33rd byte of data is subsequently read out, the address signal A5 changes, so that the comparator COMP generates the mismatch signal LEQ.

As a result, the address of the information storage RAM of the all-semiconductor storage device MO-M31 is switched, and 1 byte of data is output in the same manner as the first reading described above.

In this embodiment, the information storage RAM is an EFROM (Erasable & Electrically Programmable Read Only Memory) mainly because it is possible to speed up the read operation as described above. In other words, since the above-mentioned EFROM has a relatively slow read operation and is usually used to store programs, there is a high probability that the read operation will be performed regularly in a certain order as described above. .

When applied to FROM in this way, it goes without saying that the manual buffer IB is omitted.

The effects obtained from the above examples are as follows. That is, (11) holds the stored information read out from the information storage section, becomes operational independently of the information storage section in response to a control signal supplied from the external terminal, and transfers the retained information to the external terminal; By providing a latch circuit that has the function of transmitting data, it is possible to output the same address again from the latch circuit, which enables high-speed reading and enables output operation at arbitrary timing. It will be done.

(2) A storage section is configured by providing a plurality of semiconductor memory devices having the above configuration and connecting their address terminals and data line terminals in parallel, and a first address commonly supplied to each of the semiconductor memory devices. A control circuit including an address storage circuit and an address comparison circuit corresponding to the signal is provided,
A first address signal supplied during a read operation is compared with a first address signal corresponding to the data held in the latch circuit, and if the addresses are the same, a second address is provided that specifies each semiconductor memory device. The signal is decoded and a latch circuit built in the semiconductor memory device is designated to send out a read signal, and if the address is different, the memory sections in all the semiconductor memory devices are accessed using the first address signal and the read signal is sent to each of the semiconductor memory devices. The second address signal is transferred to a latch circuit, the second address signal is decoded, a read signal is output from the latch circuit built in the semiconductor memory device, and the first address signal at that time is taken into the address storage circuit. do. As a result, when reading from consecutive addresses or repeatedly reading from a certain address range, such as when executing a program,
The probability of performing a read operation of outputting the stored information already held in the latch circuit without selecting the address of the memory array is increased, and the effect is that it is possible to substantially improve the memory read operation speed. .

(3) By configuring the information storage section with a programmable ROM, since the information processing program is mainly stored, there is a high probability that the readout will be performed in an orderly manner (as a result, a high speed The effect is that information processing becomes possible.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, instead of the 32 semiconductor memory devices described above as one unit, the memory device may be one that includes more semiconductor memory devices, such as 64 or 128, as one unit. In this case, it is possible to read a large amount of data of 64 bytes or 128 bytes at high speed to which consecutive addresses are assigned. In addition to the above-mentioned 8-bit configuration, one piece of data can have various embodiments such as 16-bit, 4-bit, or 1-bit. The information storage RAM of the semiconductor memory device may be composed of a dynamic RAM. In dynamic RAM, row-related address signals and column-related address signals are supplied chronologically from the same address terminal, so the timing signal (address strobe signal) and the It is sufficient to generate a corresponding address signal. In addition, the information storage RAM is MOS
The input buffer IB and the launch circuit FF may be constructed using bipolar transistors. In this way, M
By adopting the Bi-CMO3 technology of forming an OSFET and a bipolar transistor, the output operation of the latch circuit FF can be made faster.

A storage device using the above-mentioned semiconductor memory device can be constructed by configuring a plurality of the above-mentioned semiconductor memory devices as one unit on a mounting board such as a printed circuit board (memory board), and providing a plurality of memory boards. It may also be intended to increase storage capacity. In this case, the memory control section may be formed on one memory board or an independent printed circuit board.

The present invention can be widely used as a semiconductor memory device and a memory device using the same, such as a microcomputer system.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical ones are as follows. That is, it holds the stored information read out from the information storage section, and independently operates the information storage section in response to a control signal supplied from an external terminal, and causes the information storage section to send the held information to the external terminal. By providing a latch circuit with a function, the same address can be read out again from the latch circuit, thereby enabling high-speed reading and output operation at arbitrary timing. Further, by utilizing the output function of the semiconductor memory device, a plurality of semiconductor memory devices having the above configuration are provided, and their address terminals and data line terminals are connected in parallel to form a memory section, and each of the semiconductor memory devices A control circuit including an address storage circuit and an address comparison circuit corresponding to a first address signal commonly supplied to the latch circuit is provided, and the control circuit includes an address storage circuit and an address comparison circuit corresponding to a first address signal commonly supplied to the latch circuit. If the addresses are the same, the second address signal that specifies each semiconductor memory device is decoded, and the launch circuit built in that semiconductor memory device is specified to read out the read signal. If the address is different, the first address signal is used to access the memory sections in all the semiconductor memory devices, the read signals are transferred to respective latch circuits, and the second address signal is decoded and stored in the semiconductor memory device. A read signal is output from the latch circuit, and the first address signal at that time is taken into the address storage circuit. This allows the memory information already held in the latch circuit to be output without having to select the address of the memory array when reading from consecutive addresses or repeatedly reading within a certain address range, such as when executing a program. The probability that a read operation can be performed becomes higher, and it becomes possible to substantially improve the memory read operation speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing an embodiment of an address comparison circuit provided in a memory control section, and FIG. 1 is a block diagram showing an example of a storage device using a semiconductor storage device. FIG. RAM...information storage unit, FF...latch circuit, IB...
Input buffer, MO-M31...semiconductor storage device, C0
NT: memory control unit, FFI: flip-flop circuit, COMP: comparator, G1: gate circuit,
N1-N3... Inverter circuit patent attorney Uo Ogawa l゛Electric゛＼ Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. An information storage unit including memory cells arranged in a matrix and an address selection circuit, and an information storage unit that holds stored information read from the information storage unit and instructs output operations supplied from external terminals. 1. A semiconductor memory device comprising: a latch circuit having a function of independently activating the information storage section and transmitting held information to an external terminal in response to a control signal. 2. A write signal is supplied to the information storage section through an input buffer that is activated during a write operation in response to a control signal supplied from an external terminal. 2. The semiconductor memory device according to item 1. 3. An information storage section including memory cells arranged in a matrix and an address selection circuit, and storing stored information read from the information storage section, and storing information in the information storage section according to a control signal supplied from an external terminal. A plurality of semiconductor memory devices each include a latch circuit that independently enters an operating state and sends retained information to an external terminal.
It includes a storage section whose address terminals and data line terminals are connected in parallel, and an address storage circuit and an address comparison circuit corresponding to a first address signal commonly supplied to each of the semiconductor storage devices, and which performs a read operation. Compare the first address signal supplied at the time with the first address signal corresponding to the data held in the latch circuit, and if the address is the same, decode the second address signal specifying each semiconductor memory device. Then, the latch circuit built in the semiconductor memory device is specified to send out a read signal, and if the address is different, the information storage section in all the semiconductor memory devices is accessed by the first address signal, and the read signal is sent to each latch circuit. A function of decoding the second address signal and outputting a read signal from a latch circuit built in the semiconductor memory device, and also importing the first address signal at that time into the address storage circuit. What is claimed is: 1. A storage device comprising: a memory control unit having: 4. The storage device according to claim 3, wherein the information storage section of the semiconductor storage device is a program ROM.