JPS61133893A - Time apparatus - Google Patents

Time apparatus

Info

Publication number
JPS61133893A
JPS61133893A JP59255538A JP25553884A JPS61133893A JP S61133893 A JPS61133893 A JP S61133893A JP 59255538 A JP59255538 A JP 59255538A JP 25553884 A JP25553884 A JP 25553884A JP S61133893 A JPS61133893 A JP S61133893A
Authority
JP
Japan
Prior art keywords
time
clock
circuit
time information
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59255538A
Other languages
Japanese (ja)
Inventor
Toshio Furuta
利夫 古田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59255538A priority Critical patent/JPS61133893A/en
Publication of JPS61133893A publication Critical patent/JPS61133893A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04RRADIO-CONTROLLED TIME-PIECES
    • G04R20/00Setting the time according to the time information carried or implied by the radio signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To enable the selection of correct time and a desired time, by a method wherein a desired time setting circuit is provided to enable the setting of desired time in such a manner that the operation of a time errors detecting is invalidated to keep the time from automatic correction. CONSTITUTION:A basic clock 101, an advance correction clock 102 and a delay correction clock 103 are outputted from a clock generation circuit 1 and any of the clocks are selected with a time counting clock selection circuit 4 to be inputted into a time counting circuit 5. Normally, the output of a standard time generation circuit 2 is compared with the output of the time counting circuit 5 by a time errors detecting circuit 3 and an indication signal is applied to the selection circuit 4 to output correct time information 105. Moreover, when a desired time setting circuit 6 is provided to apply desired time information 110 to the time counting circuit 5, an operation invalidation signal 111 is provided to the time errors detecting circuit 3 simultaneously to output the desired time information without being subjected to automatic correction.

Description

【発明の詳細な説明】 〔厘業上の利用分野〕 本発明は正確な時刻情報と任意の時刻情報のいずれかを
発生し供給する時刻装置に関する〇〔従来の技術〕 この種の時刻装置の従来例を第2図に示す。図中ZF!
クコツク発生回路、2は標準時刻発生回路、3は時刻誤
差検出回路、4は計時ククック選択回路である。クロッ
ク発生回路Iは基本クロック(全損周波数QM)101
と基本タロツクの一定割合増(全部周波aQr)の進み
補正クロック1(12と基本りaツク101の一定割合
減(全損周波数Qs)の遅れ補正クロック103とを発
生している。
[Detailed description of the invention] [Field of industrial application] The present invention relates to a time device that generates and supplies either accurate time information or arbitrary time information. [Prior art] This type of time device A conventional example is shown in FIG. ZF in the diagram!
2 is a standard time generation circuit, 3 is a time error detection circuit, and 4 is a clock selection circuit. Clock generation circuit I is a basic clock (total loss frequency QM) 101
A lead correction clock 1 (12) with a fixed percentage increase (total frequency aQr) of the basic tarock and a delay correction clock 103 with a fixed percentage decrease (total loss frequency Qs) of the basic tarlock 101 are generated.

計時クロック選択回路4は前記のクロック発生回路1の
発生するクロックの一つを時刻誤差検出回路3からの遅
れ指示信号lo8又は、進み指示信号109により選ん
で計時クロック106として出力する。計時回路5は該
計時クロック106をカウントしてI/−1@、あらか
じめ時刻設定手段(図示していない)にょシ設定された
特定時刻にlると時刻情報105を発生する。この時刻
情報105が/ステムの時刻情報として利用される。時
刻情報105はまた時刻誤差検出回路3に入力され、時
刻発生回路2が放送局等からの標準時報を受信しで発生
した標準時刻情報104と比較さnる。
The timekeeping clock selection circuit 4 selects one of the clocks generated by the clock generation circuit 1 according to the delay instruction signal lo8 or the advance instruction signal 109 from the time error detection circuit 3 and outputs it as the timekeeping clock 106. The timekeeping circuit 5 counts the timekeeping clock 106 and generates time information 105 when it reaches a specific time set in advance by time setting means (not shown). This time information 105 is used as the time information of the /stem. The time information 105 is also input to the time error detection circuit 3, where it is compared with standard time information 104 generated by the time generation circuit 2 receiving a standard time signal from a broadcasting station or the like.

時刻誤差検出回路3は前記時刻情報105と標準時刻情
報104とを受け、時刻の進みまたは遅れを検出し、同
時に誤差時間αI(進み誤差時間)また汀α2(遅れ誤
差時間)を算定し、補正時間βIまたはβ2を次式によ
り針具する。
The time error detection circuit 3 receives the time information 105 and the standard time information 104, detects whether the time is ahead or behind, and simultaneously calculates and corrects the error time αI (leading error time) and the lag α2 (lag error time). The time βI or β2 is determined by the following formula.

進み誤差補正時間βl=αIXQM/(QM−Qs)遅
れ誤差補正時間β2=α2 XQM/ (QF  QM
 )例えば基本クロックと補正クロックとの割合が1、
0%差で誤差時間αが1秒の場合、補正時間は10秒と
なる。時刻誤差検出回路3は進み誤差の場合は遅れ指示
信号108を、遅れ誤差の場合は進み指示信号109を
補正時1…だけ出力する。
Leading error correction time βl = αIXQM/(QM-Qs) Lagging error correction time β2 = α2 XQM/ (QF QM
) For example, if the ratio between the basic clock and the correction clock is 1,
When the difference is 0% and the error time α is 1 second, the correction time is 10 seconds. The time error detection circuit 3 outputs a delay instruction signal 108 in the case of an advance error, and outputs an advance instruction signal 109 in the case of a delay error by 1 . . . during correction.

計時クロック選択回路4は、前記指示信号108゜10
9によってそれぞれ遅れ補正クロック103、進み補正
クロック102を選定し、計時クロック106として補
正時間だけ出力する。補正時間後は基本クロック101
を出力する。
The timekeeping clock selection circuit 4 receives the instruction signal 108°10.
A delay correction clock 103 and a lead correction clock 102 are respectively selected by 9 and outputted as a timekeeping clock 106 for only the correction time. Basic clock 101 after correction time
Output.

〔解決すべき問題点〕[Problems to be solved]

しかるに一定時刻になると起動させなけれはならない様
な新規開発のプログラムのデバッキングの為には、その
時刻を任意な時点で得る必要があるが、従来例の時刻装
置では情報処理ンステムに常時正確な時刻情報を供給し
ているため任意の時刻を得ることができないという欠点
がめった。
However, in order to debug a newly developed program that must be started at a certain time, it is necessary to obtain the time at an arbitrary point in time, but conventional time devices do not always provide accurate information to the information processing system. Since it supplies time information, it has the disadvantage that it is rarely possible to obtain an arbitrary time.

〔問題点の解決手段〕[Means for solving problems]

本発明は上述の欠点に着目してなされたもので、情報処
理ンヌテムがプログラムデバッキング等のために、任意
の時刻情報を必要とするときKは任意時刻情報か又情報
処理シヌテムがプログラムデバッキング等以外の通常運
用のとぎには、時刻情報の補正を一度に段階的に行なわ
ず時刻情報の連続性を保ちながら自動的に補正し標準時
報に高精度で同期した正確な時刻情報が供給できる時刻
装置を提供することにある。その次めに、本発明の時刻
装atは、基本クロックと進み補正タロツクと遅れ補正
クロックとを発生するクロック発生回路と、前記クロッ
クのいずれか全選択して計時クロックとして出力する計
時クロック選択回路と、計時クロックをカウントし時刻
情報を発生する計時回路と、標準時報より標準時刻情報
を発生する標準時刻発生回路と、前記時刻情報と標準時
刻情報とを比較し、進みまたは遅れ指示信号を発生する
時刻誤差検出回路と、任意時刻の設定後は、標準時刻情
報と前記任意時刻情報との比較による時刻誤差検出回路
の動作を無効とする任意時刻設定回路とを備え次構成と
している。
The present invention has been made by focusing on the above-mentioned drawbacks, and when the information processing system needs arbitrary time information for program debugging etc., K is arbitrary time information or the information processing system needs arbitrary time information for program debugging etc. During normal operation, the time information is not corrected step by step at once, but is automatically corrected while maintaining the continuity of the time information, providing accurate time information that is synchronized with the standard time signal with high precision. The purpose of this invention is to provide a time device. Next, the time device AT of the present invention includes a clock generation circuit that generates a basic clock, a lead correction tarlock, and a delay correction clock, and a clock clock selection circuit that selects all of the clocks and outputs it as a clock clock. , a timekeeping circuit that counts a timekeeping clock and generates time information, and a standard time generation circuit that generates standard time information from the standard time signal, compares the time information with the standard time information and generates an advance or delay instruction signal. The present invention includes a time error detection circuit for detecting an arbitrary time, and an arbitrary time setting circuit for disabling the operation of the time error detection circuit by comparing standard time information and the arbitrary time information after setting the arbitrary time.

〔実施例〕〔Example〕

第1図に本発明の一実施例を示す。なお第1図において
第2図の記号番号と同じ記号のブロック及び同じ信号の
信号鞠は[司−である。
FIG. 1 shows an embodiment of the present invention. In FIG. 1, the block with the same symbol number and the same signal as the symbol number in FIG. 2 is [-].

したがって第1図と第2歯で相違する部分の機能に限定
し、その動作を説明する。
Therefore, the operation will be explained by limiting to the functions of the parts that are different between the first tooth and the second tooth.

任意時刻設定回路61″を情報処理ンヌテムが一定時刻
になると起動させなければならない様なプログラムfe
新規に開発させるときその時刻を任意の時点で得るため
に使用される。
A program FE that requires the arbitrary time setting circuit 61'' to be activated when the information processing system reaches a certain time.
It is used to obtain the time at any point when developing a new one.

例えば任意時刻設定回路6に任意の時刻が設定されてい
ない通常の運用では常時計時回路5より正確な時刻情報
が情報処理ンヌテムに供給させている。その時の時刻を
13uooMoos  と仮定するO したがってI OHOOMOO3に起動させるプログラ
ムをデバッキングするKは翌日まで待つ必要があるがそ
の様なことは許されない。そこで現時刻が13 ROO
MOO8であっても任意時刻設定回路6に09H55M
OO8を設定し、任意時刻情報110を通して計時回路
5にその時刻をプリセツトすることにより計時回路5内
の時刻情報l′i13ROOMOO8から09H55M
OO8となる。
For example, in normal operation when no arbitrary time is set in the arbitrary time setting circuit 6, more accurate time information is supplied from the constant clock circuit 5 to the information processing system. Assume that the time at that time is 13uooMoos. Therefore, K who debugs the program started by IOHOOMOO3 must wait until the next day, but such a situation is not allowed. So the current time is 13 ROO
Even if it is MOO8, 09H55M is set in arbitrary time setting circuit 6.
By setting OO8 and presetting the time in the clock circuit 5 through the arbitrary time information 110, the time information l'i13ROOMOO8 in the clock circuit 5 is changed to 09H55M.
It becomes OO8.

計時回路5にグリセットされた任に時刻09H55HO
O8は計時クロック選択回路4から出力されている基本
クロックによる計時クロック106により計時され09
H55MOO8以後正確な任意時刻情報が情報処理ンス
テムに供給される。
The time is 09H55HO as reset in the clock circuit 5.
O8 is clocked by the clock 106 based on the basic clock output from the clock clock selection circuit 4.
After H55MOO8, accurate arbitrary time information is supplied to the information processing system.

5分軽過し、10HOOMOO8Kなると新規開発のプ
ログラムが起動され、正確な時刻に合せてデバッキング
ができる。
After 5 minutes have passed and the clock reaches 10HOOMOO8K, a newly developed program will be activated, allowing debugging to be performed at the correct time.

又任意時刻設定回路6に任意の時刻情報かセットされて
いる間は動作信号1】1が時刻誤差検出回路3九入力さ
れており標準時刻情報と任意時刻情報との比較による時
刻誤差検出回路3の動作を無効にしている。
Also, while arbitrary time information is set in the arbitrary time setting circuit 6, the operating signal 1]1 is input to the time error detection circuit 39, and the time error detection circuit 3 detects the time error by comparing the standard time information and the arbitrary time information. operation is disabled.

すなわち時刻発生回路2が放送局等からの標準時報を受
信して発生する標準時刻情報104が出力されても計時
回路5にプリセットされた任意時刻情報を優先させるた
めにそれらの誤差を検出し計時回路5内の時刻情報を自
動補正させない。
That is, even if the time generation circuit 2 receives a standard time signal from a broadcasting station or the like and outputs the standard time information 104, it detects these errors and performs timekeeping in order to give priority to the arbitrary time information preset in the timekeeping circuit 5. The time information in the circuit 5 is not automatically corrected.

次に倉規開発のプログラムのデバッキングが予定のスケ
ジュールで終了すると任意時刻設定回路6にセントされ
ていた任意の時刻情報をリセットし代りに標準時刻情報
をセットし、計時回路5にプリセットする。同時に動作
無効信号111もリセットする。
Next, when the debugging of the program developed by Kuranori is completed according to the scheduled schedule, the arbitrary time information stored in the arbitrary time setting circuit 6 is reset, standard time information is set instead, and the clock circuit 5 is preset. At the same time, the operation invalidation signal 111 is also reset.

〔発明の効果〕〔Effect of the invention〕

本発明は、上述の如き構成としたため、情報処理ノヌテ
ムが一定時刻で起動させなければならない様なプログラ
ムのデバッキング等のために任意の時刻情報を必要とす
るときには任意時刻情報が又プログラムのデバッキング
等以外の通常運用のときには時刻情報の補正を一度に段
階的に行わず、時刻情報の連続性を保ちながら自動的に
補正し標準時報に高精度で同期した正確な時刻情報が供
給できるので通常運用時には正確な時刻情報が又デバッ
キング等の時には任意の時刻情報が得られるので効果的
なデバッキングも可能で更に正確な時刻情報を必要とす
る情報処理7ヌテムの要望をみたすことができるという
効果がある。
Since the present invention has the above-described configuration, when arbitrary time information is required for debugging a program that requires the information processing unit to start at a fixed time, the arbitrary time information can also be used to debug a program. During normal operations other than backing, etc., time information is not corrected step by step at once, but is automatically corrected while maintaining time information continuity, providing accurate time information that is highly precisely synchronized with the standard time signal. Accurate time information can be obtained during normal operation, and arbitrary time information can be obtained during debugging, enabling effective debugging and meeting the needs of information processing 7 systems that require more accurate time information. There is an effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例に係る時刻装置を示す回路
図、 そして、第2図は、従来の時刻装置を示す回路図である
。 1・・・クロック発生回路 2・・・標準時刻発生回路 3・・・時刻誤差検出回路 4・・・計時クロック選択回路 5・・・計時回路    6・・・任意時刻設定回路1
01・・・基本クロック 102.1.03・・・進み補正、遅れ補正クロツク1
04・−・標準時刻情報 105・・・時刻情報106
・・・計時クロック 110・・・任意時刻情報@ 1
 囮 第 2 図
FIG. 1 is a circuit diagram showing a time device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional time device. 1...Clock generation circuit 2...Standard time generation circuit 3...Time error detection circuit 4...Timekeeping clock selection circuit 5...Timekeeping circuit 6...Arbitrary time setting circuit 1
01...Basic clock 102.1.03...Advance correction, delay correction clock 1
04...Standard time information 105...Time information 106
...Time clock 110...Arbitrary time information @ 1
Decoy number 2

Claims (1)

【特許請求の範囲】[Claims] 基本クロックと進み補正クロックと遅れ補正クロックと
を発生するクロック発生回路と、前記基本又は進み補正
クロックのいずれかを選択し計時クロックとして出力す
る計時クロック選択回路と、計時クロックをカウントし
時刻情報を発生する計時回路と、標準時報より標準時刻
情報を発生する標準時刻発生回路と、前記時刻情報と標
準時刻情報とを比較し進みまたは遅れ指示信号を発生す
る時刻誤差検出回路と、任意時刻の設定後は標準時刻情
報と前記任意時刻情報との比較による時刻誤差検出回路
を動作無効にする任意時刻設定回路とからなる時刻装置
A clock generation circuit that generates a basic clock, a lead correction clock, and a delay correction clock; a timekeeping clock selection circuit that selects either the basic clock or the lead correction clock and outputs it as a timekeeping clock; and a timekeeping clock selection circuit that counts the timekeeping clock and generates time information. a standard time generation circuit that generates standard time information from a standard time signal; a time error detection circuit that compares the time information with the standard time information and generates an advance or lag instruction signal; and an arbitrary time setting. The rest of the time device includes an arbitrary time setting circuit that disables a time error detection circuit based on a comparison between standard time information and the arbitrary time information.
JP59255538A 1984-12-03 1984-12-03 Time apparatus Pending JPS61133893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59255538A JPS61133893A (en) 1984-12-03 1984-12-03 Time apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59255538A JPS61133893A (en) 1984-12-03 1984-12-03 Time apparatus

Publications (1)

Publication Number Publication Date
JPS61133893A true JPS61133893A (en) 1986-06-21

Family

ID=17280118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59255538A Pending JPS61133893A (en) 1984-12-03 1984-12-03 Time apparatus

Country Status (1)

Country Link
JP (1) JPS61133893A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192115A (en) * 1987-02-04 1988-08-09 Nec Corp Time synchronizing device
JPH0239219A (en) * 1988-07-28 1990-02-08 Nec Corp Time mechanism

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192115A (en) * 1987-02-04 1988-08-09 Nec Corp Time synchronizing device
JPH0239219A (en) * 1988-07-28 1990-02-08 Nec Corp Time mechanism

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