JPS59174783A - Time apparatus - Google Patents

Abstract

PURPOSE:To achieve a highly accurate synchronization with the standard time signal through an automatic correction maintaining the continuity of time information by including a plurality of timepiece circuits which inputs a distributed time counting clocks to generate time information except for one circuit thereof which generates time signal pulse separately. CONSTITUTION:A time counting clock selection circuit 4 selects one of clocks generated from a clock generation circuit 1 by indication signals 108 and 109 from a time errors detection circuit 3 and outputs it as time counting clock 106. The time counting clock 106 is distributed to a plurality of time counting circuits 6-1-6-n corresponding to devices in a system via a time counting clock distribution circuit 5. The time counting circuit 6-1-6-n count the time counting clocks 107-1-107-n distributed thereto and send time information to corresponding devices when reaching a specified time preset by a time setting means (not illustrated). One time counting circuit also generates a time signal pulse 105. The time signal pulse 105 is inputted into a time error detection circuit 3 and compared with a regular time signal pulse 104 generated from a regular time signal generation circuit 2 after the standard time signal is received.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time device that generates and supplies accurate time information. Large-scale information processing/systems often have a clock circuit for each device that makes up the system. In this case, if the time information of each clock circuit is not synchronized, the times will not match between the devices and the 7 stems will malfunction. Therefore, it is necessary to set up a time device that constantly generates and supplies time information that is synchronized with the reference standard time, and supplies it to each device.Conventional technologyIn the past, there was no such device, and in many cases, operators were responsible for detecting errors from the standard time. is corrected at regular intervals. Further, in this correction operation, time is measured at the time of correction, and the error between the time and the previous measurement is corrected at once. Therefore,
Corrections when the time is ahead of the standard time may cause the same time information to appear twice, while corrections when the time is behind the standard time have the disadvantage that the time information may become discontinuous, causing malfunctions in the system.

Purpose of the Invention The purpose of the present invention is to provide a system for large-scale information processing,
To provide a time device that eliminates the above-mentioned drawbacks, automatically corrects time information while maintaining continuity of time information, and synchronizes with a standard time signal with high precision, without correcting time information step by step at once. be.

Structure of the Invention A time device according to the present invention includes: a clock generation circuit that generates a basic clock, a lead correction clock, and a delay correction clock; a timing clock selection circuit that selects one of the clocks and outputs it as a timing clock; A timing clock distribution circuit that distributes a clock to each device of the system, and a plurality of circuits that input the distributed clock clock and generate time information, and at least one of the circuits separately generates a time signal pulse. A timekeeping circuit, an on-the-hour signal generating circuit that generates an on-time signal pulse from a standard time signal, and a time signal generation circuit that compares the time signal pulse generated by one circuit of the time-keeping circuit with the on-the-hour signal pulse, and generates a lead or lag instruction signal. In addition to the time error detection circuit, the timekeeping clock selection circuit selects the corrected clock for a predetermined period of time and selects the basic clock for the rest of the time in response to the lead or lag instruction signal.

Embodiment FIG. 1 shows an embodiment of the present invention. Clock generation circuit 1
are basic clocks (oscillation frequencies e, Qu)], o] and a certain percentage increase in the basic clock (oscillation frequency QF).
s) and the delay correction clock 103 is generated. The time clock selection circuit 4 selects one of the clocks generated by the clock generation circuit 1 according to the instruction signal 108, 109 from the time error detection circuit 3, and outputs it as the time clock 106. The clock clock 106 is distributed to a plurality of clock circuits 6-1 to 6-n corresponding to each device in the system via the clock clock distribution circuit 5. Timing circuit 6-1~
5-n are distributed time clocks 107-1 to 107-
n is counted, and when a specific time set in advance by a time setting means (not shown) is reached, time information is sent to each corresponding device. 1 clock circuit (6-1 in the figure) further generates a time signal pulse 105. This time signal pulse 105 is input to the time error detection circuit 3, and is compared with the hour signal pulse 104 generated when the hour signal generating circuit 2 receives a standard time signal from a broadcasting station or the like.

The time error detection circuit 4 receives the time signal pulse 105 and the hour signal pulse 104, detects whether the time is ahead or behind,
At the same time, the error time α is calculated, and the correction times βl and βl are calculated using the following formula.

Leading error correction time β1 = α・QM/(QM−Qs) Delay error correction time β2−α・QM/(QF QM) For example, if the ratio between the basic clock and the correction clock is 10 inches apart and the error time α is 1 second. In this case, the correction time is 10 seconds. The time error detection circuit 3 outputs a delay instruction signal 108 in the case of a lead error.
If there is a delay error, advance instruction signal 1'09 is output for the correction time. The timekeeping clock selection circuit 4 selects the delay correction clock 10 according to the instruction signals 108 and 109, respectively.
3. The advance correction clock 102 is selected and the timing clock 10 is selected.
6, only the correction time is output. After the correction time, the basic clock 101 is output. FIG. 2 shows a time chart of each signal line when a delay error is detected.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a clock that is increased or decreased by a certain percentage of the basic clock is selected as the time clock input to the time measurement circuit at each predetermined set time, and a clock that is increased or decreased by a certain percentage of the basic clock is selected as the time measurement clock that is input to the time measurement circuit at each predetermined set time. By changing to the basic clock afterwards,
The clock circuit can synchronize the generated time information with the standard time signal with high precision. Since the above-mentioned correction is carried out continuously and automatically, there is no inconvenience, such as in the conventional method, where the time information is output from the clock circuit twice or at intervals. The error is corrected by the clock circuit 6-
This is done by comparing the time signal pulses 105 generated by 1.
The corrected timekeeping clock 106 is also transmitted to the other timekeeping circuits 6-2 to 6-n via the timekeeping clock distribution circuit 5, so that these timekeeping circuits 6-2 to 6-n also generate synchronized time information. It turns out. Therefore, each device of the seven stems operates by obtaining time information synchronized with a highly accurate standard time signal, so that no malfunction occurs in the system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the time relationship of each signal line signal when a delay error is detected. 1... Clock generation circuit, 2... Hourly signal generation circuit, 3... Time error detection circuit, 4...
...Timekeeping clock selection circuit, 5...Timekeeping clock distribution circuit, 6-1 to 5-n...Timekeeping circuit, 101...Basic clock, 102/103・
...advance correction fate correction clock, 104...
... Hourly signal pulse, 106, 107-1 to 107-n
...Time clock, 108/109...
・Delay instruction/advance instruction signal. No./I￥] h Z diagram

Claims (1)

[Claims] In a system having a plurality of devices that require time information, a clock generation circuit that generates a basic clock, a lead correction clock, and a delay correction clock, and a timekeeping clock that selects one of the clocks and outputs it as a timekeeping clock. A selection circuit, a timing clock distribution circuit that distributes the timing clock to each device of the system, and a circuit that inputs the distributed timing clock and generates time information, and at least one of the circuits is separately provided. a plurality of timekeeping circuits that generate time signal pulses; an hourly signal generating circuit that generates hourly signal pulses from a standard time signal; and one of the timekeeping circuits.
a time error detection circuit that compares a time signal pulse generated by the circuit with the hourly signal pulse and generates a lead or lag instruction signal; A time device characterized in that it selects the corrected clock for a certain amount of time and selects a basic clock for the rest of the time.