JPS61133797A - Video signal correction circuit - Google Patents

Abstract

PURPOSE:To correct a false signal obtain a picture signal same in waveform as an original picture signal of record side, by replacing the false signal generated at a line sequential system with a right picture signal by 1H delay circuit. CONSTITUTION:A record reproduction device 15 supplies color difference signal R-Y from an output terminal 12 provided with a recording and a reproduction system of a color difference signal to 1H delay circuit 22, comparison circuit 23 and a terminal 24b of switch circuit 24, respectively. On the other hand, the color difference signal B-Y taken out from a terminal 13 is supplied to 1H delay circuit 27, comparison circuit 20 and a terminal 21b of a switch 21, respectively. The output signals (g), (h) of 1H delay circuits 27, 30 are as shown in the figure (J), (K), and signal (j) is outputted from the switch circuit 21 to output terminal 31 as shown in figure (M), and signal (i) is outputted from the switch 24 to output terminal 32 as shown in figure L. This signal (i) is the same color difference signal R-Y as shown in figure (A), and the signal (j) is the same color difference signal B-Y as shown in figure B.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal correction circuit, and in particular to a video signal correction circuit that corrects a pseudo video signal at a level different from the original video signal, which occurs when a line-sequential color difference signal is reproduced from a recording medium. The present invention relates to a correction circuit that corrects a signal (pseudo signal) by replacing it with a video signal of the correct level.

BACKGROUND TECHNOLOGY The transmission method, which is generally referred to as a line sequential method, has the property that the two color difference signals R-Y and B-Y have similar color information in adjacent horizontal synchronization periods (so-called line correlation). )use·! -Rukono: This allows two color difference signals of the same band to be transmitted in a narrow band through one transmission path. FIG. 4 shows a block system diagram of an example of this line sequential method. In the figure, for example, a color difference signal RY is input to an input terminal 1, and a color difference signal B-Y is input to an input terminal 2. Color difference signal R-Y
is supplied to the terminal 3a of the switch circuit 3, and the color difference signal B-Y is supplied to the terminal 3b of the switch circuit 3 after being added with a discrimination signal by the discrimination signal adder 4. The switch circuit 3 alternately connects the terminals 3a and 3a to each other every horizontal cycle period (1H).
Since the input color difference signals of 3b are switched and output, the color difference signals R-Y and B-Y are synthesized from the switch circuit 3 in a time-series manner alternately every 1H, and the color difference signals B-Y are transmitted every 2H. A line-sequential color difference signal to which a discrimination signal is added is extracted within the period.

This line sequential color difference signal is sent to the modulator 5. Recording medium 6° demodulator 7
The signal is supplied to the 1H delay circuit 8 and the discrimination signal detector 9 through transmission lines such as the like. Here, assuming that the color difference signals R-Y and B-Y entering the input terminals 1 and 2 have waveforms as schematically shown in FIG. 5 (A> and (B), respectively), the demodulator The reproduced line sequential color difference signal extracted from 7 is as schematically shown in FIG. 5(C).
In the figure, illustration of the discrimination signal is omitted. ). In addition, each numerical value at the top of the waveform shown in Fig. 5 (A) to (E), Fig. 2 (A) to (M), and Fig. 3 (A) to (Q) described later is the 1H.
Indicates the amplitude value of the signal for the period.

The reproduction line sequential color difference signal delayed by 1H by the 1H, +1 delay circuit 8 is supplied to the terminal 101) of the switch circuit 10 and the terminal 11a of the switch circuit 11, respectively.

In addition, the terminal 10a of the switch circuit 10, the switch circuit 11
The output reproduction line sequential color difference signals of the demodulator 7 are supplied to the terminals 11b of the demodulator 7, respectively. The switching circuits 1° and 11 are controlled in conjunction with each other depending on the presence or absence of the discrimination signal detection signal from the discrimination signal detector 9, and the terminal 10b is connected to the terminal 10b during the 1H period when the discrimination signal is detected.

The input signal of the terminal 11b is selectively outputted, and the input signal of the terminals 10a and 11a is selectively outputted during the 1H period when no discrimination signal is detected. As a result, the switch circuit 10 is connected to the output terminal 12.
Therefore, the reproduced color difference signal R- as schematically shown in FIG. 5(E)
A reproduced color difference signal B-Y is output from the switch circuit 11 to the output terminal 13 as schematically shown in FIG.

Problems to be Solved by the Invention However, the line sequential method utilizes the line correlation of the color difference signals to repeatedly reproduce the color difference signals of 1H period every 2H. If the line correlation collapses, for example, the color difference signal R-Y shown in FIG.
When the amplitude of changes from rOJ to [0,3J and when the amplitude of
．． When the amplitude of the color difference signal B-Y shown in FIG. 5(B) changes from rOJ to "1" and from "1" to rOJ, the output terminal 12.13 There was a problem in that a reproduced color difference signal (hereinafter referred to as a pseudo signal) having an amplitude different from that of the primary color difference signal waveform was generated during the period indicated by X in (D) and (E) of the same figure. .

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a video signal correction circuit that solves the above problems by replacing the above-mentioned pseudo signal with a signal of the correct imaging width.

Means for Solving the Problems The video signal correction circuit according to the present invention supplies a line-sequential signal, in which first and second video signals are synthesized alternately and in time series every 1H, via a transmission path. , by using a first delay circuit having a delay time of 1H. to the second output terminal. A circuit connected to a device that outputs a second video signal, the circuit including second to fifth delay circuits with a delay time of 1H, first and second comparison and identification circuits, and first and second signal outputting circuits. It consists of a generation source and first to fourth switch circuits. Above 1. The first and second video signals from the second output terminal are output from the first and second output terminals. The second comparison and discrimination circuit causes the second. The first .1H taken out from the third delay circuit. The level is compared with the second video signal, and when they substantially match, a matching signal is output.

The fourth delay circuit is supplied with the output signal of the first switch circuit, and receives a coincidence signal from the first comparison/discrimination circuit delayed by 1H or a coincidence signal from the first signal generation source delayed by 1H. The first period in which the signal No. 1 is output is the same as the second signal.
The switch circuit selectively outputs the output signal of the second comparison and discrimination circuit, and the fourth switch circuit selectively outputs the output signal of the third delay circuit. Further, the fifth delay circuit is supplied with the output signal of the second switch circuit, and is supplied with a coincidence signal from the second comparison discrimination circuit delayed by 1H or from the second signal generation source delayed by 1H. During the second period for outputting the second signal, the first switch circuit selects and outputs the output signal of the first comparison and discrimination circuit, and the third switch circuit selects and outputs the output signal of the first comparison and discrimination circuit. The output signal of is selectively output. Furthermore, a period during which signals other than the above are output from the fourth and fifth delay circuits,
That is, periods other than the first and second periods are the fourth period.
The output signal of the fifth delay circuit causes the first and second switch circuits to switch between the first and second switch circuits. While the second signal is selectively output,
Third. The fourth switch circuit is connected to the first switch circuit. The first output from the second output terminal. The second video signal is selectively output.

If there is no line correlation between the first and second video signals constituting the line-of-action sequential signal, as explained in conjunction with FIG. The first output terminal is taken out from the second output terminal. The second video signal has a signal waveform different from the original video signal waveform. Therefore, in this case, since the coincidence signal is not taken out from the first and second comparison and identification circuits, the first
．． The second signal is the fourth signal. Since the output is from the fifth delay circuit, the third. The output video signal of the fourth switch circuit is the first video signal 1H later (1H temporally future). Switch to the second video signal.

That is, 3rd. The reproduced video signal taken out from the fourth switch circuit is normally the first one. Since the match signal is output from the second comparison/discrimination circuit, the second. The 1st and 2nd video signals delayed by 1H by the third delay circuit are output, but if the line correlation collapses, the
After 1H, the 1st. Switch to the second video signal. As a result, reproduced video signals with correctly restored waveforms are taken out from the third and fourth switch circuits. Next, one embodiment of the present invention will be described.

Embodiment FIG. 1 shows a block diagram of an embodiment of the circuit of the present invention. The recording and reproducing device 15 has a color difference signal recording and reproducing system as shown in FIG. It also has a regeneration system. A first video signal, for example, a color difference signal R-Y, is taken out from the first output terminal 12 shown in FIG. A second video signal, for example, a color difference signal @B-Y, is extracted, and these color difference signals are supplied to the correction circuit 16, respectively. On the other hand, the reproduced luminance signal is taken out from the luminance signal recording and reproducing system in the recording and reproducing device 15, and the 1H delay circuit 1
7, where it is delayed by 1H for time alignment with the output color difference signal of the correction circuit 16, and then output to the output terminal 18.

The color difference signal R-Y taken out from the output terminal 12 is 1HM.
Extension circuit 22. The signal is supplied to the terminal 24b of the comparison/discrimination circuit 23 and the switch circuit 24, respectively. On the other hand, the color difference signal B-Y taken out from the output terminal 13 is sent to the 1H delay circuit 19. The signal is supplied to the terminal 21b of the comparison/discrimination circuit 20 and the switch circuit 21, respectively.

Here, the color difference signal recording and reproducing system in the recording and reproducing device 15 has a configuration as shown in FIG.
When the color difference signals (original signals) shown in Figures (A) and (B) come in, the demodulator 7 shown in Figure 4 The output signal waveform is shown in Figure 2 (C
), and color difference signals B-Y and R-Y as schematically shown by a and b in FIGS. 2(D) and (E) are taken out from the output terminals 13.12. Therefore, in this case, each output signal of the 1H delay circuits 19 and 22 is as shown in FIG.
and delayed color difference signals C and d as schematically shown in (G). The delayed color difference signal C is connected to the terminal 21a of the switch circuit 21.
while being supplied to the comparison and identification circuit 20. Further, the delayed color difference signal d is supplied to the terminal 24a of the switch circuit 24, and is also supplied to the comparison discrimination circuit 23.

The comparison discrimination circuit 20 is 1Hi! ! The levels of the input color difference signal a and the output color difference signal C of the extension circuit 19 are compared, and a high level matching signal is output only when the two signal levels substantially match, and a low level signal is output when they do not match. (does not output match signal). Therefore, the comparison discrimination circuit 2
The output signal of 0 becomes the signal e schematically shown in FIG. 2(H). Similarly, the comparison/discrimination circuit 23 compares the levels of the input color difference signal (1) and the output color difference signal (d) of the 1H delay circuit 22, and outputs a high-level match signal only when the two signal levels substantially match. When not in use, it outputs a low level signal. Therefore, the output signal of the comparison and discrimination circuit 23 becomes the signal f schematically shown in FIG. 2(1). The switch circuit 25 has the output signal e applied to a terminal 25a, and
A constant DC voltage corresponding to a high level from the DC voltage source 26 is applied to the terminal 25b, and one of them is selectively outputted and supplied to the 1HM extension circuit 27. On the other hand, switch circuit 2
8, the output signal f is applied to the terminal 28a, and a constant DC voltage corresponding to a high level from the DC voltage source 29 is supplied to the terminal 28b, and one of these input signals is selected and outputted to IH1. It is supplied to the extension circuit 30.

The output signal of the 1H delay circuit 27 is sent to the switch circuits 24 and 2.
The output signal of the 1H delay circuit 30 is applied as a switching signal to the switch circuits 21 and 25, respectively. Here, the switch circuits 21, 24, 25 and 28 are connected to terminals 21a, 24a, 2 when the switching signal is at a high level.
Connected to 5a and 28a, and 2 when the level is from mouth to level.
l b , 24b.

25b and 28b.

Therefore, when the line correlation of the input color difference signal a collapses and the output signal e becomes low level at time t1 shown in FIG. 2, the line correlation of the other input color difference signal does not collapse and the Since the output signal f is at a high level, the switch circuit 25 is connected to 25a, and at time t2 after 1H.
The output signal of the 1H delay circuit 27 becomes low level as schematically shown at 9 in FIG. 2(J), and the switch circuits 24 and 28 are switched to the terminals 24b and 28b, respectively.

As a result, the output signal f of the comparison discrimination circuit 23 at time t2
Even if becomes a low level, this low level signal f does not pass through the switch circuit 28, and high level signals from the two DC voltage sources pass through the switch circuit 28 and are supplied to the 1H delay circuit 30. . Therefore, the output signal of the 1H delay circuit 30 also becomes high level at time t3, 1H after t2, as schematically shown at h in FIG. 2(K), and the switch circuit 21
25 is then connected to the terminals 21a and 25a.

Furthermore, since the output signal e is at a high level at time 3, the switch circuit 24°28 is connected to the terminals 24a and 28a at time 4, 1H later, and the output signal f is at a low level at time t4. Therefore, the low level signal f passes through the switch circuit 28 and becomes 1Hil! It is supplied to the extension circuit 30.

As a result, even if one output signal @e of the comparison/identification circuit becomes low level at time °C5 1H after time t4, this low level signal will delay the low level output signal f at time t4 by 1Hil. Since the signal obtained by delaying by 1H in the circuit 30 is taken out at time t5 as shown in FIG. A high level signal from the DC voltage source 26 is sent from the circuit 25 to the 1H delay circuit 2.
7. Therefore, time t6 1H after time t5
Then, the output signal of the 1HN extension circuit 27 becomes high level as shown in FIG. 2 (LJ).

In this way, the output signals g and h of the 1H delay circuits 27 and 30 become as schematically shown in FIG. 2 (J) and (K), respectively.
A signal J schematically shown in FIG. 2 (M) is output to 1.
The switch circuit 24 outputs a signal 1 schematically shown in FIG. 3(L) to the output terminal 32. This signal i is shown in Figure 2 (
This is the same signal as the original color difference signal RY shown in A), and the signal j is the same signal as the original color difference signal B-Y shown in FIG. That is, the corrected primary color difference signals B-Y and R are output to the output terminals 31 and 32 by the correction circuit 16.
-Y is retrieved.

By the way, in the above case, the switch circuit 25°28, the DC voltage if! 26.29, the output signal of the comparison discrimination circuit 20.23 is transferred to the 1H delay circuit 27.30.
The primary color difference signal waveform can also be obtained by directly supplying the primary color difference signal waveform.

However, the waveforms of the primary color difference signals R-Y and 8-Y are
), (B), the switch circuit 25.2
If 8 etc. are omitted, the primary color difference signal waveform cannot be obtained. 3(C) is the output line sequential color difference signal of the demodulator 7 shown in FIG. 4, and the signal waveforms a to f schematically shown in FIG. The waveforms of each part shown in a~``,
FIGS. 3(L) and 3(M) show waveforms at the respective portions indicated by g and h in FIG. 1. FIG. 3(J) shows a signal waveform when the output signal e of the comparison/discrimination circuit 20 shown in FIG. 3(H) is directly supplied to the 1HM extension circuit 27 without using the switch circuit 25 and delayed by 1H. , and (K) in the same figure shows a signal waveform when the output signal f of the comparison/discrimination circuit 23 shown in ([) in the same figure is directly supplied to the 1H delay circuit 30 without using the switch circuit 28 and delayed by 1Hil. . When the switching circuit 24 is controlled by the signal shown in FIG. 3(J),
At the output end of the switch circuit 24, a color difference signal as shown in FIG. On the other hand, when the switch circuit 21 is subjected to switching control using the signal shown in FIG. 3(K), a color difference signal as shown in FIG. 3(P) is taken out at the output terminal of the switch circuit 21. The color difference signal shown in FIG. 3(Q) is the primary color difference signal RY shown in FIG.
), the color difference signal shown is the primary color difference signal B shown in (8) of the same figure.
-Y results in a different signal waveform.

Therefore, in this embodiment, as shown in FIG. 1, by providing the switch circuits 25 and 28, respectively, the signals shown schematically in FIGS. 9 and h. By controlling the switching of the switch circuit 24 using this signal g, a color difference signal i shown in FIG. 3(0) having the same waveform as the primary color difference signal RY is obtained from the switch circuit 24. Furthermore, compared to the signal shown in FIG. 3(K), the signal shown in FIG. 3(M) is different from the signal shown in FIG.
8, the level remains high for 1H period from time tb. Therefore, by controlling the switching of the switch circuit 21 using a signal, the IHm interval immediately after time tb is also 1
The output signal C (shown in FIG. 3(F)) of the H delay circuit 19 is outputted to the output terminal 31. The output signal of this switch circuit 21 is as shown by j in FIG. 3 (N>), and is a color difference signal having the same waveform as the primary color difference signal B-Y shown in FIG. 3(B).

Note that the present invention is not limited to the above-described embodiments, and the signal to be corrected may be a video signal, and therefore, the present invention can be applied to primary color signals in addition to color difference signals.

Effects of the Invention As described above, according to the present invention, by using a 1H delay circuit or the like, a pseudo signal generated in a line sequential method is replaced with a correct video signal, thereby correcting the pseudo signal and converting the original signal on the recording side. It has features such as being able to obtain a video signal with the same waveform as the video signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the circuit of the present invention;
2 and 3 are signal waveform diagrams for explaining the operation of the block system shown in FIG. 1, FIG. 4 is a block system diagram showing an example of a line-sequential recording/reproducing system, and FIG. It is a signal waveform diagram for explaining the operation of the block system. 8.17, 19.22.27.30... 1H delay circuit, 12.13... Reproduction color difference signal output terminal, 15...
Recording and reproducing device, 16... Correction circuit, 20.23...
Comparison identification circuit, 21, 24, 25.28... Switch circuit, 26.29... DC voltage source, 31.32...
Correction color difference signal output terminal. Figure 1 Figure 2 b b b t4ts ts →Kyoma Figure 3 → Shokaku

Claims (1)

[Claims] The first video signal and the second video signal are transmitted for one horizontal cycle period (
A line sequential signal synthesized alternately in time series every 1H) is supplied via a transmission line, and an output delay signal of a first delay circuit that delays this by 1H and an input signal of the first delay circuit. are selected and output alternately every 1H to the first output terminal.
The second video signal is output to the second output terminal.
A video signal correction circuit connected to a device that outputs a video signal, wherein the first and second video signals from the first and second output terminals are separately supplied and delayed by 1H. , compares the levels of the output signals of the third delay circuit, the second and third delay circuits, and the first and second video signals from the first and second output terminals, respectively, and compares the levels of both signals. first and second comparison and identification circuits that output a matching signal when the signals substantially match, and a first comparison and identification circuit that generates and outputs the first and second signals at a preset constant level.
and a second signal generation source, a first switch circuit that selectively outputs either the output signal of the first comparison and discrimination circuit or the first signal from the first signal generation source; a second switch circuit that selectively outputs either the output signal of the second comparison/identification circuit or the second signal from the second signal generation source; and the outputs of the first and second switch circuits. fourth and fifth delay circuits that are separately supplied with signals and delay them by 1H; and a fourth and fifth delay circuit that selectively outputs either the input signal or the output delayed signal of the second delay circuit as a first reproduced video signal. 3
and a fourth switch circuit that selects and outputs either the input signal or output delay signal of the third delay circuit as a second reproduced video signal, and During the first period in which the delayed matching signal from the first comparing/discriminating circuit or the first signal delayed by 1H is taken out, the second switching circuit outputs the output from the second comparing/discriminating circuit. At the same time, the fourth switch circuit selectively outputs the output signal of the third delay circuit, and the output signal from the second comparison/discrimination circuit delayed by 1H from the fifth delay circuit. During the second period in which the coincidence signal or the second signal delayed by 1H is taken out, the first switch circuit selectively outputs the output signal of the first comparison and discrimination circuit, and the third switch The circuit selectively outputs the output signal of the second delay circuit, and the first and second switch circuits selectively output the output signal of the second delay circuit during periods other than the first and second periods. In addition to selectively outputting
A video signal correction circuit characterized in that the third and fourth switch circuits are configured to selectively output the first and second video signals from the first and second output terminals.