JPH04265074A - Video signal processor - Google Patents

Abstract

PURPOSE:To reduce degradation in picture quality due to a difference in transmission line characteristic by emphasizing the difference between plural divided transmission signals to record and transmit them and compressing the difference between transmission signals at the time of multiplexing video signals. CONSTITUTION:After a video signal V inputted from a terminal 1 is alternately distributed to two channels A and B in every line by a channel dividing circuit 3, the time base is expanded twice to generate A and B channel signals Va and Vb. Signals Va and Vb are added by an adding circuit 5 to generate a channel sum signal Vc and are subjected to subtraction by a subtracting circuit 7 to generate a channel difference signal CS. The signal CS is inputted to a level converting circuit 9, and a difference signal CS is outputted which has the level converted so that the gain is raised in the case of a short amplitude of the signal CS and is reduced in the case of a long amplitude of the signal CS. Signals CS' and CA are inputted to an adding circuit, and signals V'a and V'b consisting of halves of the sum and the difference are recorded on a magnetic tape 21 after FM modulation in modulation processing circuits 15 and 17.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a video signal processing device for recording, reproducing, or transmitting a video signal, and in particular, for recording or transmitting a video signal by dividing it into a plurality of transmission paths. The present invention relates to a video signal processing device suitable for reducing image quality deterioration caused by differences in characteristics such as nonlinear distortion, gain fluctuation, and DC fluctuation.

0002

[Prior Art] In high-definition televisions such as high-definition televisions, which provide much higher definition and higher quality images than current television systems, conventional television systems are used to transmit high-definition and high-definition image information. A transmission band several times larger than that required is required.

[0003] When recording, reproducing, or transmitting high-definition television signals such as high-definition television, there is a method of recording or transmitting by dividing the video signal into multiple transmission paths and reducing the bandwidth of each transmission path. It is used. In such recording and transmission systems, one video signal is divided into parts, transmitted through different transmission paths, and then combined into one video signal again. Therefore, if there is a difference in transmission path characteristics such as linearity, gain, DC characteristics, etc. between the respective transmission paths, significant image quality deterioration occurs in the combined video signal due to line flicker, line pairing, etc.

[0004] In the conventional device, Japanese Patent Application Laid-Open No. 62-15983
As described in the publication, when dividing a video signal, a reference signal is multiplexed and recorded, and during playback, the reference signal is corrected for each transmission path so that it has a predetermined value, so that the relative A method was used to eliminate differences in transmission path characteristics.

[0005]

[Problem to be solved by the invention] In the above conventional technology,
There was a problem in that it was necessary to multiplex the reference signal in advance when dividing the video signal, and the original video signal could not be transmitted during the multiplexing period of the reference signal, making it impossible to use the transmission path effectively. . In addition, a malfunction prevention circuit or a reference signal noise removal circuit is required in case the multiplexed reference signal is not completely regenerated due to noise or dropouts occurring in the transmission path, and large-scale and complex signal processing is required. A circuit was needed.

An object of the present invention is to provide a video signal processing circuit that does not require multiplexing of reference signals and is capable of reducing image quality deterioration due to characteristic differences between transmission paths using a simple circuit.

[0007]

[Means for Solving the Problems] The above object is achieved as follows. In other words, the difference between each transmission signal that is divided and transmitted is processed and recorded and transmitted, and when the video signal is synthesized from each transmission path, the difference between each transmission signal is emphasized. Processing is performed to reduce the difference.

Furthermore, in order to suppress an extreme increase in the amplitude of the transmission signal by emphasizing the difference between the transmission signals, the degree of emphasis is increased when the difference between the transmission signals is small; If it is large, processing is performed to reduce the degree of emphasis.

[0009]

[Operation] The video signal processing apparatus of the present invention can be separated into pre-processing in the recording and transmitting process and post-processing in combining the video signals from each transmission path. That is, pre-processing is performed to emphasize the differences between the respective transmission signals that are divided into a plurality of parts and transmitted, and post-processing is performed to compress the differences between the respective transmission signals. These pre-processing and post-processing have a one-to-one correspondence and are completely opposite processes, so the video signal is perfectly reproduced without any deterioration.

On the other hand, the above-mentioned post-processing operates to reduce the difference between each transmission signal, that is, to average the signals from each transmission path, so that the D
Level differences caused by differences in transmission path characteristics such as C variation, gain variation, and linearity distortion are reduced by averaging. That is, it is possible to reduce image quality deterioration such as line flicker and line pairing caused by differences in transmission path characteristics such as linearity, gain, and DC characteristics.

[0011] The above-mentioned reduction in image quality deterioration caused by differences in transmission path characteristics can be more effectively achieved by further compressing the differences between transmission signals in post-processing. However, this requires more emphasis on the difference between the transmitted signals in preprocessing, and the amplitude of the transmitted signal increases due to the emphasis on the difference signal. Therefore, when the difference between the transmission signals is small, the degree of emphasis is increased, and when the difference is large, the degree of emphasis is decreased, thereby suppressing the extreme increase in the amplitude of the transmission signal. At the same time, it is possible to enhance the effect of reducing image quality deterioration caused by differences in transmission path characteristics.

[0012] Furthermore, since the above-mentioned post-processing operates to reduce the difference between each transmission signal, that is, to average the signals from each transmission path, the noise components independently superimposed on each transmission path are There is also a secondary effect of reduction through averaging.

[0013]

[Embodiments] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a magnetic recording and reproducing apparatus that records and reproduces a video signal by dividing it into two channels.

In FIG. 1, 1 is an input terminal for a video signal V to be recorded, and 3 is a channel division circuit that divides the video signal V input from 1 into two signals, an A channel signal Va and a B channel signal Vb. , 5 is an adder circuit that adds the channel-divided Va and Vb to generate the channel sum signal CA, 7 is a subtracter circuit that subtracts Va and Vb to generate the channel difference signal CS, and 9 is the adder circuit that adds the channel-divided Va and Vb to generate the channel sum signal CA. A level conversion circuit performs non-linear level conversion and converts it into CS'; 11 is an addition circuit that adds the channel sum signal CA and the level-converted channel difference signal CS' and outputs Va'; 13 is a channel sum signal CA; Subtraction circuits 15 and 17 subtract the level-converted channel difference signal CS' and output Vb'.
Modulation processing circuits 19 and 20 that modulate in a form suitable for recording in the head system (for example, FM modulation) record the signals modulated by the modulation processing circuits 15 and 17 on a magnetic tape during recording, and transfer the signals to the magnetic tape during playback. - a magnetic head for reproducing the signals recorded on the tape; 21, the magnetic tape; 16 and 18, demodulation processing circuits for demodulating the signals reproduced by the magnetic heads 19 and 20, respectively, and reproducing PVa' and PVb'; ,1
2 is an addition circuit that performs addition processing on the demodulated PVa' and PVb' to generate a reproduced channel sum signal PCA; 14 is a subtraction circuit that performs subtraction processing on the demodulated PVa' and PVb';
10 is a level inversion circuit that performs level conversion on PCS' with the inverse characteristics of level conversion circuit 9 and converts it into PCS; 6 is a reproduction channel sum signal PCA and a reproduction channel difference signal PCS whose level has been inversely converted. An adder circuit 8 performs addition processing to output the reproduced A-channel signal PVa, and 8 subtracts the reproduced channel sum signal PCA and the reproduced channel difference signal PCS whose level has been inversely converted, and outputs the reproduced B-channel signal PV.
4 is the reproduction A channel signal PVa.
and a reproduced B channel signal PVb to generate a reproduced video signal PV. 2 is an output terminal of the reproduced video signal PV resulting from the channel combination.

Next, the operation of this embodiment will be explained using the block diagram shown in FIG. 1 and the waveform diagram shown in FIG. 2. The video signal V input from the terminal 1 is sent to the channel division circuit 3, where it is alternately distributed line by line into two channels, A and B, and the time axis of each is expanded by twice to produce an A channel signal Va and a B channel signal Vb. is generated. FIG. 2(1) shows waveform diagrams of V, FIG. 2(2) shows Va, and FIG. 2(3) shows Vb. L1, L2, . . . in FIG. 2 represent lines of video signals, and Va has odd lines L1, L3, .
Even-numbered lines L2, L4, . . . are outputted to Vb with their respective time axes expanded twice. Next, the channel-divided channel signals Va and Vb are subjected to addition processing in an adder circuit 5 to generate a channel sum signal CA.
, Vb are subjected to subtraction processing by the subtraction circuit 7 to produce a channel difference signal CS
is generated. The generation process of CA and CS is shown in the following equation.

[0017]

[Math 1]

[0018]

[Math 2]

Channel difference signal C generated by subtraction circuit 7
S is input to a level conversion circuit 9, which outputs a channel difference signal CS' that undergoes nonlinear level conversion so that the gain is high when the amplitude of CS is small, and the gain is low when the amplitude of CS is large. be done.

After that, both the level-converted channel difference signal CS' and the channel sum signal CA are sent to the adder circuit 11.
and is input to the subtraction circuit 13 to generate Va' and Vb'. The generation process of these Va' and Vb' is shown in the following equation.

[0021]

[Math 3]

[0022]

[Math 4]

Va' and Vb' are subjected to FM modulation in modulation processing circuits 15 and 17, respectively, and then recorded on magnetic tape 21 independently for each channel via magnetic heads 19 and 20.

The level conversion circuit 9 shown here can be realized by utilizing the nonlinear characteristics of a diode, a transistor, or the like. Furthermore, when the channel division circuit 3 is configured with a digital circuit, the addition circuits 5 and 11 and the subtraction circuits 7 and 13 may be configured with digital circuits, and the level conversion circuit 9 may be configured with a ROM (read only memory). . That is, the output value for each input level of the nonlinear function is written in advance as ROM data at an address equal to the input level, the input CS is connected as the address, and this ROM data output is used as the level-converted signal CS. 'And it is sufficient. In this case, the outputs Va and Vb of the channel division circuit 3 are output as digital signals, and after being digitally processed by the addition circuits 5 and 11, the subtraction circuits 7 and 13, and the level conversion circuit 9, Va'
, Vb' are converted into analog signals by D/A converters provided in the modulation processing circuits 15 and 17 and subjected to modulation processing. By doing this, it is possible to eliminate unnecessary A/D and D/A conversion circuits, and most of the recording signal processing except for the modulation processing circuit can be digitally processed. There are economic effects due to circuit miniaturization, power saving, etc.

Furthermore, so that a predetermined phase between channels such as H alignment can be realized on the track pattern formed on the magnetic tape 21 by the magnetic heads 19 and 20,
If it is necessary to delay the signal of either channel, most of the recording signal processing except for the modulation processing circuit is implemented by a digital processing circuit as described above, and the addition circuit 11
A delay circuit such as a digital memory may be inserted between the subtraction circuit 13 and the modulation processing circuit 15 or between the subtraction circuit 13 and the modulation processing circuit 17.

Through the above-described operation, the video signal inputted from the terminal 1 is divided into two channels by the channel division circuit 3, and the difference between the channels is emphasized when the amplitude is small due to the nonlinear characteristics of the level conversion circuit 9. It will be recorded.

During reproduction, the signals reproduced from the magnetic tape 21 by the magnetic heads 19 and 20 are demodulated in demodulation processing circuits 16 and 18, respectively, and are converted into PVa'
and PVb' are output. Demodulated PVa' and PV
b' are input to an adder circuit 12 and a subtracter circuit 14 to generate a reproduced channel sum signal PCA and a level-converted reproduced difference signal PCS'. These PCA and P
The generation process of CS' is shown in the following equation.

[0028]

[Math 5]

[0029]

[Math 6]

As shown in the above equation and equations (3) and (4), if the recorded signals Va' and Vb' are completely reproduced without deterioration, that is, PVa' becomes Va'
When PVb' is equal to Vb', the channel sum signal CA is reproduced in the reproduced channel sum signal PCA. Similarly, in this case, the level-converted reproduced difference signal PCS' becomes completely equal to CS' in the recording process.

The level-converted reproduced difference signal PCS' output from the subtraction circuit 14 is input to the level inverse conversion circuit 10, where it is subjected to non-linear level conversion with characteristics opposite to those of the level conversion circuit 9. This is the opposite of the level conversion circuit 9.
Since it is a conversion to S, as shown above, V
Each signal of a' and Vb' is PVa', P without any deterioration.
When reproduced as Vb', PCS'=CS', and the output PCS of the level inversion circuit 10 is converted to be equal to CS.

The reproduced channel sum signal PCA and the reproduced channel difference signal PCS obtained as described above are input to the adder circuit 6 and the subtracter circuit 8, and are subjected to arithmetic processing into a reproduced A channel signal PVa and a reproduced B channel signal PVb. Ru. The calculation process of these PVa and PVb is shown in the following equation.

[0033]

[Math 7]

[0034]

[Math. 8]

As shown above, the recorded Va'
and Vb' signals PVa' and PVb completely without deterioration.
', PCS=CS, PCA=C
Since A, from the above formula, formula (1), and formula (2),
The reproduced A channel signal PVa is reproduced equally to the A channel signal Va in the recording process. Similarly, the reproduced B channel signal PVb is reproduced equally to the B channel signal Vb in the recording process.

The reproduced A channel signal PVa and the reproduced B channel signal PVb thus obtained are input to the channel synthesis circuit 4, where they are synthesized into a series of reproduced video signals PV and outputted from the output terminal 2. The operation of this channel synthesis circuit is opposite to the operation of the channel division circuit 3 whose waveform diagram is shown in FIG. Channel synthesis processing is performed by alternately outputting the signals.

Note that the level inverse conversion circuit 10 shown here can be realized by utilizing the nonlinear characteristics of a diode, a transistor, etc., similarly to the level conversion circuit 9. Furthermore, when the channel synthesis circuit 4 is configured with digital circuits, the adder circuits 6 and 12 and the subtraction circuits 8 and 14 are configured with digital circuits, and the level inverse conversion circuit 10 is configured with a ROM like the level conversion circuit 9. It's okay. That is, the converted PCS is written in advance as data at an address equal to the input PCS', and the input PCS' is
may be connected as an address, and this ROM data output may be used as the level-converted signal PCS. In this case, the demodulated PVa' and PVb' are converted into digital signals by the A/D conversion circuits provided in the demodulation processing circuits 16 and 18, and then outputted as the output P of the adder circuit 6.
Va and the output PVb of the subtraction circuit are input to the channel synthesis circuit 4 as digital signals. By doing this, unnecessary A/D and D/A conversion circuits can be omitted,
In addition, since most of the reproduced signal processing except for the demodulation processing circuit can be digitally processed, there are economical effects such as miniaturization of the processing circuit and power saving by using LSI.

Furthermore, so that a predetermined phase between channels such as H alignment can be realized on the track pattern formed on the magnetic tape 21 by the magnetic heads 19 and 20,
When the signal of either channel is delayed and recorded, a delay circuit is inserted into the output stage of the demodulation processing circuit 16 or 18, and the signal output from the demodulation processing circuit is processed with a predetermined delay. It should be configured as follows.

Through the above-described operation, a signal whose difference between channels during recording is emphasized in a small amplitude region due to the nonlinear characteristics of the level conversion circuit 9 is converted to a small amplitude channel by the level inversion circuit 10 in the reproduction signal processing process. The difference between the signals is compressed and returned to a signal having the original difference, which is further synthesized into a series of reproduced video signals by the channel synthesis circuit 4. Therefore, modulation/demodulation processing and magnetic recording/reproduction operate ideally, and the recorded Va', Vb' signals are completely converted to PVa.
', PVb', the channel-divided channel signals of Va and Vb are reproduced as PVa and PVb without deterioration.
The channels are combined as follows.

Furthermore, the modulation processing circuit 15 and the magnetic head 1
9. The modulation/demodulation characteristics and If there are differences in transmission characteristics including electromagnetic conversion characteristics, etc., such as linearity, gain, DC characteristics, etc., these characteristic differences cause fluctuations in the original differences between channels. According to the present invention, even if the difference between channels varies due to such a difference in characteristics of the transmission path,
Since the inter-channel difference of the original video signal is emphasized and the inter-channel difference is compressed by the level inversion circuit 10 in the process of processing the reproduced signal, it is possible to reduce the influence of the inter-channel difference fluctuation due to the characteristic difference of the transmission path. . therefore,
Line flicker caused by differences in the characteristics of these transmission lines,
This has the effect of reducing image quality deterioration due to line pairing, etc.

Furthermore, in the inter-channel difference compression process by the level inversion circuit 10 in the reproduced signal processing process, the reproduced signals PVa' and PVb' from the two channels are averaged in the region where the inter-channel difference is a small signal. It can be considered as processing. Therefore, when considering the noise generated in the transmission process, the independent noises superimposed on these two signals PVa' and PVb' are averaged, which also has the effect of reducing the noise.

Next, the characteristics and operations of the level conversion circuit 9 and the level inversion circuit 10 shown in the block diagram of FIG. 1 will be explained using the characteristic diagrams of FIGS. 3 and 4. Note that here, the level conversion circuit 9 and the level inversion circuit 10 are R.
A case of configuration using OM will be explained. It is also assumed that the input video signal is quantized with 8 bits and has 0 to 255 levels.

FIG. 3 shows the level conversion characteristics of the output CS' with respect to the input CS of the level conversion circuit 9 shown in the block diagram of FIG. The slope of this level conversion characteristic is the difference between the input signal (CS) and the signal after level conversion (CS').
It represents the ratio of , that is, the gain, and is set to be greater than 1 in a region where the input amplitude is small. Further, the full scale value after level conversion is set to be equal to the full scale value of the input signal. Due to this level conversion characteristic, when the amplitude of the channel difference signal CS is small, the difference signal is emphasized, and even when the amplitude of the channel difference signal CS is large, the level conversion is performed so that the level after conversion does not exceed the full scale value of the input. will be carried out.

As shown in the waveform diagram of FIG. 2, the channel division in this embodiment is to divide the signals of two adjacent lines in the field into an A channel signal Va and a B channel signal Vb. The channel difference signal CS is a difference signal between two adjacent lines. In general video signals, signals on adjacent lines are often similar, so the amplitude of the channel difference signal CS is rarely large, and usually takes a small amplitude value. In addition, even if the channel division method is different from this embodiment, if it is a channel division method in which adjacent signals on the screen are sequentially divided into each channel, the channel difference signal CS
The amplitude of is normally a small amplitude value. Such a channel division method is also advantageous in terms of the hardware scale of the channel division circuit and the channel combination circuit.

Furthermore, when this level conversion characteristic is not applied, CS=CS', which is equivalent to using the characteristic indicated by the broken line in FIG. In this case, the above formula (1) ~
As shown in equation (4), Va=Va', Vb=Vb
', and the channel-divided signals are demodulated and recorded as they are. On the other hand, when the level conversion characteristic indicated by the solid line in FIG. 3 is applied, the level-converted value of CS' is d on the positive side and - There is a possibility of an increase in the level of d. Therefore, as shown in Equations (3) and (4), the amplitudes of Va' and Vb' increase by d levels (d/2 on the positive side and -d/2 on the negative side) by applying the level conversion characteristic. ) will be done. Usually the value of d is 10% to 30% of the maximum amplitude of the video signal.
%, the channel difference signal C normally takes a small amplitude value due to only a slight increase in the amplitude of the recorded signal.
S can be emphasized effectively.

FIG. 4 shows the level inversion characteristics of the output PCS with respect to the input PCS' of the level inversion circuit 10 shown in the block diagram of FIG. This level inverse conversion characteristic is an inverse function of the level conversion characteristic of the level conversion circuit 9 shown in FIG. 3, and the gain is set to be smaller than 1 in a region where the input amplitude is small. Similarly, the full scale value after level inversion is set to be equal to the full scale value of the input signal.

Due to this level inversion characteristic, the channel difference signal emphasized in the small amplitude region during recording is returned to its original level, and at this time, the fluctuation of the difference between channels caused by the characteristic difference of the transmission path, and further the recording and reproduction. Noise components generated during the process are also reduced. As a result, it is possible to reduce image quality deterioration such as line flicker and line pairing caused by differences in the characteristics of these transmission paths, and it is also possible to simultaneously reduce noise superimposed on reproduced video signals.

By configuring the level conversion circuit 9 and the level inversion circuit 10 using ROM as described above,
Any conversion characteristic can be set, and matching with the inverse conversion characteristic can be achieved with high accuracy.

Furthermore, when the present invention is implemented by a digital signal processing circuit, the amplitude increases due to channel difference signal emphasizing processing, so it is necessary to increase the number of bits for signal processing. However, as shown in this embodiment, the emphasis processing of the channel difference signal is performed after the channel division processing, and the channel synthesis processing is performed after the compression processing of the reproduction channel difference signal in the reproduction signal processing, so that the signal processing process can be improved. This has the effect of minimizing the increase in circuit scale due to the increase in the number of bits. For example, when an input video signal is quantized with 8 bits, the complex signal processing of the channel dividing circuit and channel combining circuit is processed with 8 bits, and the addition circuit, subtraction circuit, level conversion circuit, and level conversion circuit related to the present invention are processed using 8 bits. It is sufficient to increase the number of processing bits only for the inverse conversion circuit and the like and perform processing using 9 bits.

Next, another embodiment in which the present invention is applied to a magnetic recording and reproducing apparatus that records and reproduces a video signal by dividing it into two channels will be described with reference to the block diagram of FIG.

In FIG. 5, 1 is an input terminal for the video signal V to be recorded, and 3 is a channel division circuit that divides the video signal V input from 1 into two signals, an A channel signal Va and a B channel signal Vb. , 5 is an adder circuit that adds the channel-divided Va and Vb to generate the channel sum signal CA, 7 is a subtracter circuit that subtracts Va and Vb to generate the channel difference signal CS, and 9 is the adder circuit that adds the channel-divided Va and Vb to generate the channel sum signal CA. A level conversion circuit performs non-linear level conversion and converts it into CS'; 11 is an addition circuit that adds the channel sum signal CA and the level-converted channel difference signal CS' and outputs Va'; 13 is a channel sum signal CA; Subtraction circuits 15 and 17 subtract the level-converted channel difference signal CS' and output Vb'.
Modulation processing circuits 19 and 20 that modulate in a form suitable for recording in the head system (for example, FM modulation) record the signals modulated by the modulation processing circuits 15 and 17 on a magnetic tape during recording, and transfer the signals to the magnetic tape during playback. 21 is a magnetic tape; 16 and 18 are demodulation processing circuits that demodulate signals reproduced by the magnetic heads 19 and 20, respectively; 22 and 23 are demodulation processing circuits; 1
Time axis correction circuits 6 and 18 correct the time axes of the demodulated signals and output them as PVa' and PVb', and 12 adds the time axis corrected PVa' and PVb' to reproduce the reproduction channel sum. An addition circuit that generates the signal PCA; 14 a subtraction circuit that performs subtraction processing on PVa' and PVb' that have been subjected to time axis correction processing to generate PCS'; 10 a subtraction circuit that generates PCS';
The level conversion circuit 9 performs level conversion with the inverse characteristics to the PCS.
6 is a level inversion circuit that converts the playback channel sum signal PCA and the playback channel difference signal PCS whose level has been inversely converted.
An adder circuit 8 performs addition processing to output the reproduced A channel signal PVa, and an adder circuit 8 subtracts the reproduced channel sum signal PCA and the reproduced channel difference signal PCS whose level has been inversely converted to reproduce the reproduced B channel signal PVa.
4 is a subtraction circuit that outputs the channel signal PVb; 4 is a channel synthesis circuit that synthesizes the reproduced A channel signal PVa and the reproduced B channel signal PVb to generate a reproduced video signal PV; 2 is an output of the channel-combined reproduced video signal PV It is a terminal.

The embodiment whose block diagram is shown in FIG. 5 has the structure of the embodiment of FIG. 1 added with time axis correction circuits 22 and 23, and the other structure is the same as that of the embodiment of FIG. . That is, the signal demodulated by the demodulation processing circuit 16 is input to the time axis correction circuit 22, and is processed by using a signal serving as a time axis reference such as a negative synchronization signal or a burst signal included in the recording signal. , corrects time axis fluctuations such as jitter and skew of the reproduced signal, and converts the corrected signal into PVa'
The signal is input to the addition circuit 12 and the subtraction circuit 14 as a result. Similarly, the signal demodulated by the demodulation processing circuit 18 is input to the time axis correction circuit 23, and after correcting the time axis fluctuation of the reproduced signal, it is output as PVb' to the addition circuit 12 and the subtraction circuit 1.
4 is input.

By inserting the time axis correction circuits 22 and 23 after the demodulation processing circuits 16 and 18, time axis fluctuations such as jitter and skew of the reproduced signal are removed, and at the same time, the time axis between channels is The deviation can also be relatively removed. Therefore, there is an effect that signals such as PCA and PCS' generated by addition and subtraction processing of PVa' and PVb' can be generated and processed with high precision without being affected by time lag between channels.

Note that when the processing after this time axis correction circuit, that is, the addition circuits 6 and 12, the subtraction circuits 8 and 14, the level inversion circuit 10, and the channel synthesis circuit 4 are configured with digital circuits, the time axis correction circuit A/
The signal converted into digital data by the D conversion circuit is
After time axis correction, the digital signals may be output as PVa' and PVb'. By doing this, unnecessary A/D and D/A conversion circuits can be omitted, and most of the reproduced signal processing except for the demodulation processing circuit can be digitally processed, so the processing can be performed using LSI etc. There are economic effects due to circuit miniaturization, power saving, etc.

Further, so that a predetermined phase between channels such as H alignment is realized on the track pattern formed on the magnetic tape 21 by the magnetic heads 19 and 20,
When the signal of either channel is recorded with a delay, the time axis correction circuits 22 and 23 may be configured to correct the time difference between the demodulated signals.

Next, an embodiment in which the present invention is applied to a magnetic recording and reproducing apparatus that multiplexes a luminance signal and a color signal in the time axis and further divides them into two channels for recording and reproducing will be described with reference to the block diagram and the diagram in FIG. This will be explained using the waveform diagram in FIG.

In FIG. 6, 1 is an input terminal for the luminance signal V to be recorded, 24 is an input terminal for the first color signal CR, 25 is an input terminal for the second color signal CB, and 28 is the first color input terminal. A color signal line sequential circuit receives the signal CR and the second color signal CB and alternately switches the two color signals line by line to make them line sequential; 3 is a luminance signal V input from 1 and a color signal line sequential circuit; a channel division circuit that receives the color signal line-sequentialized at 28, time-axis multiplexes the luminance signal and the color signal, and divides it into two signals, an A channel signal Va and a B channel signal Vb;
5 is an adder circuit that performs addition processing on the channel-divided Va and Vb to generate a channel sum signal CA; 7 is a subtraction circuit that performs subtraction processing on Va and Vb to generate a channel difference signal CS; 9 is a nonlinear circuit that produces a channel difference signal CS. CS' with level conversion
11 is a channel sum signal CA.
13 is a channel sum signal CA.
and a level-converted channel difference signal CS', and outputs Vb', 15 and 17 are Va', V
modulation processing circuits 19 and 20 that respectively modulate b' into a form suitable for tape head recording (for example, FM modulation);
21 is a magnetic head that records signals modulated by modulation processing circuits 15 and 17 on magnetic tape during recording, and reproduces the signals recorded on the magnetic tape during playback;
Demodulation processing circuits 22 and 23 respectively correct the time axes of the signals demodulated by the demodulation processing circuits 16 and 18 and convert them into PVa. A time axis correction circuit 12 outputs the time axis correction processed PVa' and PVb' as a reproduced channel sum signal P.
An addition circuit that generates CA; 14 a subtraction circuit that subtracts PVa' and PVb' that have been subjected to time axis correction processing to generate PCS'; 10 a subtraction circuit that performs level conversion on PCS' with the inverse characteristics of the level conversion circuit 9; A level inversion circuit that converts into
Reference numeral 6 denotes an adder circuit that adds the reproduced channel sum signal PCA and the reproduced channel difference signal PCS whose level has been inversely converted and outputs the reproduced A channel signal PVa, and 8 represents the reproduced channel sum signal PCA and the reproduced channel difference whose level has been inversely converted. signal pc
4 is a subtraction circuit that performs subtraction processing on S and outputs a reproduced B channel signal PVb; 4 is a subtracter circuit that performs channel synthesis of a reproduced A channel signal PVa and a reproduced B channel signal PVb, and generates a series of reproduced luminance signals PV and a series of line sequential reproduced color signals; 2 is an output terminal for the channel-combined reproduced luminance signal PV; 29 separates the first color signal and the second color signal from a series of channel-combined line-sequential reproduced color signals; and a color signal interpolation circuit that interpolates from the preceding and following lines and outputs them as a continuous signal during a period when each color signal is not output;
7 is an output terminal for the first reproduced color signal PCR separated and interpolated by the color signal interpolation circuit 29; 28 is the color signal interpolation circuit 2;
This is an output terminal for the second reproduced color signal PCB separated and interpolated by 9.

The embodiment whose block diagram is shown in FIG. 6 has the configuration of the embodiment shown in FIG. 28
, and a color signal interpolation circuit 29, an output terminal 27 for the first reproduced color signal PCR, and an output terminal 28 for the second reproduced color signal PCB.
, and the other configurations are the same as the embodiment shown in FIG. That is, in the embodiments shown in FIGS. 1 and 5, one system of video signals, such as a video signal consisting only of a luminance signal or a video signal in which a luminance signal and a chrominance signal are frequency multiplexed, is processed. However, the embodiment shown in FIG. 6 has input/output terminals for two types of color signals independent of the luminance signal. The first color signal CR and second color signal CB input from the input terminals 24 and 25 are sent to the color signal line sequential circuit 2.
8 and is line-sequentialized so that CR and CB appear alternately on each line. At this time, each color signal is thinned out at a ratio of 1 line to 2, so
In order to prevent the occurrence of aliasing distortion due to this thinning process, a prefilter processing circuit provided inside the color signal line sequential circuit 28 performs vertical band limiting processing and then line sequentialization is performed. The line-sequential signal of these two types of color signals CR and CB is input to the channel division circuit 3, where it is time-axis multiplexed with the luminance signal V input from the input terminal 1, and the A-channel signal Va and the B-channel signal Vb are Split into two signals. Next, time axis multiplexing of luminance signals and chrominance signals and channel division processing in this channel division circuit 3 will be explained using the waveform diagram of FIG. 7. FIG. 7(1) shows a waveform diagram of the A channel signal Va output from the channel division circuit 3, and FIG. 7(2) shows a waveform diagram of the B channel signal Vb. V1, V2, V3, . . . in FIG. 7 represent each line of the luminance signal V input from the input terminal 1. Further, C1, C2, C3, . . . represent each line of a signal in which two types of color signals CR and CB are line-sequentialized by the color signal line sequential circuit 28. As shown in FIG. 7, the time axis of the luminance signal V is expanded, and the time axis of the line-sequential color signal is compressed and divided into respective channels. In this case, the ratio of the time axis multiplex period of V and C is:
It is set to be equal to the ratio of the respective highest frequencies of the luminance signal and the color signal. That is, the highest frequency of the luminance signal is 20 MHz, and the highest frequency of the color signal is 5 MHz.
, the luminance signal V and the line-sequential color signal C
The time axis is converted so that the ratio of multiplexed periods is 4:1 (=20:5). The input luminance and color signals are input to channel A for the odd lines of V1, V3, . . . and C1, C3, .
The even numbered lines of C4, . At this time, in order to properly perform time axis correction in the reproduced signal processing, a signal such as a burst signal serving as a time axis reference may be added. After this, channel division circuit 3
The signals divided into the A channel signal Va and the B channel signal Vb are processed and recorded on the magnetic tape 21 in the same manner as in the embodiments of FIGS. 1 and 5.

When the signals recorded by the above processing are to be reproduced from the magnetic tape 21, the reproduced A channel signal PVa and the reproduced B channel signal PVb are processed in the same manner as in the embodiment shown in FIG. is generated and input to the channel combining circuit 4. In the channel synthesis circuit 4, the luminance signal and chrominance signal that are time-domain multiplexed in each channel are separated, each inversely converted in time-base and returned to the original time-base, and then converted into a series of reproduced luminance signals and a series of lines. The sequential reproduced color signals are combined and output. The reproduced luminance signal PV synthesized by the channel synthesis circuit 4 is outputted from the output terminal 2, and the line-sequential reproduced color signal is inputted to the color signal interpolation circuit 29. The color signal interpolation circuit 29 separates a first color signal and a second color signal from a series of channel-combined line-sequential reproduced color signals, and interpolates from the previous and succeeding lines during periods when each color signal is not output. The first reproduced color signal P as a continuous signal
CR and a second reproduced color signal PCB are generated and output to the output terminal 26.
and output from 27.

As explained above, when the present invention is applied to a magnetic recording and reproducing device that multiplexes a luminance signal and a chrominance signal in the time axis and further divides the luminance signal into two channels for recording and reproducing, the luminance signal and the chrominance signal are This has the effect of reducing image quality deterioration such as line flicker and line pairing, which are caused by differences in transmission path characteristics, which occur in both signals, and noise reduction by averaging the reproduced channel signals. In addition, there is no need for independent processing circuits for processing the luminance signal and the first and second color signals, and the processing of the luminance and color signals can be performed simultaneously with a single processing circuit, which has an economical effect by reducing the circuit size. .

In this embodiment, as shown in the waveform diagram of FIG. 7, the signals of each channel are multiplexed in the order of a negative synchronization signal and a burst signal, followed by a luminance signal and a chrominance signal. However, the order of the luminance signal and the chrominance signal is not limited to this, and the chrominance signal and the luminance signal may be multiplexed in this order following the negative synchronization signal and the burst signal. Regarding the order of channel division, the explanation has been made assuming that odd lines are divided into A channel signals and even lines are divided into B channel signals, but the order is not limited to this.
It is also possible to allocate odd numbered lines to the B channel. Furthermore, the correspondence between the luminance signal and the chrominance signal is reversed, for example, the luminance signal is divided into odd-numbered lines as A-channel signals and even-numbered lines as B-channel signals, and the chrominance signal is assigned as even-numbered lines to A and odd-numbered lines to B-channel. It may be.

Furthermore, in this embodiment, two types of color signals CR and C
After B is processed line-sequentially, for example, odd-numbered lines are processed as CR and even-numbered lines are processed as CB, the channels are divided into channels for each line. That is, when dividing odd lines into A channel signals and even lines into B channel signals, the color signals are always divided into CR for the A channel and CB for the B channel. In this case, in areas with low chromaticity, CR, CB
Each of the signals has a signal level near the achromatic level, and the channel difference becomes small, so it is possible to reduce fluctuations in the achromatic level caused by differences in characteristics between channels. Furthermore, as in the previous embodiments, there is also the effect of reducing noise in areas with low chromaticity. Also,
The color signals may be rearranged so that color signals of the same type are recorded simultaneously in adjacent channels. That is, the channel combining circuit is configured so that two types of color signals, CR and CB, are alternately output to the A channel, and CR and CB color signals are alternately output to the B channel in the same order. In this case, since the channel difference signal is always a difference between color signals of the same type, pairing of color signals and flicker can be reduced, as in the embodiments described above.

In addition, in this embodiment, after line-sequential processing of two types of color signals, the A and B channel signals are processed as a negative synchronization signal and a burst signal, followed by a luminance signal and a line-sequential color signal. However, the two types of color signals are not processed line-sequentially, and the signals of each channel are processed as a negative synchronization signal and a burst signal, followed by a luminance signal, a first color signal, and a second color signal. It may be multiplexed in this order. In this case, please refer to Figure 6.
The first color signal and the second color signal are input directly to the channel division circuit 3 from the input terminals 24 and 25 without using the color signal line sequential circuit 28 shown in FIG. Furthermore, the reproduced color signal is directly output from the channel synthesis circuit 4 to the output terminals 26 and 27 without using the color signal interpolation circuit 29.

In all the embodiments shown so far, the A channel signal Va and the B channel signal V given from the channel dividing circuit are as shown in the waveform diagrams of FIG. 2 or FIG.
In this embodiment, a negative synchronization signal and a burst signal are added and output to b. In other words, either the video signal including the synchronization signal is directly subjected to channel division processing, or only the effective area excluding the blanking period of the input video signal is subjected to channel division processing and then provided inside the channel division circuit. This figure shows a configuration in which a negative polarity synchronization signal, a burst signal, etc. are added and outputted by a synchronization signal addition circuit. The location where the negative polarity synchronization signal and burst signal are added is not limited to the configuration shown in these embodiments, and the negative polarity synchronization signal and burst signal may be added after emphasizing the channel difference signal. . This embodiment will be explained below using the block diagram of FIG.

In FIG. 8, 1 is an input terminal for a video signal V to be recorded, and 3 is a channel division circuit that divides the video signal V input from 1 into two signals, an A channel signal Va and a B channel signal Vb. , 5 is an adder circuit that adds the channel-divided Va and Vb to generate the channel sum signal CA, 7 is a subtracter circuit that subtracts Va and Vb to generate the channel difference signal CS, and 9 is the adder circuit that adds the channel-divided Va and Vb to generate the channel sum signal CA. A level conversion circuit performs non-linear level conversion and converts it into CS'; 11 is an addition circuit that adds the channel sum signal CA and the level-converted channel difference signal CS' and outputs Va'; 13 is a channel sum signal CA; Subtraction circuits 30 and 31 perform subtraction processing on the level-converted channel difference signal CS' and output Vb', and subtracting circuits 30 and 31 provide Va' and Vb' with a negative polarity synchronization signal and a burst signal used as a time axis reference in reproduction signal processing. The synchronization signal addition circuits 15 and 17, respectively added, are synchronization signal addition circuits 30 and 31, which output a negative polarity synchronization signal and a bar.
19 and 20 are modulation processing circuits 15 and 20 which respectively modulate the signal to which the strike signal has been added into a form suitable for recording on a tape head system (for example, FM modulation);
Magnetic heads 17 record the modulated signals on magnetic tapes and reproduce the signals recorded on the magnetic tapes during reproduction; 21 is a magnetic tape; 16 and 18 are magnetic heads 1;
Demodulation processing circuits 9 and 20 respectively demodulate the reproduced signals; 22 and 23 demodulation processing circuits 16 and 18;
The time axis of the demodulated signal is corrected and the PV
a' and PVb'; 12 is an addition circuit that adds the time-axis corrected PVa' and PVb' to generate the reproduced channel sum signal PCA; 14 is the time-axis corrected PVa; 10 is a level inversion circuit that performs level conversion on PCS' with the inverse characteristics of the level conversion circuit 9 to convert it into PCS, and 6 is a reproduction channel sum signal PCA. an addition circuit that performs addition processing with a reproduced channel difference signal PCS whose level has been inversely converted and outputs a reproduced A channel signal PVa;
8 is a subtraction circuit that subtracts the reproduced channel sum signal PCA and the reproduced channel difference signal PCS whose level has been inversely converted, and outputs the reproduced B channel signal PVb; A channel synthesis circuit 2 synthesizes and generates a reproduced video signal PV, and 2 is an output terminal for the channel-combined reproduced video signal PV.

The embodiment whose block diagram is shown in FIG. 8 has the configuration of the embodiment shown in FIG. 5 with synchronization signal adding circuits 30 and 31 added, and the other configurations are the same as the embodiment shown in FIG. . In the channel division circuit 3, only the effective area excluding the blanking period of the input video signal is subjected to channel division processing, and is outputted as an A channel signal Va and a B channel signal Vb. After this, addition circuits 5 and 11, subtraction circuits 7 and 13, and level conversion circuit 9 are added as in the previous embodiments.
As a result, Va' and Vb' signals with enhanced channel difference components are generated and input to the synchronization signal adding circuits 30 and 31. The synchronization signal adding circuits 30 and 31 add a negative polarity synchronization signal and a burst signal to be used as a time base reference in the reproduction signal processing, modulate the signals, and send them to the magnetic tape 21 via the magnetic heads 19 and 20. Each is recorded. The subsequent reproduction signal processing process is the same as that of the embodiment shown in FIG. 4, a blanking period and a synchronization signal multiplexed during this period are added so as to have the same form as the video signal V input from the terminal 1, and output as a reproduced video signal PV.

By inserting the synchronization signal addition circuits 30 and 31 before the modulation processing circuits 15 and 17, a signal serving as a time axis reference is accurately added, thereby eliminating jitter, skew, etc. that occur during the recording and reproduction process. Time axis errors can be detected with high accuracy, and the accuracy of time axis correction processing in the time axis correction circuits 22 and 23 can be improved. In addition, even if a synchronization signal with a period of 1H or more is added, such as a vertical synchronization signal, the level of this synchronization signal is recorded without being affected by channel difference emphasis, so synchronization separation in playback signal processing is difficult. This has the effect of allowing stable operation.

Also, as in the previous embodiments, the channel division circuit 3, the addition circuits 5 and 11, and the subtraction circuits 7 and 13
When the level conversion circuit 9 is constructed of a digital signal processing circuit, the synchronization signal addition circuits 30 and 31 are also constructed of digital circuits, and after adding a synchronization signal or a burst signal as digital data, the modulation signal is The signal may be configured to be input to the circuits 15 and 17, converted into an analog signal by a D/A conversion circuit provided inside the modulation signal circuits 15 and 17, and subjected to modulation processing. At this time, the synchronization signal addition circuits 30 and 31 write the digital data of the synchronization signal and the burst signal in the ROM in advance, and
The structure may be such that data is sequentially read out from the ROM and added. By adding a synchronization signal or a burst signal as digital data in this manner, it is possible to add a signal serving as a time axis reference with high precision and at a stable level.

Furthermore, when adding the same synchronization signal or burst signal to each channel, the data ROM in which the synchronization signal or burst signal is written may be configured to be shared by each channel. good. By doing so, the number of data ROMs required for each channel can be reduced to one system, and there is an economical effect due to circuit reduction. At this time, the signals of either channel are adjusted so that a predetermined phase between the channels, such as H alignment, is realized on the track pattern formed on the magnetic tape 21 by the magnetic heads 19 and 20. If it is necessary to delay the signal, add the synchronization signal or burst signal in the same phase using a common ROM, and then insert a delay circuit such as a digital memory to delay the signal of one channel. Just configure it.

Although the case where the synchronization signal addition circuits 30 and 31 are added to the embodiment shown in FIG. 5 has been explained here, the luminance signal and the color signal are In the case of time-axis multiplexing and further channel division, the same effect can be obtained by inserting the synchronizing signal adding circuits 30 and 31 before the modulation processing circuits 15 and 17.

[0071] In addition, all the examples shown so far are 1H
A video signal consisting of a luminance signal or a luminance signal and a chrominance signal input during a period of The period may be longer than 2H. That is, by performing channel division processing by removing redundant periods such as horizontal or vertical blanking of an input video signal, it is possible to extend the time axis of the video signal after channel division by an amount corresponding to these redundant periods.

In addition, in all the embodiments shown so far, the input video signal is divided into channels line by line, but the method is not limited to such a dividing method, and it is possible to divide the input video signal into channels by every specific number of pixels or every few lines. Alternatively, channels may be divided for each field or frame. Even with the above division, if the signals of each channel are signals from close locations on the screen, the amplitude of the channel difference signal will be distributed at a relatively small level due to the correlation of the images, so the channel difference signal Even when the level is emphasized using non-linear characteristics, the channel difference signal can be effectively emphasized, and the same effect as in the embodiment can be obtained.

[0073]

Effects of the Invention According to the present invention, the difference between each transmission signal that is divided into a plurality of parts and transmitted is emphasized and transmitted, and when combining video signals from each transmission path, each transmission signal By processing to compress the difference between the transmission lines, it is possible to reduce the influence of fluctuations in the difference between the transmission lines due to variations in linearity, gain, DC characteristics, etc. This has the effect of reducing image quality deterioration such as line flicker and line pairing.

[0074] Furthermore, when the difference between the transmission signals is small, the degree of emphasis is increased, and when the difference is small, the degree of emphasis is decreased.
It is possible to effectively emphasize the difference in the transmission signal without an extreme increase in the amplitude of the transmission signal, and reduce the influence of fluctuations in the difference between the transmission paths due to variations in the linearity, gain, DC characteristics, etc. of the transmission path. This has the effect of reducing image quality deterioration such as line flicker and line pairing caused by differences in transmission path characteristics.

Furthermore, when combining video signals from each transmission path, the reproduced signal is processed to correct the time axis and then the differences between the respective transmission signals are compressed. This has the effect of successfully reducing the influence of fluctuations in differences between transmission paths without being affected by time axis errors caused by transmission.

Furthermore, when the present invention is applied to a magnetic recording/reproducing device that multiplexes a luminance signal and a chrominance signal on the time axis and records and transmits the divided signals over a plurality of transmission paths, the luminance signal and the chrominance signal The image quality deterioration such as line flicker and line pairing caused by differences in transmission path characteristics that occur in both
It can be reduced simultaneously with one circuit, and there is an economical effect by reducing the circuit scale.

Furthermore, when combining video signals from each transmission path, the process of compressing the difference between the respective transmission signals operates to average the signals from each transmission path. It also has the side effect of reducing noise components independently superimposed on the road.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of the channel division circuit 3 shown in FIG. 1.

3 is a characteristic diagram illustrating the operation of the level conversion circuit 9 shown in FIG. 1. FIG.

4 is a characteristic diagram illustrating the operation of the level inversion circuit 10 shown in FIG. 1. FIG.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing still another embodiment of the present invention.

7 is a waveform diagram showing an output waveform of the channel division circuit 3 shown in FIG. 6. FIG.

FIG. 8 is a block diagram showing still another embodiment of the present invention.

[Explanation of symbols]

3...Channel division circuit, 4...Channel synthesis circuit, 5, 6, 11, 12...addition circuit, 7, 8, 13, 14...subtraction circuit, 9...Level conversion circuit, 10...Level inversion circuit, 15, 17...modulation processing circuit, 16, 18... demodulation processing circuit, 19, 20...magnetic head, 21...magnetic tape, 22, 23...time axis correction circuit, 28...color signal line sequential circuit, 29...color signal interpolation circuit, 30, 31...Synchronization signal addition circuit.

Claims (13)

[Claims] Claim 1: A video signal processing device for processing a video signal as two or more N channel signals, comprising:
means for generating a channel sum signal based on the level sum of the N channel signals; means for generating a channel difference signal based on the level difference of the N channel signals; and means for emphasizing the level of the channel difference signal; A video signal processing device comprising: means for generating N transmission signals with enhanced channel difference components from the level-enhanced channel difference signal and the channel sum signal. 2. The means for emphasizing the level of the channel difference signal is non-linear level converting means such that the gain becomes 1 or more when the amplitude of the channel difference signal is lower than a predetermined level. The video signal processing device according to claim 1, having a configuration including the following. 3. A video signal processing device that processes a video signal as two or more N channel signals, wherein the N
means for generating a channel sum signal based on the level sum of the N channel signals; means for generating a channel difference signal based on the level difference of the N channel signals; means for converting into a difference signal; and means for generating N output channel signals from the compressed channel difference signal and the channel sum signal;
A video signal processing device comprising: 4. The means for converting into a compressed channel difference signal includes nonlinear level converting means such that the gain becomes 1 or less when the amplitude of the channel difference signal is lower than a predetermined level; 4. The video signal processing device according to claim 3, having a configuration including: 5. A video signal processing device that processes a video signal as two or more N channel signals, wherein the N
signal demodulation means for demodulating each of the channel signals;
means for generating a channel sum signal based on the level sum of the N demodulated signals; means for generating a channel difference signal based on the level difference of the N demodulated signals; compressing the level of the channel difference signal; A video signal processing device comprising: means for converting into a compressed channel difference signal; and means for generating N output channel signals from the compressed channel difference signal and the channel sum signal. 6. The video signal processing according to claim 5, wherein the signal demodulation means includes means for correcting time axis errors for each of N channels based on the time axis reference signal. Device. 7. A video signal processing device that processes a video signal as two or more N channel signals, wherein a first channel sum signal is generated based on a level sum of the first N channel signals. means for generating a first channel difference signal based on the level difference of the first N channel signals; means for emphasizing the level of the first channel difference signal; means for generating N transmission signals with enhanced channel difference components from the first channel difference signal and the first channel sum signal; means for generating a channel sum signal; means for generating a second channel difference signal based on the level difference of the second N channel signals; compressing the level of the second channel difference signal; A video signal processing device comprising: means for converting into a difference signal; and means for generating N output channel signals from the compressed channel difference signal and the second channel sum signal. 8. The means for emphasizing the level of the first channel difference signal has a gain of 1 or more when the amplitude of the first channel difference signal is lower than a predetermined level. 8. The video signal according to claim 7, wherein the video signal includes nonlinear level conversion means, and the means for converting into the compressed channel difference signal includes level inverse conversion means having a conversion characteristic that is an inverse function of the nonlinear level conversion characteristic. processing equipment. 9. A video signal processing device that processes a video signal as two or more N channel signals, wherein a first channel sum signal is generated based on a level sum of the first N channel signals. means for generating a first channel difference signal based on the level difference of the first N channel signals; means for emphasizing the level of the first channel difference signal; means for generating N transmission signals with enhanced channel difference components from the first channel difference signal and the first channel sum signal; signal conversion means for modulating each of the N transmission signals; 2 N
signal demodulation means for demodulating each of the channel signals;
means for generating a second channel sum signal based on the level sum of the N demodulated signals; means for generating a second channel difference signal based on the level difference of the N demodulated signals; A means for compressing the level of a channel difference signal and converting it into a compressed channel difference signal, and a means for generating N output channel signals from the compressed channel difference signal and the second channel sum signal. A video signal processing device characterized by: 10. The means for emphasizing the level of the first channel difference signal has a gain of 1 or more when the amplitude of the first channel difference signal is lower than a predetermined level. 10. The video signal according to claim 9, wherein the video signal includes nonlinear level conversion means, and the means for converting into the compressed channel difference signal includes level inverse conversion means having a conversion characteristic that is an inverse function of the nonlinear level conversion characteristic. processing equipment. 11. The signal demodulation means according to claim 9 or 10, wherein the signal demodulation means includes means for correcting time axis errors for each of N channels based on the time axis reference signal. Video signal processing device. 12. The video signal according to claim 7, wherein the first and second N channel signals are signals based on a luminance signal, a first color signal, and a second color signal, respectively. processing equipment. 13. The video signal processing according to claim 9, wherein the first and second N channel signals are signals based on a luminance signal, a first color signal, and a second color signal, respectively. Device.