JPS59117887A - Correcting circuit of video signal - Google Patents

Abstract

PURPOSE:To prevent the generation of a virtual signal when the line correlation of a color difference signal is disturbed by correcting a video signal where only an amplitude at a 1H is different from an amplitude before and after 1H close to the original video signal. CONSTITUTION:Reproduced color difference signals R-Y and B-Y extracted for time matching are applied respectively correcting circuits 17, 18 from a recording and reproducing device 16 for the purpose of correction, then a color difference before 2H is extracted at time t1. Further, a color difference signal at 5H adjacent to the virtual signal is extracted at time t2. Since this signal is replaced to the color difference after 1H of the color difference signal at high level, it cannot be a correct signal, but the signal is the same as a color of background in the reproducing screen, and the difference is not so much remarkable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal correction circuit, and in particular to an adder and a combination of two color difference signals. The present invention relates to a correction circuit that replaces and corrects a pseudo video signal (pseudo signal) at a level different from that of a video signal with a video signal at a correct level.

BACKGROUND OF THE INVENTION The applicant of the present invention previously proposed a block system recording and reproducing system as shown in FIG. In the same figure, input terminal 1
and 2 have a color difference of, for example, 1 m @RY and B-Y, respectively.
comes in. The color difference signal RY is input to one input 1 of the adder 3.
Supplied directly to the terminal. The color difference signal B-Y is sent to the polarity inverter 4.
and a switch 5, J: is inverted (supplied to the other input terminal of the adder 3) every horizontal opening period (11-1). Therefore, the color difference input to the input terminal 1 For example, the signal R-Y is schematically shown in FIG. 2 (△), and the color difference signal B-Y input to terminal 2 is schematically shown in FIG. and the output signal of switch 5 is 1.
The output signal of the adder 3 becomes as schematically shown in Fig. 61 <C>, and the output signal of the adder 3 becomes as not schematically shown in Fig. 61 (D).

The combined signal taken out from the adder 3 is modulated by a modulator 6 into a signal form suitable for recording and reproduction, and then recorded on a recording medium 7 by a known recording means (not shown). Note that the luminance signal is recorded on this recording medium 7, for example, on another track.

The recording medium 7 is reproduced by a known reproduction converter (not shown), and the reproduced signal is demodulated by a demodulator 8 and then supplied to a 1H delay circuit 9. At the same time, an adder 10 and a subtracter 1
1 to each one input terminal. The demodulated signals extracted by the 11-1 delay circuit 9 and delayed by 11'' are supplied to the other input terminals of the adder 10 and the subtracter 11, respectively. Here, since the input demodulated signal of the 11-1 delay circuit 9 has the same waveform as the output addition composite signal of the adder 3 schematically shown in FIG. 2(D), 1]] the output of the delay circuit 9 The signal will be as shown in the figure ([). Therefore, adder 10
A signal having a waveform schematically shown in FIG. 2(F) is extracted from the output terminal 1, and this signal is outputted to the output terminal 14 as a reproduced signal of the color difference signal 1'm-Y.

On the other hand, since the subtracter 11 performs the operation of subtracting the output signal of the demodulator 8 from the output signal of the 1-to-I delay circuit 9, a signal having the waveform schematically shown in FIG. 2(G) is extracted from the subtracter 11. It will be done. The output signal of this subtracter 11 is transmitted to a polarity inverter 12.
After the polarity is inverted at , the voltage is applied to one contact of the switch 1', and at the same time, it is directly applied to the other contact of the switch 13.

Since the switch 13 is configured to be switched every 11" like the switch 5, a signal having a waveform schematically shown in Fig. 2, Part 1) is extracted from the switch 13, and this signal is the color difference signal B. -Y is outputted to the output terminal 15 as a reproduced signal. Note that the amplitude of the output reproduced color difference IL@ of the output terminal 1/1.15 is the same as the amplitude of the input color left signal of the input terminal 1.2, so if necessary, a subsequent attenuator (not shown) may be used. ), the amplitude is attenuated to 1/2.

In this way, according to the recording and reproducing method proposed by the present applicant mentioned above, the color information between the color difference signals R-Y and B-Yl and the adjacent horizontal openings 1y'JIIJJ are close to each other. By utilizing this property (line correlation), we have the advantage of being able to transmit two color difference signals in the same band over a single transmission path in a narrow band.

Problems to be Solved by the Invention However, in the recording/reproducing system 15 proposed by the applicant, if the line correlation of the color difference signals input to the input terminals 1 and 2 collapses, for example, as shown in FIG. △) When the amplitude of the input color difference signal R-Y changes from rOJ to 61-0.3J at a3, and when it changes from ``Q, 3J to ``O'', and when the amplitude of the input color difference signal R-Y changes from rOJ to 61-0.3J, and when the amplitude changes from ``Q, 3J to ``O'', and when there is a person not shown in Fig. 2 (B), When the amplitude of the J color difference signal B-Y changes from "0" to "rl, 0", and from "OJ" to "rOJ", the reproduction signal output terminal 14. ．． 15, as shown by the circle /υ in Figure 2 (F), a signal (under JX, this is called a pseudo f, ffi signal) with an amplitude different from that of the recorded signal waveform is generated. There was a problem with this.

Therefore, it is an object of the present invention to solve the above-mentioned problems by replacing the above-mentioned pseudo signal with a signal of correct amplitude, and to provide an Ic video signal correction circuit.

Means for Solving the Problems The present invention provides a second video signal for the video signal of the camera 1.
The polarity is inverted and synthesized for every 1-1, and this added composite signal is supplied via a transmission line and is combined with the output delay signal of the first delay circuit and the output delay signal of the first delay circuit. A signal obtained by adding and synthesizing the input signals respectively is extracted at the reproduction output of the first video signal, and a signal obtained by subtracting the input horn signal and the output delayed signal of the first delay circuit, respectively. a circuit separately connected to each of the first and second video signal reproduction outputs of the device for extracting the second video signal as a reproduction output, and connecting the circuit to the reproduction output terminal. The second and third delay circuits connected in series with a delay time of 1H are compared in level with the input signal and output signal of the second and third delay circuits, respectively, and the level of both signals is approximately equal. Gi is the first level, mismatched Nodoki (J 2nd 1 novel 1st. 2nd
first and second comparison discrimination circuits that output a comparison discrimination signal of At least a delayed comparison identification signal generating circuit is supplied with the first to fourth comparison identification signals, and only the second comparison identification signal is at the second level. generating a switching signal, a second switching signal when the first and third comparison identification signals are at the second level and the second and third comparison identification signals are at the first level; and a switching signal generation circuit that generates a third switching signal at other times, and selectively outputs an output signal of the third delay circuit when the first switching signal is supplied; When the second switching signal is supplied, the input horn signal of the second delay circuit is selectively output, and when the third switching signal is supplied, the output signal of the second delay circuit is selectively output. Each of the embodiments will be described below with reference to FIG. 3 and the subsequent drawings.

Embodiment First, the method of generating the +Vi pseudo signal will be explained. Input terminals 1 and 2 have values sampled at 111 intervals as shown in Figure 3. ) is input, and when this input signal is low level, it is represented by a circle, and when it is high level, it is represented by a Δ mark. As shown in the second column, the output signal of the 11-1 delay circuit 9 can be represented by ○ and △ shapes. Therefore, the output signal of the 11-1 delay circuit 9 is
The output signal of the adder 10 is as shown in the bottom layer of the figure. That is, as can be seen from FIG. 2(F), the output signal of the adder 10 generates a pseudo signal during the period t11-1, indicated by the X mark in FIG. As shown in FIG. 3, the input signal at the same time and the output signal of the IIN extension circuit 9 are compared, and if they have the same figure, a signal representing the figure C is reproduced and outputted to the output terminal of the adder 10. Otherwise, a pseudo signal is reproduced and output.

FIG. 4 is a diagram showing output signals of the adder 10 corresponding to input low waveforms of various input terminals 1 and 2 according to the notation method shown in FIG. Here, in the mouth, both the ◯ mark and the Δ mark indicate different levels. The output signal of the mourner 10, which is λ-j in response to the input signal in the left column of FIG. J-1ft similar signal generation position is different 1,
The following points can be seen from Figure 4. ■The value obtained by sampling the input video signal (color difference signal here) at IH intervals is 2
Input video (Kl) at the same level more than once (21-1 or more)
In a video signal or a video signal that is a combination thereof, a reproduced video signal having the same amplitude as the recorded video signal is always correctly reproduced 11 to 1 period after the pseudo signal is generated.

■When the value obtained by sampling the input video signal at an interval of 11-1 is 1 time < 11-1), another pseudo signal is generated after the pseudo signal, as shown in the bottom column of Figure 4. do.

In other words, for input video signals that are at the same level at least two eye intervals or a video signal that is a combination thereof, J3
When the correlation between adjacent horizontal scanning periods collapses, there is always a correlation between the signals of the next adjacent horizontal scanning period, so that a correct signal is always reproduced after the pseudo signal is generated.

Also, 1 numbering value at 111 intervals is once (if the values are different), the correlation between the video signals between adjacent 1 and 1 has collapsed, and the correlation between the video signals of the next 1 day is also different. As a result, a pseudo signal is generated after the pseudo signal.

The present invention is mainly a circuit for correcting the pseudo signal in the case (2) above, and FIG. 5 shows a block diagram of an embodiment of the circuit of the present invention. The recording/reproducing device 16 includes a recording/reproducing system for color difference signals as shown in FIG.
For example, the luminance signal is recorded on a track different from the color difference signal recording 1 to the rack, and a luminance signal recording/reproducing system for reproducing the luminance signal is also provided. After the level of R-Y is adjusted as necessary, it is supplied to the correction circuit 17 of one embodiment of the circuit of the present invention, and the reproduced color difference signal B-Y taken out from the output terminal 15J is level-adjusted as necessary. After that, the reproduced luminance signal is supplied to a compensation circuit 18 having the same configuration as the compensation circuit 17, and the reproduced luminance signal is further supplied to the compensation circuit 11-1.
If! is supplied to the extension circuit 19, and the correction circuits 17 and 18.
The signal is output to the output terminal 20 after being delayed by 111 times due to the time difference between the output color difference signal and the output color difference signal.

On the other hand, the reproduced color difference signal R-Y taken out from the recording/reproducing device @16 is sent to the 1 to 1 which is connected in cascade in two stages in the correction circuit 17.
The signal is sequentially supplied to the delay circuits 21 and 22, and is also supplied to a terminal a of a comparison/discrimination circuit 23 and a switch circuit 34, which will be described later. The comparison/discrimination circuit 23 compares the levels of the input color difference signal R-Y of the 11-IM extension circuit 21 with the IHW extended output color difference signal R-Y, and if the low levels of the two substantially match, it is a high level, indicating a mismatch. When , the first comparison identification signal (1 signal) at a low level is output. Further, the comparison discrimination circuit 24 outputs the color difference signal R-Y which has been delayed by 1)-1 by the 11-1 delay circuit 21 and the color difference signal R-Y extracted from the 11-1 delay circuit 22.
A total of 21-1 delayed color difference signals R-Y extracted from
and a second comparison identification signal obtained by operating in the same manner as the comparison identification circuit 23 is supplied to the second comparison identification signal 11 which is connected in cascade in two stages.
-1 output to delay circuits 25 and 26. This results in 1
From the H delay circuit 25, a third comparison identification signal is obtained by delaying the second comparison identification signal by 114, and from the 1-to-1 delay circuit 26, a fourth comparison identification signal is obtained by delaying the second comparison identification signal by 21-1. A comparison identification signal is extracted.

The four-man power NOR circuit 29 is the first. The polarity is inverted by the third comparison identification signal and the inverters 27 and 28, and the second. and a fourth comparison identification signal, respectively.

Also, at the same time, the four-man power NOR circuit 33
and a fourth comparison identification signal is output from inverters 30, 31 and 3.
2, and the second comparison identification signal is directly supplied. These inverters 27,2
8.30 to 32 and the NOR circuits 29 and 33 constitute a switching signal generation circuit, and the output signal of the NOR circuit 29 controls switching of the switch circuit 34,
The output color 8 of the NOR circuit 33 controls the switching of the switch circuit 35.

Here, when the output signal of the NOR circuit 29 is at a high level, the switch circuit 34 is connected to the terminal a to receive the output color difference signal of the recording/reproducing device 16 (that is, the 11-1 force spreading circuit 21
The input color difference signal (R-Y) is selectively outputted to the terminal of the switch circuit 35, and when the two output signals of the NOR circuit are at low level, it is switched and connected to the terminal (11) and the output color difference signal R- of the delay circuit 21 is output. Selectively output Y to the terminal of the switch circuit 35.

Further, when the output signal of the NOR circuit 33 is at a high level, the switch circuit 35 is connected to the terminal a and selectively outputs the output color difference signal R-Y of the 1)-1 delay circuit 22 to the output terminal 36. When the output signal is at a low level, it is connected to the terminal S and the output color difference signal R-Y of the switch circuit 34 is output.
is selectively output to output terminal 3G.

As a result, the color difference signal RY with one pseudo signal corrected is outputted to the above-mentioned output terminal 36. vinegar"
That is, as shown at the top of FIG. 6, the waveform of the color difference signals R-Y and B-Y to be recorded by the recording/reproducing device 16 is at a high level for a period of 1l1, as shown at the top of FIG. In other words, if the signal input is illustrated using the same notation as in FIG. 3, it will be as shown in the signal input column of FIG. 6. Here, the ○ mark indicates a low level and the Δ mark indicates a high level, which is the same as in Figure 3, but in Figure 6, a 1" number is further written to indicate the order of H between the ○ mark and the Δ mark. When this signal is input, the output signal of the delay circuit 9 shown in FIG. Output terminal 1
The signal taken out from 4 and supplied to the 11-1 delay circuit 21 in the correction circuit 17 is 3 as shown graphically in the figure.
A pseudo signal is generated at the fourth point 14.

Therefore, the input signal and the output signal of the one-day delay circuit 22 are graphically illustrated in FIG. 23
, 24, 1l1 The first to fourth comparison identification signals taken out from the delay circuits 25 and 2G are "correct" or "incorrect" as shown in FIG. In the figure, 1-Correct indicates that the comparison result is correct, and therefore the next comparison identification signal 1 (is at a high level), while ``Error'' indicates that the comparison result is incorrect. Therefore, the comparison identification signal at the time is 1"-level. Here (...
, NOl and the circuit 29 is connected to the first . The third comparison identification signal is 1
- level, and the second. Only when the fourth comparison identification signal is at a high level, the circuit 23 shown in FIG.
．． 24. It outputs a high level signal B only when the outputs of 25 and 26 are 1 error, and outputs a low level signal (,,H'?i) at other times.

On the other hand, the NOR circuit 33 is connected to the first . Only when the third and fourth comparison identification signals are at high level and the second comparison identification signal is at low level, the circuits 23, 24, 25 and 2G shown in FIG. It outputs a high-level signal only when the output is 1 (correct, false, correct, correct), and outputs a low-level signal at other times.

Therefore, the input color difference signal R-Y of the delay circuit 21 is the first 21-1 shown by ■, ■ in FIG.
The outputs of 25 and 26 are "correct, correct, correct, correct", and the next 1 to 1 receives a pseudo signal, but this time it is "false, correct, correct", so the outputs of NOR circuits 29 and 33 are Each output J signal becomes a low level as shown by "L" in FIG. Therefore, since the switch circuits 34 and 35 are connected to the terminals of the first 3H, the output color difference signal R-Y of the 11-1 delay circuit 21 passes through the switch circuits 34 and 35, respectively.
C output terminal 36/\ is output. As a result, the corrected output signal of the output terminal 36 is as shown graphically in FIG.
When the low level signal of the second 1'' enters the first delay circuit 21, the correct color difference signal of the low level of the first 1'' is taken out, as shown by ■, and the pseudo signal is input after the next 1H. When it comes, it is indicated by ■ and the correct color 1 of the I-level of the second 1 (No. 2 is taken out.

Then, at time t1 after the next 1 to 1, the pseudo signal enters the 11-1 delay circuit 21 again, but the circuits 23, 24.
Since the outputs of 25 and 26 are "correct, incorrect, correct, correct" as shown in FIG. 6, the output signal of the N'OR circuit 29 is at the 1-1- level, and the output signal of the NOR circuit 33 is at the high level. , a switch circuit 35 is switched and connected to the terminal a side. As a result, at this time t1, the 11-1 delay circuit 22
The 21'' delayed color difference signal extracted from the 21'' delayed color difference signal, that is, the low level color difference signal RY shown by ■ in FIG. 6, is outputted to the output terminal 36 through the switch circuit 35. That is, at this time t1, the color difference signal R, which is originally indicated by ■, is at a low level.
-Y should be output, but if the output signal of the 1HN extension circuit 21 is outputted as is to the output terminal 36, the 1 pseudo signal 1H before will be output, so 2
By replacing the color difference signal RY before H with the color difference signal RY, a color difference signal having the same amplitude as ① is extracted.

At time t2, which is 111 times after time t1, the 5th H color difference signal R-Y enters the 11'' delay circuit 21, and the 5th H color difference signal R-Y is input to each output terminal of the 11'' delay circuit 21 and 22. Since pseudo signals are taken out respectively, the circuits 23, 24 and 25
As shown in FIG. 6, the outputs of the circuits 26 and 26 are "false correct/false correct", so that the NOR circuit 29 outputs a high level signal and the NOR circuit 33 outputs a low level signal. As a result, the switch circuit 34 is switched and connected to the terminal a, and the switch circuit 35 is switched and connected to the terminal A.
The color difference signal RY serving as the input signal passes through the switch circuits 34 and 35, respectively, and is outputted to the output terminal 3G. As a result, at time t2, each of the output signals of the 1-1 delay circuits 21 and 22 becomes a pseudo signal, so instead of these signals, the signals shown by ■ in FIG. The J5th low-level color difference signals 1 to 4 are outputted as correction output signals from the output terminal 36.

Note that at time t2, the high-level color difference signal of the 4th 11th color difference signal indicated by MU should be output, but in this embodiment, the 5th color difference signal next to the pseudo signal 11-1 indicated by ▪ should be output. Since the low-level color difference signal of 1" is output, in a strict sense it does not mean that the original 11-1 minute color difference signal has been reproduced, and it cannot be said that it is a correct signal, but the original Since the color after 11-1 of the color difference signal is replaced with
It can be made less noticeable.

After time 111 after time 12, since there is a correlation between adjacent 11-1, the NOR circuits 29 and 33 each output a low level signal, and the output terminal 36 receives a signal as shown in FIG. <The output color difference signals of the IH delay circuit 21 are taken out in descending order.

The color difference signal B-Y reproduced and output from the recording and reproducing device 1G is transmitted to a correction circuit 1ε and 11a having the same configuration as the correction circuit 17.
The same correction as described above is performed and the result is output to the output 9Mf 37.

In addition, 3rd. The circuit that generates the fourth comparison identification signal is
A block system configuration shown in FIG. 7 may also be used. In the figure, the same component parts as those in FIG. In FIG. 7, 1t-fi! ¥ extension circuit 2
Further, 1-day delay circuits 40 and 41 are connected to the output terminals of J5, and the comparison and identification circuits 42 and 43 compare the levels of the input color difference signal and the output color difference signal of the delay circuits 40 and 41. When the two signal levels substantially match, a high level signal is output, and when they do not match, a low level signal is output to the output terminals 44 and 45. Therefore, the low value outputted to the -C output terminal 44 is output from the comparison discrimination circuit 24J to the output horn terminal 4.
It is the same as the third comparison identification signal obtained by delaying the second comparison identification signal 2 outputted to 1, and is also the same as the third comparison identification signal obtained by delaying the second comparison identification signal 2 which is output to the comparison product circuit /! The signal outputted from output terminal 3 to output terminal /1.5 is the same as the fourth comparison identification signal obtained by delaying the second comparison identification signal by two days. Output terminal 40, 4
．． 1, 4.4 and 45, J, the first . Second. The third and fourth comparison identification signals are converted into switching signals by a circuit similar to that shown in FIG. 5 to control the switching of the -C switch circuits 34 and '35.

Note that the signal for correction may be a video signal, and therefore the present invention can be applied to primary color signals in addition to color difference signals.

Effects As described above, according to the present invention, the spurious signals 2) occurring in the reproduction signal of the recording and reproduction method previously proposed by the applicant can be reduced by 1.
By using a 1-1 delay circuit or the like, it is possible to replace the signal with the correct signal, and in particular, it is possible to correct a video signal in which only the amplitude of 111 is similar to the amplitude after 11-1 to be close to the original video signal. It has the following features.

[Brief Description of the Drawings] Fig. 1 is a block system diagram showing an example of a recording/reproducing system that the present applicant has previously conceived, and Fig. 2 (A) to (+-1> are blocks shown in Fig. 1, respectively). Figure 3 is a diagram schematically showing the signals of each part to explain the operation of the system, and Figure 2 (A) shows the generation position of the pseudo signal. A graphical representation of the signal
1 and 5 are block system diagrams showing one embodiment of the circuit of the present invention, and FIG. A diagram for explaining the signals of each part of the illustrated block system, and FIG. 7 is a block system diagram showing another embodiment of the main part of the circuit of the present invention. 1.2...Input terminal, 9, 19, 21, 22°25.
26.40.41...11-1 delay circuit, 14°15
...Output terminal, 16...Recording and reproducing device, 17, 18
... Correction circuit, 23.24, 42.43 ... Comparison identification circuit, 34.35 ... Switch circuit, 36.37.
...Color difference signal output terminal. Figure 1 Figure 3 Figure 2

Claims (3)

[Claims] (1) The polarity of the second video signal is inverted and added to the first video signal every horizontal synchronization period (1 day), and this addition and combination signal is supplied via the transmission line and combined into 1 A signal obtained by adding and synthesizing the output delay signal of the first delay circuit and the input signal of the first delay circuit, which is delayed by a day, is taken out as the reproduction output of the first video signal. The reproduction output of the first and second video signals of the device that takes out the signals obtained by subtracting the input signal and the output delay signal of the first delay circuit as the reproduction output of the second video signal. second and third delay circuits each having a delay time of 11-1, which are circuits connected to each of the terminals separately, and which are cascade-connected to the playback output terminal, and the second and third delay circuits each having a delay time of 11-1. The input signal and the output signal of the third delay circuit are compared in level, and when the levels of both signals substantially match, it is the first level, and when they do not match, the first level is the second level. A first comparison discrimination circuit outputting a second comparison discrimination signal, a third comparison discrimination signal 11" before the second comparison discrimination circuit, and a fourth comparison discrimination signal 2H before the second comparison discrimination circuit. a comparison identification signal generation circuit that obtains at least the first
to fourth comparison identification signals are supplied, of which the second
When only the comparison identification signal of is at the second level, the first
generating a second switching signal when the first and third comparison identification signals are at the second level and the second and fourth comparison identification signals are at the first level; and a switching signal generating circuit which generates a third switching signal at other times, and an output (No. 8) of the third D extension circuit when the first switching signal is supplied. When the second switching signal is supplied, the input signal of the second delay circuit is selected and output, and when the third switching signal is supplied, the input signal of the second delay circuit is selectively output. A video signal correction circuit characterized by comprising a group of switch circuits for selecting output signals. (2) The comparison identification signal generation circuit converts the second comparison identification signal extracted from the second comparison identification circuit into 11-
1 delay circuit, and the third ratio taken out from the fourth delay circuit ((☆ A fifth delay circuit that delays the identification signal by 114 and outputs No. 1 to the fourth comparison identification signal). 2. The video signal correction circuit according to claim 1, characterized in that it comprises an i-works extension circuit. (3) The comparison identification signal generating circuit includes fourth and fifth delay circuits having a delay time 111 connected in cascade to the output terminal of the third delay circuit, and the fourth and fifth delay circuits having a delay time 111 connected in series to the output terminal of the third delay circuit. Input h of the fifth delay circuit
When the levels of @ and the output signal are compared respectively, and the levels of both signals almost match, the first level is used, and when they do not match, the second level is used.
The third level of The third. which outputs the fourth comparison identification signal. 2. The video signal correction circuit according to claim 1, further comprising a fourth comparison and discrimination circuit.