JPH03259694A - Picture signal recording device - Google Patents

Abstract

PURPOSE:To prevent a deteriorated picture signal from being recorded by providing an inhibit means inhibiting a color difference line sequential signal subjected to FM modulation outputted from an FM modulation means from being given to a multiplex means when the sequence of color difference signals in color difference line sequential signals is discriminated by a discrimination means so as not to be normal. CONSTITUTION:A switch 10 is switched on/off according to the result of discrimination represented by a CID signal 33, and only when the switch 10 is closed, the output of a color difference FM modulator 9 is fed top an adder 11 via the switch 10 and added to the output of a luminance FM modulator 8 and an ID modulation circuit 12 and the added signal is outputted. Moreover, when the switch 10 is opened, since the output of the color difference FM modulator 9 is not fed to the adder 11, a luminance signal other than the color difference line sequential signal and the ID signal are subjected to frequency multiplex by the adder 11 and the result is recorded on a magnetic disk 18. Thus, it is discriminated that the sequence of R-Y, B-Y signals is not normal, the input of a black/white picture signal is displayed and the recording of the color difference line sequential FM signal is inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image signal recording device for recording an image signal, and particularly to an image signal recording device that records an image signal by inputting an image signal composed of a luminance signal and a color difference line sequential signal. The present invention relates to an image signal recording device that records the image signal on a recording medium such as a magnetic disk.

[Prior Art] As an image signal recording/reproducing apparatus, for example, a still video recording/reproducing apparatus is conventionally known. A conventional still video playback device is configured as shown in FIG. 8, for example. In this reproducing device, an image signal recorded on a magnetic disk 51 is reproduced by a magnetic head 52, 53,
After being amplified by preamplifiers 54 and 55, it passes through a head switch 56 to a luminance FM demodulation circuit 57 and a color difference FM demodulation circuit 5.
8, input to the ID demodulation circuit 59. And brightness FM
The FM demodulated signals sent to the demodulation circuit 57 are sent to the luminance processing circuit 60.
, are input to the color difference processing circuit 61. In the case of frame reproduction using image signals recorded on two tracks on the magnetic disk 51, the brightness processing circuit 6
0 outputs the input luminance signal to the video output circuit 62 without performing interpolation processing or skew compensation, and the color difference processing circuit 61 synchronizes the input color difference line sequential signal to generate the R-Y signal. and the B-Y signal to the video output circuit 62.

On the other hand, in the case of field reproduction using an image signal recorded on one track on the magnetic disk 51, in addition to the processing performed in frame reproduction, the luminance processing circuit 60 and the color difference processing circuit 61 perform frame interpolation processing and Skew compensation is performed and the signal is output to the video output circuit 62. As a result, the video output circuit 62 outputs a composite video signal (commonly known as S output) based on the NTSC system or PAL system from the input luminance (Y), R-Y, and B-Y signals as necessary. It forms the so-called luminance, chroma separation output signals, RGB signals, etc., and outputs them to the image output terminal 6.
Output from 3.

On the other hand, the signals demodulated by the luminance FM demodulation circuit 57 and the bypass circuit 58 are respectively input to the luminance process circuit 609 and the color difference process circuit 61, and are also input to the luminance output terminal 64 for dubbing and the sequential eight color difference line terminals 65 for dubbing. is also output. These output terminals 64.6
Since the signal output from 5 is not processed by the luminance processing circuit 60 and the color difference processing circuit 61,
There is no signal deterioration due to deterioration of the S/N ratio or generation of distortion due to interpolation processing or skew compensation. Therefore, if dubbing recording is performed by supplying this signal to the recording device, high-quality dubbing can be achieved compared to the case where dubbing recording is performed using signals processed by the luminance processing circuit 60 and color difference processing circuit 61. Records can be made.

Next, FIG. 9 shows a schematic configuration of a conventional still video recording apparatus that inputs and records a dubbing output signal output from a playback apparatus as shown in FIG.

In FIG. 9, the signals output from the dubbing luminance output terminal 64 and the dubbing color difference line sequential output terminal 65 are respectively inputted from the dubbing luminance input terminal 902 and the dubbing color difference line sequential input terminal 903, The signals are input to dubbing selector switches 905 and 906, respectively. The other input terminal of these switches 905 and 906 receives a signal input from the image input terminal 901 which is converted into a luminance signal and a color difference line sequential signal in a video input circuit 904 and is input thereto. During dubbing recording, switches 905 and 906 are both connected to the dubbing input side, and the outputs of dubbing changeover switches 905 and 906 are FM-modulated by a luminance FM modulator 908 and a color difference FM modulator 909, respectively. The added signal is sent to the adder circuit 9.
11.

The signal added by the adding circuit 911 is sent to the recording amplifier 91.
3. The data is recorded on a magnetic disk 918 by hot heads 916 and 917 via recording gate switches 914 and 915. Note that opening and closing of the recording gate switches 914 and 915 is controlled by a recording control circuit 921, and dubbing recording of image signals onto the magnetic disk 918 is performed.

[Means for Solving the Invention] However, in the conventional recording device described above, when a monochrome reproduced image signal is input during dubbing recording, while a normal dubbing luminance signal is input to the dubbing luminance input terminal 902. , because abnormal signals such as random noise are input to the color difference line sequential input terminal 903 for dubbing,
If you perform dubbing recording using this, unnecessary signals will be recorded, so if you play back the image signal recorded by dubbing in this way, a deteriorated black and white image signal with color noise etc. will be played back. The problem was that it ended up happening.

Furthermore, in order to prevent the deterioration of the monochrome image signal as described above, it is conceivable to remove the connection connected to the dubbing color difference line sequential input terminal 903 when a monochrome reproduced image signal is input during dubbing recording. However, if such a thing is done, the situation will be the same as if the connection of the dubbing color difference line sequential input terminal 903 was disconnected, but the recording device would still be supplied with a black and white reproduced image signal. This has the drawback that the black and white reproduced image signal is not recognized as the color reproduced image signal and is recorded incorrectly.

The present invention has been made in view of the above-mentioned conventional example, and when the input state of the color difference line sequential signal is determined during dubbing recording, and it is determined that the order of R-Y and B-Y of the color difference line sequential signal is not normal. By prohibiting the recording of color difference line sequential FM signals or by recording a predetermined voltage signal, it is possible to prevent the recording of degraded image signals due to recording of unnecessary signals. The purpose of the present invention is to provide an image recording device with a

[Means for Solving the Problems] In order to achieve the above object, the image signal recording device of the present invention has the following configuration. That is, an image signal recording device inputs a luminance signal and a color difference line sequential signal and records the same on a recording medium, the apparatus comprising: FM modulation means for FM modulating each of the luminance signal and the color difference line sequential signal; a determining means for determining the order of color difference signals in the signal;
multiplexing means for multiplexing the luminance signal modulated by the M modulation means and the color difference line sequential signal; and prohibiting means for prohibiting the output FM modulated color difference line sequential signal from being supplied to the multiplexing means.

[Function] In the above configuration, when each of the input luminance signal and color difference line sequential signal is FM modulated and multiplexed and output to the image signal recording section, the order of the color difference signals in the color difference line sequential signal is determined. If it is determined that the order of the color difference signals is not normal, the FM modulated color difference line sequential signal output from the FM modulation means is not multiplexed with the FM modulated luminance signal. As a result, when a monochrome image signal is input or when a color difference line sequential signal is not input for some reason, the color difference line sequential signal is not multiplexed with the luminance signal.
It is possible to prevent unnecessary color noise from being recorded.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of a still video recording apparatus as a first embodiment of the present invention.

In FIG. 1, dubbing signals inputted from a dubbing luminance input terminal 2 and a dubbing color difference line sequential input terminal 3 are inputted to dubbing signal changeover switches 5 and 6, respectively. A signal inputted from the image input terminal 1 is converted into a luminance signal and eight color difference line sequential signals and inputted to the other inputs of the dubbing signal changeover switches 5 and 6, respectively. During dubbing recording, the dubbing signal changeover switches 5 and 6 are both connected to the dubbing input side, and the dubbing luminance signal and the dubbing color difference line sequential signal are selected.

The signals output from the dubbing signal changeover switches 5 and 6 are transmitted to a luminance FM modulator 8 and a color difference FM modulator 9, respectively.
M modulated.

Note that the frequency of the output of the brightness FM modulator 8 is approximately 7 to 9 MHz.
A signal obtained by FM modulating the carrier signal with a luminance signal,
The signal is input to the adder 11 as is. On the other hand, the frequency of the R-Y signal part of the a part of the color difference FM modulator 9 is approximately 1.2 MH.
The B-Y signal portion is a signal FM-modulated by the R-Y signal, which is a carrier signal of Z, and the B-Y signal portion is a signal FM-modulated by the carrier signal-Y signal, which has a frequency of approximately 1.3 MHz. 11.

In this way, the adder 11 frequency-multiplexes the FM-modulated luminance signal and the color difference signal. In addition, the ID modulation circuit 12
In this case, a carrier signal with a frequency of approximately 200KH2 is DP due to the number of ID data in the still video format.
S K (Differential Phase
5ift Keying) modulation to form an ID signal, which is multiplexed with the image signal in an adder 11. Note that this ID data includes the date and a user option code that can be set arbitrarily by the user.

On the other hand, the synchronization separation circuit 7 separates the synchronization signal from the signal output from the changeover switch 5 and inputs it to the ID modulation circuit 12 , recording control circuit 21 , and pulse generation circuit 20 . Further, the CID discrimination circuit 19 discriminates R-Y/B-Y for the color difference line sequential signal outputted from the changeover switch 6. By detecting the offset of the DC voltage at the pedestal portion, the RY signal and the BY signal, which are switched every horizontal scanning period in the color difference line sequential signal, are discriminated.

The pulse generation circuit 20 generates an S/H (sample hold) pulse signal 31 for the R-Y signal portion and an S/H pulse signal 32 for the B-Y signal portion in the color difference line sequential signal, and
The CID discrimination circuit 19 samples the color difference line sequential signals according to these pulse signals and compares the voltage levels of the sampled signals to determine whether the R-Y signal portion or the B-Y signal portion is output to the discrimination circuit 19. determine whether the
The CID signal 33 representing the discrimination result is sent to the pulse generator 2.
0 and the system controller 25.

Here, it is assumed that the CID signal 33 is at a low level when the order of R-Y and BY is normal in a color difference line sequential signal, for example, but becomes a high level when the order is disordered.

The pulse generator 20 also includes HD (horizontal synchronization) pulses,
A VD (vertical synchronization) pulse is output to the system controller 25. The configuration and operation of other parts are explained in the 9th section.
Since the configuration and operation of the parts with the same names as shown in the conventional example shown in the figure are the same, their explanation will be omitted.

FIG. 2 is a flowchart showing the operational processing procedure in the system controller 25. As shown in FIG.

In FIG. 2, first, in step S1, the system controller 25 erases the monochrome image reproduction instruction display provided on the output section 28, and closes the switch 10 in step S2. Next, the process proceeds to step S3, where the register N in the system controller 25 is initialized to "O".

Next, in step S4, it is checked whether dubbing recording is instructed by the operation instruction section 27. If dubbing recording is instructed by the operation instruction section 27, the process proceeds to step S6, but if dubbing recording is not instructed, step S5 is performed. The process ends with the switch 10 closed.

When dubbing recording is instructed, the process advances to step S6, and the selector switches 5 and 6 are connected to the dubbing input (terminal b in the figure). H from the pulse generation circuit 20
If a D (horizontal synchronization) pulse is input, the process advances to step S8, and the signal level of the CID signal 33, which is the output of the CID determination circuit 19, is determined. If the CID signal 33 is at a high level (the order of the color difference signals is out of order), the process proceeds to step S9, where the value of the register N is increased by 1 and N=N+.
Set to 1. On the other hand, if the signal level of the CID signal 33 is low level, the process proceeds to step Sll, and the vertical synchronizing signal VD
Wait for pulse input.

When the value of the register N is incremented by 1 in step S9, the process proceeds to step SIO, where it is determined whether the value is N22. If the value of the register N is "5" or less (N<5), the process advances to step Sll, and it is checked whether a VD (vertical synchronization) pulse has been input.

If the VD pulse is not input, the process returns to step S4 and continues the determination process based on the CID signal 33 described above.

If it is confirmed in step Sll that a VD pulse is input, that is, the next VD pulse is input before the number of errors in the order of R-Y, B-Y reaches "5" during 1 If so, the process advances to step S13, and the monochrome image reproduction instruction display on the output unit 28 remains erased. Then, in step S14, the switch 10 is kept closed, and then in step S15, the register N is initialized to "0", and the process returns to step S4 again to continue the process of determining the CID signal 33.

On the other hand, if it is N22 in step SIO, that is, if the number of errors in the order of R-Y, B-Y reaches "5" during 1■, the process advances to step S16, and the monochrome image signal is input. In step S17, the black and white image reproduction instruction display section provided in the output section 28 is turned on. Then, in step S17, the switch 10 is opened to prevent the color difference line sequential FM signal from being input to the adder 11, thereby preventing recording of the color difference line sequential FM signal. Next, the process proceeds to step 318, and it is determined whether or not a VD pulse has been input from the pulse generator 20. If not, the process returns to step S4, and the above-described process is executed. Further, when a VD pulse is input in step S18, the process proceeds to step S15, where the register N=O is initialized, and the process returns to step S4 again.

Thus, according to this first embodiment, the CID signal 3
According to the determination result indicated by 3, the switch 10 is opened and closed,
Only when the switch 10 is closed, the output of the color difference FM modulator 9 is supplied to the adder 11 via the switch 10;
It is added to the outputs of the brightness FM modulator 8 and the ID modulation circuit 12 and output.

Furthermore, when the switch 10 is open, the output of the color difference FM modulator 9 is not supplied to the adder 11;
1, the luminance signal other than the color difference line sequential signal and the ID signal are frequency multiplexed, and the recording amplifier 13 and head switch 14.1
5, the information is recorded on the magnetic disk 18 by magnetic heads 16 and 17.

In this way, by determining the state of the input color difference line sequential signal, when it is determined that the order of R-Y and B-Y is not normal, it is displayed that a monochrome image signal is being input, By prohibiting the recording of color difference line sequential FM signals, it is possible to prevent an image signal deteriorated due to recording of an unnecessary signal from being recorded.

FIG. 3 is a block diagram showing a schematic configuration of a still video recording apparatus according to a second embodiment of the present invention.

This second embodiment has a constant voltage circuit 29 instead of the switch 10 in the first embodiment. It is composed of a switch 30. That is, as in the first embodiment described above, the state of the input color difference line sequential signal is determined by the CID discrimination circuit 19, and when it is determined that the order of R-Y and B-Y is not normal, the monochrome input image is By determining that a signal is being input and replacing the signal supplied to the color difference FM modulation circuit 9 with a voltage signal having one or two voltage levels generated by the voltage signal generation circuit 29. When performing dubbing recording of a monochrome image signal, it is possible to record the monochrome image signal without producing color noise or the like.

To explain the operation processing procedure in the system controller 25 in this case, in step S17 of FIG. 2, the switch 10 is opened (instead, the switch 30 shown in FIG. 3 is switched to the voltage signal generation circuit 29 (terminal a) side). This can be achieved by

FIG. 5 is a block diagram showing a detailed configuration of a pulse generation circuit and a CID discrimination circuit of a still video recording apparatus according to a third embodiment of the present invention, and FIG. 4 explains the operation of the configuration shown in the third embodiment. FIG. 7 is a timing chart showing the relationship between the color difference line sequential signal and each pulse.

The configuration of the still video recording apparatus of the third embodiment is similar to that of the first embodiment shown in FIG. 1 described above, but the configuration of the CID discrimination circuit 19 and the discrimination operation processing are different.

FIG. 5 is a block diagram showing detailed configurations of the CID discrimination circuit 19 and the pulse generation circuit 20. Hereinafter, a CID determination method different from that of the first embodiment will be explained in detail.

The output of the sync separation circuit 7 (see FIG. 1) is input to a composite sync signal input terminal 101 shown in FIG. 5, and the output of the switch 6 (see FIG. 1) is input to a color difference line sequential signal input terminal 109. On the other hand, the output of the VD generation circuit 117 is input to the system controller 25 via the VD pulse output terminal 118, and the output of the HD generation circuit 102 is input to the system controller 25 via the HD pulse output terminal 119. The output is input to the system controller 25 via the CID discrimination signal output terminal 116.

On the other hand, the composite synchronization signal input from the composite synchronization signal input terminal 101 is transmitted to the HD generation circuit 102. BF generation circuit 103
is also supplied to the HD generation circuit 102. The BF generation circuit 103 and the LSS generation circuit 1 fathom 49 6, 107 form the S/H pulse of the RY signal and the S/H pulse of the BY signal shown in FIG.
The S/H pulse of the signal is input to the S/H circuit 113 for the RY signal, and the S/H pulse of the BY signal is input to the S/H circuit 114 for the BY signal.

As shown in FIG. 5, the color difference line sequential signal input terminal 1
The color difference line sequential signal input from 09 is LPFIIO,
Through DC offset circuits 111 and 112, R
-Y signal S/H circuit 113 and BY signal S/H circuit 114.

As shown in FIG. 7, the DC offset circuits 111 and 112 have a DC level of the color difference line sequential signal that is slightly smaller in the signal output from the DC offset circuit 111 than in the signal output from the DC offset circuit 112. It is configured to apply a bias voltage such that it becomes high (high).

And RY signal S/H circuit 113. Sample and hold (S/H) by S/H circuit 114 for B-Y signal
The detected signals are compared by a comparator 115.

If the output of the S/H circuit 114 for the BY signal is high, the signal is low level, and if the signal output from the S/H circuit 113 for the RY signal is high level, the CID signal 8 is high level. output to the power terminal 116 and the reset pulse generation circuit 108. Then, if the output of the comparator 115 is at a high level, the reset pulse generation circuit 108 outputs a reset pulse to the LS generation circuit 104 and R
-The S/H pulse for the Y signal, the S/H pulse for the B-Y signal, and the color difference line sequential signal input from the color difference line sequential signal input terminal 109 are aligned in phase.

On the other hand, if the order of R-Y and B-Y is normal in the color-difference line sequential signal input to the color-difference line sequential signal input terminal 109, the DC offset circuits 111 and 112 cause the B-Y signal to be has a high DC offset, so after the reset operation by the reset pulse generation circuit 108, the output of the BY signal S/H circuit 114 is R.
The output of the -Y signal S/H circuit 113 is always higher than the output, and the output of the comparator 115 remains at a low level.

Furthermore, when a monochrome image signal is input, the signal input from the color difference line sequential signal input terminal 109 becomes noise, and in this case, the S/H circuit 113 for R-Y signal, the S/H circuit for B-Y signal,
The level of the signal output from the H circuit 114 is not constant, and the comparator 115 repeatedly outputs high level and low level signals. And IV
The above-described determination is made every H (horizontal scanning period) during the vertical scanning period, and if the level of the signal output from the comparator 115 becomes high level for a predetermined number of times or more, the monochrome image signal is It can be determined that the information has been input.

On the other hand, in FIG. 1, the dubbing color difference line sequential input terminal 3
If the connection to is disconnected, there is no signal input to the color difference line sequential signal input terminal 109 in FIG.
The outputs of the R-Y signal S/H circuit 113 and the B-Y signal S/H circuit 114 are stable, even if an abnormality occurs in the signal input to the color difference line sequential signal input terminal 109. Regardless, the level of the signal output from the comparator 115 may remain at a low level.

Therefore, in this embodiment, the DC offset circuit 111,1
12 is the LPFIIO and R-Y signal S/H circuit 113.
It is arranged between the S/H circuit 114 for the B-Y signal, and when the connection to the dubbing color difference line sequential input terminal 3 is disconnected by the DC offset circuits 111 and 112, the S/H circuit for the R-Y signal is Since the signal supplied to the circuit 113 is biased slightly higher than the signal supplied to the S/H circuit 114 for the B-Y signal, the signal output from the S/H circuit 113 for the R-Y signal is higher. The level is slightly higher than the signal output from the BY signal S/H circuit 114. As a result, the output of the comparator 115 remains at a high level.

Then, the above-mentioned determination is made every H (horizontal synchronization) during IV (vertical synchronization), and if the output from the comparator 115 is considerably greater than the number of times it is determined that a monochrome image signal is being input. When the level of the signal becomes high level, it can be determined that the dubbing color difference line sequential input terminal 3 is disconnected.

FIG. 6 is a diagram showing a part of a specific circuit example of the CID discriminating circuit 19 shown in FIG.

As shown in FIG. 6, the signal input from the color difference line sequential input terminal 109 is input to DC offset circuits 111 and 112 via the LPFIIO. and,
The outputs of each DC offset circuit 111 and 112 are the S/H circuit 113 for R-Y signal and the S/H circuit 113 for B-Y signal, respectively.
Each signal input to the circuit 114 and sampled and held is input to a comparator 115. The comparator 115 compares these sampled and held signals, and outputs the comparison result as a CID signal from the CID discrimination signal output terminal 116.

FIG. 4 is a flowchart for explaining the processing operation procedure performed by the system controller 25 upon input of the signal from the CID signal output terminal 116, and the same parts as the flowchart of FIG. 2 are omitted.

When the value of register N becomes "5" or more in step SIO in FIG. Proceeding to step S21, it is further determined whether N≧200. If the value of register N is less than "200", similarly to steps S16 to S18 of the first embodiment,
The processes shown in steps S22 to S24 are performed to continue determining the order of RY and BY in the color difference line sequential signal.

Further, if the value of register N is "200", step S2
Proceeding to step 5, since it is determined that the signal output from the comparator 115 remains at a high level, it is assumed that the connection to the color difference line sequential input terminal 3 is disconnected, and a line disconnection warning display is output. The information is displayed on the display section 28 and the process proceeds to step S24.

Note that the register N set in step SIO and S21
The value of is merely an example, and is not limited to this embodiment, and can be set as appropriate as long as it can achieve the effects of the present invention.

Furthermore, the DC offset circuits 111 and 112 shown in FIG. 5 may be provided in only one of them. Furthermore, if the polarity of the color difference line sequential signal input to the color difference line sequential input terminal 109 is reversed, the DC offset circuit 1
11, 112 polarity and S/H circuit 113 for R-Y signal
and B-Y signal S/H circuit 114 and comparator 115
All you have to do is change the wiring.

Furthermore, when the input color difference line sequential signal is not only used for dubbing recording but also output to other equipment, the order of the R-Y signal and B-Y signal of the color difference line sequential signal must be incorrect. When it is determined, by muting the output of the color difference line sequential signal, it is possible to prevent unnecessary color noise from being output.

As explained above, according to this embodiment, during dubbing recording, the input state of the color difference line sequential signal is determined, and when it is determined that the order of R-Y and B-Y of the color difference line sequential signal is not normal, , it is possible to prohibit multiplexing of the color difference line sequential FM signal onto the luminance FM signal and display that a black and white image signal is being input. This has the effect of preventing unnecessary signals from being recorded.

In addition, a DC offset having a relationship opposite to the DC offset relationship between the R-Y and B-Y signals that is predetermined and added is added to the front stage of the circuit that determines the state of the color difference line sequential signal input. Set up a circuit. By detecting that the relationship between the detected DC offsets has been reversed, it is possible to detect that the connection for inputting the color difference line sequential signal is disconnected, and a line disconnection warning is displayed.
By prohibiting the supply of color difference line sequential FM signals, it is possible to prevent unnecessary signals from being recorded.

[Effects of the Invention] As explained above, according to the present invention, during dubbing recording,
The input state of the color difference line sequential signal is determined, and when it is determined that the order of R-Y and B-Y of the color difference line sequential signal is not normal, recording of the color difference line sequential FM signal is prohibited or the predetermined voltage is This has the effect of preventing a deteriorated image signal from being recorded due to recording of an unnecessary signal by recording the signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a still video recording device as a first embodiment and a third embodiment of the present invention, and FIG. 2 is a system controller of a still video recording device as a first embodiment of the present invention. FIG. 3 is a block diagram showing a schematic configuration of a still video recording device according to a second embodiment of the present invention, and FIG. 4 is a flowchart showing a processing operation procedure according to a third embodiment of the present invention. 5 is a flowchart showing the processing operation procedure of the system controller; FIG. FIG. 7 is a timing chart showing the relationship between the color difference line sequential signal and each pulse; FIG. 8 is a schematic diagram of a still video playback device as a conventional example. FIG. 9 is a block diagram showing the schematic structure of a still video recording apparatus as a conventional example. In the figure, 2... Luminance input terminal for dubbing, 3... Color difference line sequential input terminal for dubbing, 4... Video input circuit,
5, 6, 10. 30... Changeover switch, 7... Synchronization separation circuit, 8... Luminance FM modulator, 9... Color difference FM
Modulator, 12... ID modulation circuit, 19... CID discrimination circuit, 20... Pulse generation circuit, 25... System controller, 27... Operation instruction section, 28... Output section, 29 ...Voltage signal generation circuit, 33...CID
Signal, 111.112...DC offset circuit, 11
3...RY signal S/H circuit, 114...B-Y
Signal S/H circuit, 115... Comparator. ;French ≦tsu Figure 2 (B) Figure 4

Claims (4)

[Claims] (1) An image signal recording device that inputs a luminance signal and a color difference line sequential signal and records it on a recording medium, comprising: FM modulation means for FM modulating each of the luminance signal and the color difference line sequential signal; and the color difference line sequential signal. a discriminating means for discriminating the order of the color difference signals in the sequential signal; a multiplexing means for multiplexing the luminance signal FM modulated by the FM modulation means and the color difference line sequential signal; An image characterized by comprising: prohibition means for prohibiting the FM modulated color difference line sequential signal outputted from the FM modulation means from being supplied to the multiplexing means when it is determined that the order is not normal. Signal recording device. (2) An image signal recording device that inputs a luminance signal and a color difference line sequential signal and records it on a recording medium, comprising: FM modulation means for FM modulating each of the luminance signal and the color difference line sequential signal; and the color difference line sequential signal. Discrimination means for determining the order of color difference signals in the sequential signal; multiplexing means for multiplexing the luminance signal FM modulated by the FM modulation means and the color difference line sequential signal; and voltage signal generation means for generating a predetermined voltage signal. , when the determining means determines that the order of the color difference signals in the color difference line sequential signal is not normal, the predetermined voltage signal generated by the voltage generating means is multiplexed in place of the FM modulated color difference line sequential signal. An image signal recording device comprising: a voltage signal supply means for supplying a voltage signal to the means. (3) The discrimination means includes voltage offset means for offsetting the voltage of at least one of the R-Y signal and the B-Y signal, and the R-Y signal and the B-Y signal offset or not offset by the voltage offset means. Claim 1 or 2, characterized in that it comprises sampling means for sampling each of the signals and holding the sampling results, and comparison means for comparing the sampling values held in the sampling means. The image signal recording device described in . (4) The apparatus further comprises a warning display means for displaying a warning when the determining means determines that the order of the color difference signals in the color difference line sequential signal is not normal. The image signal recording device described in 2.