JPS61133771A - Picture signal processor - Google Patents

Abstract

PURPOSE:To intend the improvement in the processing speed and the easiness of a change and a formation in the algorithm, by dividing a digital picture signal row continued in terms of the time into blocks and processing the digital picture signal row divided in parallel and independently by a processing unit installed corresponding to respective blocks. CONSTITUTION:A signal processing part is composed of the groups of signal processing units 25-27, the digital picture signal 3 written in first or second memories 8 and 9 is read through a data bus 11, and after the linear or non- linear conversion by a function is performed, this conversion data is similarly written in the third or fourth memories 12 and 13. Every signal processing units 25-27 are processed by delivering the digital picture signal divided into (n) in a scanning direction, respectively, independently and in parallel. Moreover, every signal processing units 25-27 are provided with priority orders, and only when first to fourth memories 8, 9, 12, and 13 are accessed, the access is formed against the memory in the order of higher priority order by signals 28 and 29 during processing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an image signal processing device used in a facsimile machine, a copying machine, or the like.

(Prior art and its problems) In conventional image processing devices, the algorithm of a certain function used for one image processing is usually implemented by hardware logic circuits due to the high processing speed required. It has been realized. Therefore, when designing or changing the algorithm, it is necessary to create or modify the hardware itself, which has the drawback of requiring a great deal of effort and time to create or modify the algorithm. However, the processing speed was not necessarily fast enough.

(Object of the Invention) Therefore, an object of the present invention is to provide an image signal processing device that allows easy design or modification of the algorithm of a certain function used in two-image processing, and which has a high processing speed.

(Structure of the Invention) In the present invention, the processing speed is improved based on the following idea. In other words, in general, a value converted by a function using an input signal (X□, In this case, there is a limit to the processing speed of the microprocessor,
As a means of solving this problem, let the time length of one scanning line be T and 1
Let P be the number of pixels in the scanning line.

(2) If the number of pixels of a scanning line is divided equally into n blocks, the number of pixels per block is P/n.

The processing unit corresponding to each block is P/n during 2 hours T.
Since it is only necessary to process one pixel, it is possible to perform somewhat complex function calculations even using a relatively slow microprocessor.

Therefore, a temporally continuous digital image signal sequence is divided into a plurality of blocks, processing is provided corresponding to each block, and the digital image in which the bits are divided in parallel and independently is created by processing the plurality of processing bits. By processing signal sequences, the processing speed can be improved, making it possible to introduce microprocessors, and by writing all the algorithms necessary for processing into program memory, the algorithms can be easily implemented. Modification 2 An image signal processing device that can be created is obtained.

That is, according to the present invention, the reference numerals shown in FIG. 1, which will be explained later, will be used for reference.

a converter (2) for converting a temporally continuous photoelectric conversion output obtained by scanning the document surface, that is, an analog image signal, into a bit/9 parallel digital image signal (3);
a first temporary storage memory (8) for storing digital image signals corresponding to even-numbered scanning lines; a second temporary storage memory (9) for storing digital image signals corresponding to odd-numbered scanning lines; The digital image signals stored in the first and second temporary storage memories are read alternately, and the read digital image signals are used as variables.

Performs a linear or nonlinear transformation using a certain function.

A signal processing unit (10) that outputs the result as converted data (11), a third temporary memory memo IJ (12) that stores converted data corresponding to even-numbered scanning lines, and a third temporary memory memo IJ (12) that stores converted data corresponding to even-numbered scanning lines; a fourth temporary storage memory (13) for storing corresponding conversion data; and memory control means for controlling write and read operations of the second, third and fourth temporary storage memories.

The signal processing section is implemented by microprocessor #(3).
3) An image processing device is obtained, which is characterized in that the digital image signals are independently processed in correspondence with the 7° program memory (34) and the temporary memory scan line.

(Example) The present invention will be described in detail below with reference to the drawings.

FIGS. 1 and 2 are block diagrams of an entire image processing apparatus according to an embodiment of the present invention, and the internal configuration of a signal processing unit that is a part of the image processing apparatus.

In FIG. 1, 1 indicates photoelectrically converted analog image signals (Xe, x2, . . . xn). Reference numeral 2 denotes a converter for sampling this analog image signal with a sampling clock 4 and converting it into a digital image signal (DPIX in the figure) 3 with bits i<'. 5
1 shows a timing generation circuit that generates a sampling clock 4 and a sampling effective range signal 6 that defines the sampling range in the main scanning direction. 7 counts the signal sampling relock 4 while the signal 6 is active, and outputs the digital image signal 3 to the first temporary storage memory (hereinafter referred to as the first memory) 8 and the second memory 9. and the write address of the third memory 12
and an address counter that generates a read address of converted data for the fourth memory 13. 2 in the diagram
The r-t circuit surrounded by dotted lines, flip frozzo (F'F in the figure) 14° selectors 15, 16, 18,
], 9, 20, 22.

The distributors 17 and 22 constitute the memory control section 10. In this memory control section, flips 70, 7'
l 4 (denoted as FF' in the figure) by frequency-dividing the sampling effective range signal 6.

Memo') sp 9? 12F generates timing signals 23 and 24 that control data write and read sequences for 13.

When the first timing signal 23 is Pao'', that is, the second
during the period when the timing signal 24 is 1''.

The first memory 8 receives address designation by the address counter 7 through the selector 15, and the digital image signal 3 is written through the two-way divider 17. Further, the second memory 9 receives address designation from the signal processing section 10 through the selector 16, and the digital image signal 3 is read out through the selector 18. Further, the third memory 12 receives address designation by the address counter 7 through the selector 19, and the converted data is read out through the selector 22. Further, the fourth memory 13 receives address designation from the signal processing section 10 through the selector 20, and conversion data of the signal processing section 10 is written.

Further, when the first timing signal 23 is P1n, that is, the second timing signal 23 is
During the period when the timing signal 24 is +10 II, the way each memo 'J 8 # 9 j 12 P 13 is controlled is reversed.

The signal processing unit is a signal processing unit 25 , 26 , . . . 27
The group consists of a group of Similarly, the third memory 12
Or write to the fourth memory 13. Each of the signal processing units 25 to 27 receives and processes the digital image signal divided into n in the scanning direction independently and in parallel. Further, each signal processing unit 25 to 27 is prioritized, and the first to fourth memo IJ8°9, +2
．． Processing messages only when accessing +3.

28 and 29 while monitoring the access state of each signal processing unit to the first to fourth memories.

The memory is accessed in order of priority. Note that 31 is a lead gurus and 32 is a light gurus.

FIG. 2 shows the internal configuration of the signal processing unit 26, and 33. is according to the Alco 9 rhythm of a certain function written in the program memo IJ+34.

It is a microprocessor that processes digital image signals using the current storage memory 35 as a working area and outputs the converted data. Furthermore, the signal processing units 25 at both ends
and 27 lack the processing signals 28' and 29'.

(Effects of the Invention) As explained above, the present invention uses multiple microprocessors to divide and process one image data.
Relatively slow microprocessor,? However, in addition to enabling high-speed data processing, by writing the algorithms necessary for data processing into the program memory, the Alco9 rhythm can be easily created or changed in a short time. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an image signal processing apparatus according to the present invention, and FIG. 2 is a block diagram showing the internal configuration of a signal processing unit in FIG. 1. Explanation of symbols: 1 is an analog image signal, 2 is a converter, 3 is a digital image signal, 4 is a sampling clock, 5 is a timing generation circuit, 6 is a sampling effective range signal, 7 is an address counter t, 8 is a first Temporary storage memory (first memory), 9 is a second temporary storage memory (second memory 1), 10 is a signal processing section, 11 is conversion data (data bus),
12 is a third temporary storage memory, 13 is a fourth temporary storage memory, and 14 is a flip flop (FF). 15. 16 is a selector, 17 is a distributor, 18 to 20 are selectors l, 21 is a distributor, 22 is a selector j, 23 is a first timing signal, 24 is a second timing signal,
25 to 27 are signal processing units. 28.29 is the processing signal, 30 is the address bus, -31
32 represents a read path and 32 represents a write pulse.

Claims (1)

[Claims] 1. An A/D converter that converts an analog image signal obtained by scanning a document surface into a bit-parallel digital image signal, and a first temporary storage memory that stores the digital image signal corresponding to an even-numbered scanning line. and a temporary storage memory for storing the digital image signals corresponding to odd-numbered scanning lines, and the digital image signals stored in the first and second temporary storage memories are read alternately, and the read digital image is read out. a signal processing unit that performs linear or nonlinear conversion using a certain function using a signal as a variable and outputs the result as conversion data; a third temporary storage memory that stores conversion data for the even-numbered scanning line; a fourth temporary storage memory for storing conversion data corresponding to odd-numbered scanning lines; write and read operations of the first digital signal to and from the first and second temporary storage memories; and the third and fourth temporary storage memories; and a memory control means for controlling the writing/reading of the conversion data to/from a temporary storage memory and the output operation to the outside; An image signal processing device comprising a processing unit, wherein the processing unit is configured to process each of the digital image signals independently and in parallel corresponding to scanning lines divided into n in the scanning direction. .