JPS61133671A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce series resistance effectively, by etching a part of the surface of an operating layer with a gate electrode as a mask after the gate electrode is formed and before or after the ions are implanted into source and drain regions. CONSTITUTION:By using a mask, an n type operating layer 13 is formed on a GaAs substrate 11. Then, a heat resisting metal film 14 is formed on the operating layer 13. Patterning of the film 14 is performed by anisotropic dry etching and a gate electrode 14' is formed. At this time, the etching is not stopped under the state the surface of the substrate is exposed, and over-etching is performed. The surface of the substrate including the operating layer 13 is etched. Then, by using a mask, ions are implanted, and high-concentration ion implanted layers 16 and 17 (source and drain regions) are formed. Thus, a normally OFF type GaAs MESFET, in which series resistance between the gate and the source is small, can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, particularly a GaAS Schottky gate field effect transistor (MESFE).
T).

[Technical background of the invention and its problems]

GaAs MESFETs are widely used as individual semiconductor elements constituting high frequency amplifiers, oscillators, and the like. Recently, they are also playing an important role as basic elements of GaAS high-speed logic circuits.

Among them, the normally-off MESFET is DCFL (D
direct Coupled FET LoQic)
It is an important component in high-speed logic circuits, and its high performance is the key to manufacturing high-speed logic circuits.

The figure of merit of a GaAs MESFET is written as C(I8/low), where C is the gate-source capacitance, and g
s is mutual conductance. Therefore, the figure of merit is improved by reducing CIJS and increasing 01. Focusing on ge, the actual ga+ of the FET is am-oso/(1+og+o·Rs). 0
10 is the intrinsic mutual conductance determined from the characteristics of the channel portion of the FET, and is the maximum gm that can be extracted. R8 is a series resistance between the gate and source.

FIG. 2 shows the configuration of a conventional general GaAs MESFET. Reference numeral 21 designates a semi-insulating GaAS substrate, on the surface of which an n-type active layer 22 is formed, and on the surface of this active layer 22, a gate electrode 23 forming a Schottky barrier and drain and source electrodes 24 and 25 in ohmic contact are formed. It is formed.

In this conventional configuration, the series resistance R9 between the gate and source is
is large, and from the above equation, gm becomes smaller than gmo. Therefore, how to reduce R8 is the key to obtaining a large mutual conductance and improving the high frequency characteristics of the FET.

A self-line method is known as a method for reducing the series resistance R8 of the MESFET. There are several methods for this, but the MESFE obtained by one of them
The configuration of T is shown in FIG.

In this method, an n-type active layer 32 is formed on a semi-insulating GaAs substrate 31, a gate electrode 33 is formed on the surface of the n-type active layer 32, and then source and drain regions 34 and 35 are formed by high concentration ion implantation using the gate electrode 33 as a mask. It is something. 36
．． 37 are source and drain electrodes. in this way,
Since the source and drain regions 34 and 35 are formed close to the gate electrode 33, the series resistance R8 becomes small.

However, according to this method, another problem arises in that the gate breakdown voltage decreases. For this reason, the source.

There are naturally limits to high-concentration ion implantation for the drain.

ME using the self-line method solves these problems.
As SFETs, those shown in FIGS. 4 and 5 are known. In the case shown in FIG. 4, an active layer 42 is formed on a semi-insulating GaAs substrate 41, a gate electrode 43 is patterned on its surface using a mask 44, and then side etching is performed on the gate electrode 43, and a mask 44 is removed. The source and drain regions 45 and 46 were formed by ion implantation using the structure as it was. As a result, the gate electrode 43 and the source,
A constant spacing is provided between the drain regions 45,46. In the case shown in FIG. 5, an active layer 52 is formed on a semi-insulating GaASM plate 51, a gate electrode is formed on the surface of the active layer 52, and then high-concentration ions are implanted with acceleration energy higher than usual in source and drain regions 54,55. was formed. As a result, the low resistance source and drain regions 54 and 55 are formed without increasing the surface concentration too much, thereby preventing a decrease in gate breakdown voltage.

However, the methods shown in FIGS. 4 and 5 each have their own drawbacks. That is, in the method shown in FIG.
3 is side-etched, the difference in pattern conversion with the mask becomes large, which has a large effect on variations in threshold values and the like. Furthermore, in the method shown in FIG. 5, the resistance of the surface portion of the active layer, which contributes dominantly to the series resistance R8, is not lowered, and short circuits are caused by the lateral diffusion of impurities in the source and drain regions in deep portions. Channel effects are more likely to occur.

[Purpose of the invention]

The present invention solves the above-mentioned difficulties and provides a self-line type GaAsMEl:5FET that effectively reduces the series resistance R5 while maintaining sufficient gate withstand voltage, thereby making it possible to improve performance.
The purpose is to provide a manufacturing method for.

[Summary of the invention]

In the present invention, a gate electrode made of a heat-resistant metal is formed on the surface of the active layer, and high-concentration ion implantation is performed using the gate electrode as a mask to form source and drain regions.
In the MESFET manufacturing method, after forming the gate electrode and before the high concentration ion implantation process for the source and drain regions, or after the high concentration ion implantation process for the source and drain regions,
It is characterized by the addition of a step of partially etching the surface of the active layer using the gate electrode as a mask.

〔Effect of the invention〕

According to the present invention, self-line type GaAs having a large mutual fundance and a large gate breakdown voltage can be used.
MESFET can be obtained.

[Embodiments of the invention]

The present invention will be described in detail below with reference to FIGS. 1(a) to 1(0).

First, as shown in FIG. 1(a), 3i+ ions are implanted at 2x10"/cd at 50KeV into a semi-insulating GaAS substrate 11 using a mask 12, and by annealing at 850°C for 15 minutes, selective n A mold operation layer 13 is formed. Next, the mask 12 is removed, and as shown in FIG. 1(b), a tungsten nitride (WN) film 14 is formed as a heat-resistant metal by reactive sputtering. Using a resist (not shown) as a mask, CF4 and 02
The WN film 14 is patterned by anisotropic dry etching using a mixed gas to form a gate electrode 14' as shown in FIG. 1(C). At this time, without stopping etching with the substrate surface exposed as shown in Figure 1(C),
By performing over-etching, Fig. 1(d)
As shown in FIG. 2, the surface of the substrate including the active layer 13 is etched by about 100 people. As a result, the gate length becomes slightly longer due to the step difference on both sides of the gate electrode 14', but when the gate length is 1 to 0.5 μm, the amount of etching on the substrate surface can be reduced by 3
If a range of 0 to 200 people is selected, the substantial increase in gate length can be ignored. After that, as shown in FIG. 1(e), a mask 15 is formed in a portion other than the element region, and using this and the gate electrode 14' as a mask, S1+ ions are again implanted at 100 KeV at 1X1014/CIA, and the gate electrode 14 is A self-lined high-concentration ion implantation layer 16 and 17 is formed at . Then, the mask 15 is removed and PSGll is applied to the entire surface of the substrate as shown in FIG. 1(f).
B is deposited and heat-treated at 800°C for 10 minutes to form activated n+ type source and drain regions 16" and 17-. After this, PSGIt! 18 is removed, and as shown in FIG. 1(q), Then, source and drain electrodes 19 and 20 made of AuGe/AU are formed.

As described above, according to this embodiment, a normally-off self-lined GaAs MESFET with a small series resistance Rs between the gate and source can be obtained. This MES
The FET is a non-self-line type MES shown in Figure 2.
A transconductance gm of about 230 m5/mm, which is about three times larger than that of an FET, was obtained. Furthermore, compared to the conventional self-line type MESFET shown in FIG. 3, the gate breakdown voltage was large and good at about 10 V or more.

Furthermore, compared to the structure shown in Fig. 4 in which the gate electrode is laterally etched to improve the gate breakdown voltage, the variation in the threshold value is smaller, and the short channel effect observed in the structure shown in Fig. 5 can be avoided when the gate length is 0. A thickness of up to .5 μm was not observed.

Note that the present invention is not limited to the above embodiments. For example, other heat-resistant metals such as tungsten silicide (WS i ) can be used as the gate electrode metal. In addition, the step of etching the substrate surface was performed after the gate electrode etching before the high concentration ion implantation of the source and drain in the *example mentioned above, but it may be performed after the high concentration ion implantation of the source and drain. .

[Brief explanation of drawings]

Figures 1(a) to 1) show GaAsMEs according to an embodiment of the present invention.
FIGS. 2 to 5, which are diagrams showing the manufacturing process of SFET, are diagrams showing a conventional GaAs MESFET. DESCRIPTION OF SYMBOLS 11... Semi-insulating GaAS substrate, 13... N-type operation layer, 14... WN film, 14'... Gate electrode, 16
゜17...High concentration ion implantation layer, 16-. 17-...
- Source, drain region, 19.20...source, drain electrode. Applicant's agent Patent attorney Takehiko Suzue - ^ ^ 0 °0 ν V Figure 2 Figure 3 Figure 4 Figure 5

Claims (2)

[Claims] (1) Manufacturing a semiconductor device in which a gate electrode made of a heat-resistant metal is formed on a semi-insulating GaAs substrate on which an active layer is formed, and source and drain regions are formed by high-concentration ion implantation using this gate electrode as a mask. In the method, the surface of the active layer is partially etched using the gate electrode as a mask after forming the gate electrode and before the high concentration ion implantation process for the source and drain regions, or after the high concentration ion implantation process for the source and drain regions. A method for manufacturing a semiconductor device, characterized in that: (2) The amount of etching on the surface of the active layer is 30 to 200 Å
A method for manufacturing a semiconductor device according to claim 1.