JPS61133476A - Operating circuit - Google Patents

Abstract

PURPOSE:To improve remarkably the processing speed by saving processing including carry requiring much processing time into two-stage in an operation circuit for norm calculation. CONSTITUTION:A value '010100001' is stored in an input register 101 and '01000011' is stored in an input register 102. The input corresponds to it that the 1st component of an input pattern vector is '0101' and the 2nd component is '0001', the 1st component of a standard pattern vector is '0100' and the 2nd component is '0011', the difference between the 1st components is 1, the difference between the 2nd components is '2' and the sum is '3'. The input t an adder 105 is '0101' and '1011' being the inverted data of '0100' and the result of operation is '0000' and the carry of the most significant digit is '1'. On the other hand, the carry of most significant as the result of operation of an adder 106 is '0' and then the output of a selection circuit 110 is '0010'. In an adder 111, '0000', '0010', the most significant digit carry '1' of the adder 105 and the carry of the adder 106 '0' cause '0011' and this means the sum of the differences between the 1st components and between the 2nd components.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic circuit for determining a norm between vector data.

(Prior art) In the field of pattern recognition, the norm (
There are many cases in which the distance (distance) is sought. For example, in voice recognition, the input voice is analyzed and converted into a time series (bang) of vectors representing the % enemy of the voice, and this is matched with a standard pattern registered in advance to find the smallest distance. A common method is to use a given standard pattern as the recognition result.

During this pattern matching, the main calculation is to calculate the special ridge vector of the input batten ``'' (aI + J +...e
ak) and the special ridge vector 1t) of the standard pattern = (b, , b
, . . . , bk). That is, they are subtraction, absolute value conversion, and cumulative addition expressed by the following formula.

d=llll-To11=Σ 1ak-bkl-t This calculation has generally been realized by software, but has the problem of requiring processing time and not improving matching performance.

In addition, the bit length of each component of the audio pattern can often be shorter (e.g., 8 bits) than the word dot length of the processor (e.g., 16 bits), and two audio pattern components can be stored in one word of the processor. This storage method is effective in reducing the amount of memory. However, when implementing this method with a conventional processor, the distance calculation must be performed after separating the two speech pattern components included in one word, and the separation process requires additional processing time. had.

registers 1 and 2, adders 5 and 6, inverter 3,
4.7 and 8, +1 adder 13.14°15 and 16, +1 when the most significant carry of adder 5 is IO”
When the output of adder 13 is 1″ and 0″, it is +1 adder 1
It is comprised of a selection circuit 10 that selects and outputs the output of adder 6 when the output of 4 is 11', an adder 11, and an output register 12.

The upper half word of the input register 1.2 becomes the input to the adder 5 and the inverter 30, and the lower middle word becomes the input to the adder 6 and the inverter 4. This configuration uses the fact that the operation of inverting the sign of the numerical value □□ is an operation of inverting each bit and adding 1, and the output of the selection circuit 9 is The absolute value of the difference between the upper value and the output of the selection circuit 10 is designed to output the absolute value of the difference between the lower value of the input register 1 and the lower value of the input register 2, respectively.

(Problems to be Solved by the Invention) Generally, calculation time is required for the portion where the carry is propagated. In the conventional circuit shown in Fig. 1, adders 5, 6 and 11 and +1
Adders 13, 14, 15 and 16 correspond to this. +1
Adders 15 and 16. Adders 5 and 6, +1 adders 13 and 1
4 is executed in parallel, so it has to pass through a circuit that includes four stages of carry, which poses a problem in that it hinders speeding up the processing.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, reduce the number of carry stages, and provide an arithmetic circuit for norm calculation that can operate at high speed.

(Means for Solving the Problems) The device of the present invention includes first and second input designating means consisting of 2n bits (n is a natural number), and data of the upper n bits of the first input designating means. X, and data Y of the upper n bits of the second input specifying means are input, and
, data X of the lower n bits of the first input designation means, and data Y of the lower n bits of the second input designation means! and a second arithmetic means which performs the calculation of X1+Y1 with input of a first selection means that outputs the calculation result of the first calculation means when the carry is "1"; and an output of the calculation means when the most significant carry of the second calculation means is O''; a second selection means which inverts and outputs the calculation result of the second calculation means when the most significant carry is "1", and outputs the output z1 of the first selection means and the second The output of the selection means Z! and the most significant carry C8 of the first calculation means.
and third arithmetic means for performing the most significant carry Ct tra input (!: LZI + Zt + Ct + Ct O operation) of the second arithmetic unit means.

(Example) Next, one embodiment of the present invention will be described using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The arithmetic circuit shown in FIG. 2 includes input registers 101 and 102, inverters 103, 104, 107 and 106, a selection circuit 109, an adder 111, and an output register 112.

In the selection circuit 1.09, the most significant carry of the adder 105 is 0.
'', the output of the inverter 107 is output, and when the value is ``1'', the calculation result of the adder 105 is output.
0 outputs the output of the inverter 108 when the most significant carry of the adder 106 is 'θ'', and outputs the calculation result of the adder 106 when it is 11''. Adder 111 performs addition of selection circuits 109 and 110, and adders lO5 and 10.
The most significant carry of 6 is also added.

As an example, input register 101 and 1020 bit length are assumed to be 8 bits. Input register 101 has 01010
001" (binary representation), input register 102 has "01"
The operation will be explained assuming that ``000011'' is stored.This means, for example, that the first component of the input button vector is ``0''.
101″, the second component is “0001″.

The first component of a standard batan vector is '0100'.

This corresponds to the fact that the second component was ``0011''.

The difference in the first component is 1. The difference in the second component is 2, and the sum is 3.

Now, the input of adder ios is '0101'' and @0100
With the inverted data ``1011'' of ``, the calculation result ``'oooo
”, the highest carry is “1”. Therefore, the selection circuit 10
The output of 9 is "oooo". On the other hand, adder 106
Similarly, the result of the operation is '1i o i' and the most significant carry is 'o'.Therefore, the output of the selection circuit 110 is the inversion of the output of the adder 106 and becomes '0010'.

In the adder 111, the output becomes '0011'' by adding 'oooo'' and '0010'', the most significant carry 1'' of the adder 105, and the most significant carry O'' of the adder 106. It is the sum of the difference in one component and the difference in the second component.

That is, according to this embodiment, the sum of the differences between the two bang components stored in the input register 101 and the two bang components stored in the input register 102 can be obtained at the same time.

(Effects of the Invention) The present invention has the effect that the processing speed can be significantly improved by reducing the portion including carry that requires oversalting time to two stages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram according to the prior art, and FIG. 1 is a block diagram showing an embodiment of the present invention. 1.2.101,102...Input register, 3
,4゜7.8,103,104,107.108...
・Inverter, 5゜6.11, 105, 106, 111・
...Adder, 9.10゜109.110...
...Selection circuit, 13, 14, 15, 16...-+
1 adder. lDI Tuft 2 $ 7 Figure

Claims (1)

[Claims] First and second input specifying means each consisting of 2n bits (n is a natural number); and data X_1 of the upper n bits of the first input specifying means.
and the data Y_ of the upper n bits of the second input specifying means.
1 and perform the operation of X_1+@Y@_1.
calculation means, and data X_2 of the lower n bits of the first input designation means.
and the data Y_ of the lower n bits of the second input specifying means.
2 and performs the operation of X_2+@Y@_2.
when the most significant carry of the first arithmetic means is "0", the output of the first arithmetic means is inverted and output; and when the most significant carry is "1", the output of the first arithmetic means is inverted and outputted; The first selection means outputs the calculation result of the first calculation means, and when the most significant carry of the second calculation means is "0", the output of the second calculation means is inverted and outputted. a second selection means that outputs the second calculation result when the most significant carry is "1"; and an output Z_1 of the first selection means, an output Z_2 of the second selection means and the first Most significant carry of calculation means C_
1 and the most significant carry C_2 of the second arithmetic means, and a third arithmetic means for performing an arithmetic operation of Z_1+Z_2+C_1+C_2.