KR100223752B1 - Parallel multiplier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel multiplier using a data compressor that compresses and adds bit processed data using a data compressor composed of a pass transistor multiplexer to obtain a multiplication result. The bit pre-processing unit 13 for performing the operation with each multiplier, the data compressor 14 for compressing the data output from the bit pre-processing unit 13, and the outputs of the data compressor 14 are added up to form a final result. The adder 15 outputs a multiplication value PS.

Therefore, the present invention scans a multiplier by two bits and computes the multiplier so that simultaneous computational processing is possible, and the calculated data is compressed and added, thereby reducing the number of adders. It has a decreasing effect.

Description

Parallel multiplier

1 is a block diagram of a conventional multiplier.

2 is an embodiment configuration of a parallel multiplier according to the present invention.

3 is a detailed block diagram of the bit pre-processing unit of FIG. 2 according to the present invention.

4 is a detailed configuration diagram of the logical operation unit of FIG. 3 according to the present invention.

5 is a detailed block diagram of the data compressor of FIG. 2 according to the present invention.

6 is a detailed circuit diagram of the multiplexer of FIG. 5 in accordance with the present invention.

7 is a correlation diagram of the i-th bit and the multiplier 2 bits of the n-bit multiplier.

* Explanation of symbols for main parts of the drawings

11, 12: register 13: bit preprocessing unit

14 data compressor 15 adder

21, 26, 27, 28: AND gate 22, 23, 24, 25: logic operation unit

29: Exclusive Oa Gate

31, 32, 33, 34, 35, 36: multiplexer

M1, M2, M3, M4, M5, M6, M7, M8: MOS transistors

The present invention relates to a parallel multiplier, and more particularly, to a parallel multiplier for compressing and adding bit processed data using a data compressor including a multiplexer composed of pass transistors to obtain a multiplication result.

In general, the parallel multiplier is widely used in digital signal processing devices, and a new digital signal processing device for processing a large amount of digital information signals more rapidly is required in the recent information age. Therefore, a parallel multiplier with a fast multiplication operation is essential.

1 is a block diagram of a conventional multiplier.

As shown in FIG. 1, the conventional multiplier multiplies the output values of the multiplier 1 and the multiplier 1 by multiplying the multiplier A of n bits and the multiplier B of m bits by corresponding bits, respectively. Each is composed of a summing unit (2) for summing by weight.

The operation of a conventional multiplier configured as described above will be described taking an example of multiplication of an n-bit multiplier A and an m-bit multiplier B.

First, a _n-1 a _n-2 ... n multiply by A ₁ a ₀ and multiply by b _m-1 b _m-2 . The multiplier B of the m bits consisting of b ₁ b ₀ is multiplied bit by bit in the multiplier 1. At this time, the multiplied result is summed by the weights in the adder 2 and output as a multiplication value P.

In the conventional multiplier operating as described above, as the number of bits of the multiplier and the multiplier increases, the number of adders in the adder 2 that adds the multiplied values output from the multiplier 1 by weight increases proportionally to obtain a multiplier value. Since time is required, there is a problem in that when applied to a multi-digital signal processing device that requires a high speed adversely affects the processing speed of the multi-digital processing device.

In addition, since the conventional multiplier requires a large number of adders, it requires a large design area, thereby increasing the size of the multiplier.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel multiplier for improving the multiplication operation speed and reducing the design area by a data compression operation through a data compressor composed of a multiplexer.

In order to achieve the above object, the parallel multiplier according to the present invention scans an m-bit multiplier by two bits, receives a logical operation with an n-bit multiplier, and outputs a plurality of bit carry signals (C _i-1 ) and a plurality of processing signals (G). _i ) a plurality of bit preprocessing means for respectively generating _i ); By receiving the plurality of bit carry signal (C _i-1 ) and the plurality of processing signal (G _i ) output from the bit pre-processing means and performing a compression operation, one addition signal (S) and one carry signal ( A plurality of data compression means for outputting CO); And an addition for receiving and adding the addition signal S and the carry signal CO respectively output from the plurality of data compression means to output the final multiplication value PS of the m-bit multiplier and the n-bit multiplier. The data compression means, including means, comprises a multiplexing part made up of the same number as the multiplicand and the number of bits, the multiplexing part, in response to the first processing signal G ₁ output from the bit pre-processing means. A first multiplexer for selectively outputting a processing signal (G ₂ ) and the inverted second processing signal (G ₂ ); A second multiplexer for selectively outputting a fourth processing signal (G ₄ ) and the inverted fourth processing signal (/ G ₄ ) in response to a third processing signal (G ₃ ) output from the bit pre-processing means; A third multiplexer for selectively outputting a positive output signal and a sub output signal of the second multiplexer in response to an output signal from the first multiplexer; A fourth multiplexer for selectively outputting the first processing signal (G ₁ ) and the third processing signal (G ₃ ) to the next multiplexing unit in response to an output signal from the first multiplexer; The multiplexer and a second rear end of the fourth processor signal G ₄ and the bit carry signal C _i-1 from the bit pre-processing means in response to an output signal from the third multiplexer. A fifth multiplexer outputting the carry signal C of the adding means; And the addition signal S of the adding means by selecting a signal CO outputted from the fourth multiplexer of the multiplexing unit and its inverted signal / CO in response to an output signal from the third multiplexer. It consists of a sixth multiplexer for outputting.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

2 is a diagram illustrating an embodiment of a parallel multiplier according to an embodiment of the present invention, FIG. 3 is a detailed block diagram of a bit pre-processing unit of FIG. 2, and FIG. 4 is a detailed block diagram of a logical operation unit of FIG. 3, and FIG. FIG. 2 is a detailed configuration diagram of the data compressor of FIG. 2, and FIG. 6 is a detailed circuit diagram of the multiplexer of FIG. 5, and FIG. 7 is a correlation diagram between the i-th bit and the multiplier 2 bits among n-bit multipliers.

The parallel multiplier according to the present invention is composed of registers 11 and 12, bit pre-processing section 13, data compressor 14, and adder 15, as shown in FIG.

The register 11 stores an n-bit multiplier A and outputs it to the bit preprocessing unit 13, and the register 12 stores an m-bit multiplier for scanning the bit preprocessing unit 13. do.

The bit pre-processing unit 13 receives the multipliers of the m bits stored in the register 12 and scans each of the two bits to multiply the multipliers of the n bits stored in the register 11, respectively, as shown in FIG. As described above, the first bit b ₀ or b ₂ of the scanned 2-bit multiplier and the least significant bit a ₀ of the n-bit multiplier are ANDed so that a processing signal G ₀ is transmitted to the data compressor 14. Outputs an AND gate 21 and a plurality of bit carry signals by performing a logical operation with input of two bits while moving in the upper bit direction one bit from the lowest of the scanned two-bit multiplier and the n-bit multiplier. C _i-1 ) and a plurality of logic operation units 22, 23, 24, and 25 respectively outputting the plurality of processing signals G _i to the data compressor 14.

Here, the logical operation unit is made of the same number of bits as the multiplicand as shown in FIG. 4, and as shown in FIG. 4, the second bit b ₁ and the multiplier of the multipliers of the scanned two bits are shown. AND gate 26 to logically multiply the lower 1 bit (a _i-1 ) of 2 bits, the first bit (b ₀ ) of the scanned 2 bits multiplier and the upper 1 bit (a _i ) of 2 bits of the multiplicand AND gate 27 to logically multiply by, multiply the scanned two-bit multiplier (b ₁ b ₀ ) and the two bits (a _i a _i-1 ) of the multiplicand by the data compressor 14 to the bit carry signal ( An AND gate 28 for outputting C _i-1 , and an exclusive OR gate 29 for outputting a processing signal G _{i by} performing an exclusive OR on the outputs of the AND gates 26 and 27.

In addition, the data compressor 14 compresses the data output from the bit pre-processing unit 13, and has the same number as the number of bits of the multiplicand and the AND gate 21 of the bit pre-processing unit 13. It consists of a plurality of bit carry signals (C _i-1 ) and a plurality of processing signals (G _i ) output from the logic operation units (22, 23, 24, 25).

Here, the multiplexing unit is inverted from the processing signal G ₂ output from the logic operation unit 23 using the processing signal G ₁ output from the logic operation unit 22 as a selection signal, as shown in FIG. 5. The multiplexer 31 which selects and outputs one of the processing signals / G ₂ , and the processing output from the logic operation unit 25 using the processing signal G ₃ output from the logic operation unit 24 as a selection signal. The multiplexer 32 which selects and outputs one of the signal G ₄ and the inverted processing signal / G ₄ , and the positive output and the negative output of the multiplexer 32 using the output of the multiplexer 31 as a selection signal. Select one of the multiplexer 33 and the output signal of the multiplexer 31 as a selection signal and select one of the processing signals G ₁ and G ₃ output from the logic calculating units 22 and 24. A multiplexer 34 that selects and outputs the signal CO to a next multiplexer, a processing signal G ₄ output from the logic operator 25 using the output of the multiplexer 33 as a selection signal, and the logic operator The multiplexer 35 which selects one of the bit carry signals C _i-1 output from (22, 23, 24, 25) and outputs the carry signal C to the multiplexer and the adder 15 at the second stage. And select one of a signal CO output from the multiplexer 34 and an inverted signal / CO using the output of the multiplexer 33 as a selection signal and add the signal S as an adder signal S. 25) and a multiplexer 36 for outputting.

At this time, the multiplexers 31, 32, 33, and 36 are PMOS having the input signal DO as the source input, the selection signal S as the gate input, and the drain connected to the output terminal OUT as shown in FIG. NMOS transistor M2 having a transistor M1 and the input signal DO as a drain input, the inverted selection signal / S as a gate input, and a source connected to the output terminal OUT, and the inverted input signal. PMOS transistor M5 having a source (/ DO) as the source input, the select signal S as a gate input, and a drain connected to the inverting output terminal / OUT, and the inverted input signal / DO as a drain input. And an inverted selection signal / S as a gate input and an NMOS transistor M6 having a source connected to the inverting output terminal / OUT.

Also, as shown in FIG. 6, the multiplexers 34 and 35 have a PMOS transistor M1 having an input signal DO as a source input, a selection signal S as a gate input, and a drain connected to the output terminal OUT. The input signal DO is a drain input, the inverted selection signal / S is a gate input, and an NMOS transistor M2 and a source signal D1 having a source connected to the output terminal OUT are drain inputs. And the selection signal S as a gate input, the NMOS transistor M3 having a source connected to an output terminal OUT, the input signal D1 as a source input, and the inverted selection signal / S as a gate input. And a PMOS transistor M4 having a drain connected to the output terminal OUT, the inverted input signal / DO as a source input, the selection signal S as a gate input, and a drain at the inverted output terminal / OUT. Connected PMOS Trans NMOS transistor M6 having the master M5, the inverted input signal / DO as a drain input, the inverted selection signal / S as a gate input, and a source connected to the inverted output terminal / OUT, An NMOS transistor M7 having the inverted input signal / D1 as a drain input, the selection signal S as a gate input, and a source connected to an inverted output terminal / OUT, and the inverted input signal / D1 ) Is configured as a source input, and the inverted selection signal / S is a gate input, and a PMOS transistor M8 having a drain connected to the inverting output terminal / OUT.

The adder 15 adds the outputs of the data compressor 14 to output the final multiplication value PS.

The operation of the parallel multiplier according to the present invention configured as described above will be described.

The bit pre-processing unit 13 receives the multipliers of m multipliers of the register 12 as input and scans the multipliers scanned by two bits and the n-bit multiplier stored in the register 11, as shown in FIG. The bit carry signal C _i-1 and the processing signal G _i are output to the data compressor 14. As described above, the operation method performed by the bit preprocessing unit 13 has a function of obtaining a multiplication sum.

Among the n bits of the multiplicand, the number of two bits of the multiplier combined with the i-th multiplicand is four of 00, 01, 10, and 11, and the relationship is as shown in FIG.

Seventh also a _i is the multiplicand n represents of the value of the i-th multiplicand bit, a _i-1 is the multiplicand of n bits of the represent values of the i-1-th multiplicand, b ₀ b ₁ a 2 bit scan a multiplier in one b ₀ represents the first bit and b ₁ represents the second bit.

Therefore, when multiplying the i-th bit of the multiplicand and the multiplier 2 bits, the multiplier b ₀ is multiplied by the multiplier a _i and the multiplier b ₁ is multiplied by the multiplier a _i-1 through an exclusive ora gate 29 to process the processing signal. Get the value of (G _i ). In addition, the bit carry signal C _i-1 is a value obtained by multiplying all four bits a _i , a _i-1 , b ₁ , and b ₀ .

If we express this relationship logically,

G _i = (a _i and b ₀₎ + (ai-1 and b ₁₎

Become this

Ci = (ai · a _i-1 · b1 · b0)

Becomes Accordingly, as shown in FIG. 3, four cases of multipliers corresponding to the multiplicative n bits can be easily generated, and the generated processing signal G _i and the bit carry signal C _i-1 are generated by the data compressor 14. ) Is entered.

For example, in the multiplication of a multiplier a ₃ a ₂ a ₁ a ₀ and multiplier b ₃ b ₂ b ₁ b ₀ , the bit preprocessing unit 13 performs the result as shown in FIG. 3 to obtain a final output value PS. Can be.

The bit carry signal C _i-1 and the processing signal G _i generated by the bit pre-processing unit 13 are again compressed through the data compressor 14.

That is, the data compressor 14 is required for fast performance in data processing. As shown in FIG. 5, the data compressor 14 is composed of a multiplexing unit composed of a multiplexer, and the multiplexer is composed of MOS transistors as shown in FIG.

The input signal D1 is output when the input selection signal S is '1' and the input signal D0 is output when the selection signal S is '0', and the output signal is controlled by the multiplexer of the next stage. Used as a signal.

That is, the multiplexer 31 outputs the processed signal (G ₁₎ processing the signal is a "0" by using a selection signal processing signal (G ₁₎ (G _2), and if "1" inversion processing signal (/ G ₂ ) is printed. Similarly, the multiplexers 32, 33, 36 operate in the same manner as the multiplexer 31.

In addition, the multiplexer 34 selects and outputs one of the processing signals G ₁ and G _{3 using} the output of the multiplexer 31 as a selection signal. Similarly, the multiplexer 35 operates in the same manner as the multiplexer 34.

In this way, the three signals output from the multiplexers 34, 35, 36 are input to the next stage or the second stage rear stage, or the adder 15.

Signals output from the data compressor 14 are added by the adder 15. Since data is compressed by the data compressor 14, fast addition can be performed.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the parallel multiplier according to the present invention, a conventional multiplier increases the number of full adders as the number of bits of the multiplier and the multiplier increases, while the operation processing speed is slowed. Therefore, it is possible to perform simultaneous arithmetic processing, reduce the number of adders by compressing and adding the data calculated by the multiplexer data compressor, and increase the arithmetic processing speed and design area by reducing the adders.

Claims (7)

a plurality of bit pre-processing means for generating a plurality of bit carry signals (C _i-1 ) and a plurality of processing signals (G _i ) by scanning an m-bit multiplier by two bits and performing a logical operation with an n-bit multiplier; By receiving the plurality of bit carry signal (C _i-1 ) and the plurality of processing signal (G _i ) output from the bit pre-processing means and performing a compression operation, one addition signal (S) and one carry signal ( A plurality of data compression means for outputting CO); And an addition for receiving and adding the addition signal S and the carry signal CO respectively output from the plurality of data compression means to output the final multiplication value PS of the m-bit multiplier and the n-bit multiplier. Means; wherein said data compression means comprises a multiplexing section comprising a number equal to the number of bits of said multiplicand, said multiplexing section responsive to a first processing signal G ₁ output from said bit pre-processing means; A first multiplexer for selectively outputting a processing signal (G ₂ ) and the inverted second processing signal (G ₂ ); A second multiplexer for selectively outputting a fourth processing signal (G ₄ ) and the inverted fourth processing signal (/ G ₄ ) in response to a third processing signal (G ₃ ) output from the bit pre-processing means; A third multiplexer for selectively outputting a positive output signal and a sub output signal of the second multiplexer in response to an output signal from the first multiplexer; A fourth multiplexer for selectively outputting the first processing signal (G ₁ ) and the third processing signal (G ₃ ) to the next multiplexing unit in response to an output signal from the first multiplexer; The multiplexer and a second rear end of the fourth processor signal G ₄ and the bit carry signal C _i-1 from the bit pre-processing means in response to an output signal from the third multiplexer. A fifth multiplexer outputting the carry signal C of the adding means; And the addition signal S of the adding means by selecting a signal C0 outputted from the fourth multiplexer of the multiplexing unit and its inverted signal / C0 in response to an output signal from the third multiplexer. Parallel multiplier comprising a sixth multiplexer for outputting. The first, second, third and sixth multiplexers of claim 1, wherein the input signal D0 is a source input, the selection signal S is a gate input, and a drain is connected to the output terminal OUT. A first PMOS transistor; A first NMOS transistor having the input signal D0 as a drain input and the inverted selection signal / S as a gate input and a source connected to the output terminal OUT; A second PMOS transistor having the inverted input signal / D0 as a source input, the selection signal S as a gate input, and a drain connected to an inverted output terminal / OUT; And a second NMOS transistor having the inverted input signal / D0 as a drain input and the inverted select signal / S as a gate input and a source connected to the inverted output terminal / OUT. . The first PMOS transistor of claim 1, wherein each of the fourth and fifth multiplexers has a first input signal D0 as a source input, a select signal S as a gate input, and a drain connected to an output terminal OUT. ; A first NMOS transistor having the first input signal D0 as a drain input, the inverted selection signal / S as a gate input, and a source connected to the output terminal OUT; A second NMOS transistor having a second input signal D1 as a drain input, the selection signal S as a gate input, and a source connected to the output terminal OUT; A second PMOS transistor having the second input signal D1 as a source input, the inverted selection signal / S as a gate input, and a drain connected to the output terminal OUT; A third PMOS transistor having the inverted first input signal / D0 as a source input, the selection signal S as a gate input, and a drain connected to an inverted output terminal / OUT; A third NMOS transistor having the inverted first input signal / D0 as a drain input, the inverted select signal / S as a gate input, and a source connected to the inverted output terminal / OUT; A fourth NMOS transistor having the inverted second input signal / D1 as a drain input, the selection signal S as a gate input, and a source connected to the inverted output terminal / OUT; And a fourth PMOS transistor having the inverted second input signal / D1 as a source input and the inverted select signal / S as a gate input and having a drain connected to the inverted output terminal / OUT. Parallel multiplier. 2. The apparatus of claim 1, further comprising: first storage means for storing the n-bit multiplicand and outputting the multiplier to the bit preprocessing means; And second storage means for storing the m-bit multiplier for a 2-bit scan operation on the multiplier of the bit pre-processing means. The data compression method according to claim 1 or 4, wherein the bit preprocessing means performs a logical multiplication on the first bit (b ₀ ) of the scanned two-bit multiplier and the least significant bit (a ₀ ) of the n-bit multiplier. A first AND gate outputting the processing signal G ₀ of the means; And a plurality of bit carry signals (C _{i-1) by} performing logical operations by receiving two bits each while moving in the upper bit direction by one bit from the scanned two-bit multiplier b ₁ b ₀ and the least significant bit of the multiplier. And a plurality of logic operation means for outputting the plurality of processing signals (G _i ). 6. The parallel multiplier according to claim 5, wherein said logical operation means is made of the same number as the number of bits of said multiplicand. 6. The second logical unit of claim 5, wherein the logical operation unit receives and logically multiplies a second bit (b ₁ ) of the scanned two bits and a lower one bit (a _i-1 ) of the two bits of the multiplier. And gates; A third AND gate which receives the first bit (b ₀ ) of the scanned two bits and an upper one bit (a _i ) of the two bits of the multiplicand by AND; A fourth AND gate receiving the multiplied multiplier (b ₁ b ₀ ) of the two bits and the two bits (a _i a _i-1 ) of the multiplier and performing an AND operation to output the bit carry signal (C _i-1 ); And an exclusive OR gate receiving the output from the second and third AND gates and performing an exclusive OR to output the processing signal (G _i ).