JPH05265710A - Rounding operation circuit - Google Patents

Abstract

PURPOSE:To perform O-cutting/1-raising rounding processing of the positive- negative symmetry at a high speed. CONSTITUTION:A 1st decoder 21 inputs a 2nd input signal 12 and outputs the 1st and 2nd decoding signals 13 and 14. A selection circuit 23 outputs the signal 13 as an output signal 16 when the most significant bit 15 showing the code of a 1st input signal 11 is equal to '0' and outputs the signal 14 as the signal 16 when the bit 15 is equal to '1', respectively. An arithmetic logical operation circuit 24 adds both signals 11 and 16 together and outputs this addition result as an output signal 18. A 2nd decoder 22 inputs the signal 12 and outputs a 3rd decoding signal 17 in response to the value of a prescribed table. Then, a mask circuit 25 secures the AND of the signal 17 with the signal 18 and outputs the rounding result as an output signal 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rounding arithmetic circuit for performing positive / negative symmetrical rounding to zero rounding to an arbitrary rounding position in an arithmetic unit of a signal processor.

[0002]

2. Description of the Related Art As a simple rounding operation processing method for a value represented by two's complement, there is known a rounding to 0 rounding 1 in which a bit at a rounding position is incremented by 1 and a bit higher than the rounding position is cut out. In this method, for example, for the 8-bit positive number "00001011", the rounding position is 1 from the LSB.
When it is set as a bit, the bit at the rounding position is “1” and the other bits are “0”, which is “00000010”, and the upper 6 bits in the addition result “00001011” are cut out to obtain “00001100”, For a negative bit number "11110110", the same "00" as a positive number
By cutting out the upper 6 bits in the addition result “11111000” with “000010”, “111110” is extracted.
To get 00 ".

However, in this processing method, the center of the rounding shifts in the negative direction by LSB / 2 regardless of the rounding position.
It has been reported that the time average of the error does not become 0 even if the probability of occurrence of data is positive / negative. Reference: Mochizuki et al.,
"Inverse DCT operation in VISP-LSI for moving image processing" 19
See 1990, Shin-Gaku Spring University, A-192.

In this document, as a method of solving this problem, positive / negative symmetrical 0 rounding 1 rounding is proposed. This selects the value to add according to the sign of the target data,
The center of rounding for positive numbers is LSB / 2 in the negative direction, and the center of rounding for negative numbers is LSB / 2 in the positive direction. This is a method in which the time average is set to 0.

In this method, for example, an 8-bit positive number "0"
When the rounding position for 0001011 "is the first bit from the LSB, the bit at the rounding position is" 1 ", and the other bits are" 0 ".
"00001100" is obtained by cutting out the upper 6 bits in "0001101", and an 8-bit negative number "1" is obtained.
For 1110110 ", the bits lower than the rounding position are" 1 "and the other bits are" 0 ", which is" 0000000 ".
Higher 6 in addition result "11110111" with 1 "
"11110100" is obtained by cutting out the bit.

Next, a conventional rounding operation circuit will be described based on Japanese Patent Application No. 2-199552 with reference to FIG. 3 and Table 1. In FIG. 3, 11 is the first input signal and 12
Is a second input signal, 13 and 14 are first and second decoded signals, 15 is the most significant bit of the input signal 11, 21a is a decoder, 23 is a selection circuit 3 is an arithmetic logic operation circuit (AL
U) and 16 are outputs of the selection circuit 23, and 18 is an output of the ALU 24.

Table 1 below shows the second input signal 12 when the rounding position for the 8-bit first input signal 11 is designated by the 3-bit second input signal 12 in FIG. The corresponding first and second decode signals 13 and 14 are shown.
In this table, the first column shows the second input signal 12,
The second column shows the first decoded signal 11 and the third column shows the second decoded signal 14.

[0008]

[Table 1]

Next, the operation of this circuit will be described. The decoder 21a receives the second input signal 12 and outputs the first and second decoded signals 1 corresponding to the values of the input signal 12 shown in Table 1.
3 and 14 are output. The selection circuit 23 outputs the decode signal 13 as the selection signal 16 when the most significant bit 15 indicating the sign of the first input signal 11 is “0”, and outputs the decode signal 14 when the most significant bit 15 is “1”. Selection signal 16
Output as. The arithmetic logic operation circuit 24 adds the signal 11 and the signal 16 and outputs the addition result 18.

[0010]

In the above-described conventional rounding operation circuit, in order to obtain a positive / negative symmetrical rounding-down 0 rounding result, the addition result signal 18 in FIG. It is necessary to cut out the upper bits. Therefore, in order to obtain the actual rounding result, in addition to the addition instruction in the above-described embodiment, an instruction for cutting out the bits higher than the rounding position is required, which has a drawback that high-speed processing cannot be performed.

The object of the present invention is to eliminate these drawbacks.
It is to provide a rounding operation circuit that enables high-speed operation processing.

[0012]

SUMMARY OF THE INVENTION The structure of a rounding arithmetic circuit of the present invention is such that a second input signal designating a rounding position of a first input signal represented by two's complement is inputted and a bit at the rounding position is inputted. Is a "1" and the other is a "0", the second decoder outputs a second decoded signal, and the second input signal is input, and bits higher than the rounding position are "1" Is a second decoder for outputting a third decoded signal which is "0", and these first and second decoded signals are input, and when the most significant bit of the first input signal is "1", the second decoder A selection circuit for outputting the second decoding signal and outputting the first decoding signal when the most significant bit of the first input signal is "0"; and an output of the selection circuit and the first input signal. An arithmetic circuit for performing these additions as inputs, and this arithmetic circuit A mask circuit that receives an output and the third decode signal and outputs a logical product result for each bit is provided, and positive / negative symmetrical 0 rounding 1 rounding is performed with respect to an arbitrary rounding position. And

[0013]

1 is a block diagram showing the configuration of a first embodiment of the present invention. In the figure, the second decoder 22 that outputs the third decoded signal 17 from the second input signal 12 as compared with the conventional example, and the AL by the decoded signal 17
A mask circuit 25 for masking the U output signal 18 is added.

The following Table 2 corresponds to the second input signal 12 when the rounding position for the 8-bit first input signal 11 in FIG. 1 is designated by the 3-bit second input signal 12. The first and second decode signals 13 and 14 and the third decode signal 17 are shown. In this table, the first column shows the second input signal 12 and the fourth column shows the third decoded signal 17.

[0015]

[Table 2]

The operation of this embodiment will be described below. The first decoder 21 receives the second input signal 12 as an input and outputs first and second decode signals 13 and 14 corresponding to the values of the input signal 11 shown in Table 2. The selection circuit 23 outputs the decode signal 13 to the output signal 16 when the most significant bit 15 indicating the sign of the first input signal 11 is “0”, and outputs the decode signal 14 when the most significant bit “1”. Output to 16. The arithmetic logic operation circuit 24 adds the signals 11 and 16 and outputs the addition result as an output 18. The second decoder 22 receives the input signal 12 as an input and outputs the third decoded signal 17 corresponding to the value of the input signal 12 as shown in Table 2. The mask circuit 25 takes the logical product of the output 18 and the decoded signal 17 and outputs the rounded result as the output 19.

With the above circuit, it is possible to execute a positive / negative symmetrical 0 rounding 1 rounding operation.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. In FIG. 2, the decoder 21a is different from that of FIG. 1 and the second decoder 22 is eliminated.

The following Table 3 corresponds to the second input signal 12 when the rounding position for the 8-bit first input signal 11 in FIG. 2 is designated by the 8-bit second input signal 12. The first and second decode signals 13 and 14 are shown. In this table, the first column shows the second input signal 12, the second column shows the first decoded signal 13, and the third column shows the second decoded signal 14. The present embodiment does not require the second decoder 22 as compared with the first embodiment, and therefore has the effect of simplifying the configuration.

[0020]

[Table 3]

Next, the operation of this embodiment will be described. The decoder 21a receives the second input signal 12 and outputs the first and second decoded signals 1 corresponding to the values of the input signal 12 shown in Table 3.
3 and 14 are output. The selection circuit 23 outputs the decode output 13 as the output signal 16 when the most significant bit 15 indicating the sign of the first input signal 11 is “0”, and outputs the decode output 144 when the most significant bit 15 is “1”. Output signal 1
Output as 6. The arithmetic logic operation circuit 24 adds the signal 11 and the signal 16 and outputs the addition result as an output signal 18. The mask circuit 25 receives the signal 18 and the input signal 12
And the rounded result is output as an output signal 18.

With the above circuit, it is possible to execute positive / negative symmetrical 0 rounding 1 rounding operation.

[0023]

As described above, according to the present invention, it is possible to execute the positive / negative symmetrical 0 rounding 1 rounding operation used in the above-mentioned signal processing, which is effective for maintaining the operation accuracy. There is an effect that the rounding process can be executed by one instruction.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional rounding arithmetic circuit.

[Explanation of symbols]

 11, 12, 17 First, second and third input signals 13,14 First, second decoded signal 15 Most significant bit of first input signal 16 Selection circuit output 18 Arithmetic logic operation circuit output 19 Mask circuit Output (output signal) 21, 22 First and second decoders 23 Selection circuit 24 Arithmetic logic operation circuit 25 Mask circuit

Claims (2)

[Claims] 1. A second input signal, which designates a rounding position of a first input signal represented by a two's complement, is inputted, and the bit at the rounding position is "1" and the other bits are "0". A first decoder that outputs a second decoded signal, and the second input signal that is input and the upper bits of the rounding position are "1"
And a second decoder which outputs a third decoded signal which is otherwise "0" and these first and second decoded signals are input, and the most significant bit of the first input signal is "1". A selection circuit that outputs the second decoding signal and outputs the first decoding signal when the most significant bit of the first input signal is "0"; and an output of the selection circuit and the first input. An arithmetic circuit that receives signals and inputs them and adds them, and a mask circuit that outputs the output of this arithmetic circuit and the third decode signal and outputs a logical product result for each bit are provided. Positive and negative symmetry 0
A rounding operation circuit characterized by rounding down to one round. 2. The second input signal is a signal in which the upper bit of the rounding position of the first input signal is "1" and the other bits are "0", and this is used as a third signal of the mask circuit. The rounding operation circuit according to claim 1, wherein the second decoder is eliminated by using a decode signal.