JPS61129963A - Signal output circuit for charge transfer device - Google Patents

Abstract

PURPOSE:To eliminate a noise component at reset by forming a diffusion layer having the same capacitance as that of a diffusion layer on which a signal electric charge is stored to a CCD, resetting the two diffusion layers at the same potential simultaneously and detecting a difference voltage. CONSTITUTION:The diffusion layer 22 having the same capacity as that of the diffusion layer 16 on which a signal electric charge is stored finally and an output gate 20 to which a gate potential VG the same as that of an output gate 14 is applied are formed on a P-channel silicon substrate 12 constituting a CCD10, the layers 16, 22 are connected to a reset gate 28 via gates 24, 26 to input a voltage generating in diffusion capacitances CD, CDa of the layers 16, 22 to a differential amplifier 30. Then the noise component due to the fluctuation of the amplitude of a reset voltage VR or a reset pulse phiRS fed to the gate 28 is fed in-phase to both the capacitors CD, CDa, then a CCD signal voltage VOS without the noise component is obtained at an output terminal of the amplifier 30.

Description

TECHNICAL FIELD The present invention relates to a signal output circuit, and specifically relates to reducing noise in the output section of a charge transfer device using a charge coupled device (hereinafter referred to as COD).

BACKGROUND ART For example, there is a COD transfer device that uses a floating diffusion type amplifier in the signal output section. This amplifier accumulates the signal charge transferred from the charge coupling section in its diffusion capacitance, and applies a voltage corresponding to the accumulated charge to, for example, a MOS FET.
It is detected by an amplifier composed of high input impedance elements such as. The accumulated charge in the diffusion capacitance is reset by a reset transistor connected to a predetermined reset voltage prior to charge injection from the charge coupling section.

By the way, if this reset voltage or the amplitude of the reset noculus for driving the reset transistor changes for some reason, the level of the reset state in the diffusion capacitance changes accordingly. The level of the signal received will also vary accordingly, and the signal will contain noise.

For example, an imaging device using such a charge-coupled device is provided with various timing generation circuits for driving the device, which generate periodic noise due to frequency division from the fundamental oscillation frequency. This noise causes the amplitude of the reset voltage and reset pulse mentioned above to fluctuate, and as a result,
The video signal read out from now on will also contain noise due to the above-mentioned recess and Trepel fluctuations. Since this noise has periodicity, the video reproduced from the video signal will contain visually unsightly static noise. -Object of the present invention is to provide a signal output circuit for a charge transfer device that eliminates the drawbacks of the prior art and improves the S/N ratio at the output section.

DISCLOSURE OF THE INVENTION The present invention provides a C
A second diffusion layer having substantially the same capacity as the first diffusion layer formed on the substrate surface of the OD is formed on the same substrate surface of the CCD, and the diffusion capacitance of these two diffusion layers is substantially reduced. By resetting at the same potential and at the same time and using a differential amplifier to detect the difference between the voltages generated across these two diffused capacitors, the noise component generated when resetting the diffused capacitor where signal charges are accumulated can be eliminated. It is to be removed.

DESCRIPTION OF EMBODIMENTS For a better understanding of the present invention, prior to a detailed description of the present invention, the configuration of a signal output circuit of a charge transfer device using a so-called floating D7 type sense amplifier in the output section according to the prior art will be described. Explain. Referring to FIG. 3, this example describes a two-phase drive type CCD, and the surface of the P-type silicon substrate 12 constituting the CCD 10 has data for forming charge transfer paths. An array of electrodes 11 is formed. An output f-) 14 is formed adjacent to the date electrode 11 at the end of the array, and an N-type diffusion layer 16 is formed adjacent thereto.

This diffusion layer 16 is connected to a power supply through a reset circuit (In'-) 18 so that a reset voltage vR is applied thereto, and the voltage appearing on the diffusion capacitance CD due to the diffusion layer 16 is input to a buffer amplifier fA1, More CCD
It is configured to be taken out as an output voltage v08 of 10.

Note that a constant dart voltage v0 is always applied to the output boot 14, and the output date 14 is in an open state.

In the above configuration, when horizontal transfer pulses φH1 and φH2 are applied to each gate electrode 11 at the timing shown in FIGS. The accumulated signal charge Q is sequentially transferred toward the output dart 14 and sent to the diffusion capacitance CD formed by the diffusion layer 16 via the output boot 14. This appears as a voltage Q/CD in the diffusion capacitance CD. Then, the voltage Q/CD is input to the buffer amplifier 7'A1, and the output voltage v0. is extracted as.

On the other hand, the diffusion capacitance CD (already charged to Q/CD) is reset dirt 1 as shown in Fig. 4(c) K.
8 is reset to the reset voltage VR in synchronization with the reset pulse φR8 that is periodically applied to the reset voltage VR (for example, at time t
). Next, the date electrode 11 adjacent to the output r-t 14
Horizontally so that the potential well formed near the surface of the lower silicon substrate 12 is shallower than the potential well formed near the surface of the silicon substrate 12 under the dirt electrode one step before the r-) electrode. Transfer Noculus φH1,
At the time when the level of φH2 changes (for example, time tz),
The signal charge Q1, which had been accumulated near the surface of the substrate 12 of the y-toe electrode 11 at the end, is sent to the diffusion capacitor CD.

In a conventional charge transfer device having such a configuration, when the amplitude of the reset voltage v8 or the reset voltage v8 or the reset gate 18 (i4 pulse φR8) changes,
Due to these fluctuations, the lysée and trepel fluctuate, causing noise. This reset voltage VR or reset voltage φ
If the amplitude fluctuation of R8 is, for example, an intrusion noise from the timing signal generation circuit that generates the synchronization signal of each circuit section, it becomes periodic noise, and when the charge transfer device is used in an imaging device such as a television camera. There was a problem with fixed pattern noise on the image.

Next, embodiments of a signal output circuit of a charge transfer device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows the configuration of an embodiment of a signal output circuit of a charge transfer device according to the present invention.

The difference between this embodiment and the conventional example in terms of its structure is that, in addition to the diffusion layer 16 in which the transferred signal charges are eventually accumulated, a second diffusion layer 22 is provided which has substantially the same capacitance. , output f-
1-14 is applied to form a filter chip 20, and these diffusion layers 16, 22.
are connected to the reset circuit 9-28 via darts 24 and 26, respectively, and the voltages generated in the diffusion capacitances CD, C, by the diffusion layers 16 and 22 are connected to the non-inverting input 32 and the differential amplifier 30, respectively. This is because the signal is input to the inversion input 34. As a result, the differential amplifier 30 outputs a voltage equal to the difference between the two voltages 32 and 34. The other configurations may be completely the same. Note that the output gate 20 is connected to the second. Since the capacitance of the diffusion layer 20 is provided to be substantially the same as the capacitance of the first diffusion layer 16 including the output r-t 14, it is assumed that these capacitances are substantially the same. Although not necessarily necessary, it would be advantageous to provide the output 20 as follows.

That is, the second diffusion layer 22 and the output dirt 20 can be formed with substantially the same shape and impurity concentration as the first diffusion layer 16 and the output r-) 14, which is advantageous in terms of design and manufacturing process. Ru.

In the above configuration, signal charges Q are formed adjacently under each gate electrode 11 by applying horizontal transfer pulses φMl and φH2 to each dart electrode at the timings shown in FIGS. 2(a) and 1(b). The data is sequentially transferred to the MO8 capacity. Since the output dart 14 is always open, this charge Q is finally transferred to the diffusion layer 1-CD by the diffusion layer 14 and accumulated therein.

Then, after a certain period of time has elapsed, for example at time t1o, the gate A? The gates 24 and 26 open by applying the force φT (Fig. 2(d)).
, diffusion capacitors CD and CDa are connected in parallel to each other. Thereafter, a reset signal φR8 is applied to the reset gate 28 (FIG. 2(C)), and the reset gate 28 opens, so that at time t, the diffusion capacitances CD and C are applied.
Da is reset to the level of reset voltage vR. Next, the potential well formed in the vicinity of the surface of the silicon substrate 120 under the dirt electrode 11 adjacent to the output chip 14 is transferred to the silicon substrate 120 under the dirt electrode one side in front of the date electrode 11 (on the signal charge transfer side). For example, from time t1 □, the levels of horizontal transfer signals φH1 and φH2 change so that they become shallower than the potential well formed near the surface of the substrate 12.
Transfer of the signal charge Q2 accumulated near the surface of the substrate 12 to the diffusion capacitor CD is started, and the transfer operation ends at time t13.

During the above operation, the voltages generated across the diffusion capacitors C8 and CDIL are always input to the differential amplifier 30. Here, diffusion layer 1
The signal charge Q is transferred only to the diffusion capacitance C8 by 6.
In other words, the signal voltage Q/CD is generated, but noise components due to fluctuations in the amplitude of the reset voltage vR applied to the reset gate 28 or the reset pulse φFtS are applied to both the diffusion capacitors CD and CDa in the same phase. Therefore, the output terminal of the differential amplifier 30 has a reset point 28.
The CCD signal voltage v0. from which noise components due to fluctuations in the amplitude of the reset voltage or reset pulse applied to v0. (Fig. 2(e)) is obtained.

Further, thermal noise generated when the reset gate switches is also applied to both of the diffusion capacitances Cp y Coa in the same phase, so that it is similarly removed.

In the embodiment described above, the darts 24, 26° 28 and the differential amplifier 30 are formed on the same P-type silicon substrate 12 like other elements, but the present invention is not limited to this, for example, As shown in Figure 5, the diffusion capacitance CD, CD
The voltage generated at a is connected to two buffer amplifiers 40 and 42 formed on the same substrate 12 in the same way as other elements.
It may be configured to output from terminals 44 and 46 via. In this case, the two outputs 44.degree.
6a. In this case as well, the same effects as in the embodiment shown in FIG. 1 can be obtained.

Effects As explained above, according to the present invention, when periodically resetting the diffusion capacitance in which transferred signal charges are finally accumulated, noise caused by fluctuations in the reset voltage, reset cruise amplitude, etc. Since this component can be removed, the S/N ratio at the output section of the charge transfer device can be improved. Also, when this charge transfer device is applied to an imaging device, it is possible to remove the fixed i4 turn noise that is easily noticeable in reproduced images. , the image quality can be improved.

[Brief explanation of the drawing]

1 is a circuit diagram showing the configuration of an embodiment of the signal output circuit of the charge transfer device according to the present invention; FIG. 2 is a waveform diagram showing the operation of each part of the signal output circuit shown in FIG. 1; Figure 4 is a circuit diagram showing the configuration of a signal output circuit of a conventional charge transfer device, Figure 4 is a waveform diagram showing the operation of each part of the signal output circuit shown in Figure 3, and Figure 5 is another embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a signal output circuit according to an example. l O... CCD 12... P-type silicon substrate 14.20... Output r-to 16.22... Diffusion layer 24.26... r-to 28... Reset gate 30... Differential amplifier, patent applicant Fuji Photo Film Co., Ltd. 1°.

Claims (1)

[Claims] First capacitor means formed at the end of a charge transfer path for transferring charges in a semiconductor substrate and for accumulating signal charges transferred through the transfer path; and a reset for resetting the first capacitor means. and means;
In a signal output circuit of a charge transfer device that outputs a signal corresponding to signal charges transferred through the charge transfer path, the circuit is formed on the substrate and has substantially the same capacitance as the first capacitance means. , a second capacitor means that can be reset by the reset means, and a voltage generated in the first and second capacitor means;
differential circuit means for outputting a voltage of the difference between the voltages, and the reset means simultaneously resets the first and second capacitance means at substantially the same potential. Signal output circuit.