JPS61129625A - System for controlling semicontrast image display liquid crystal display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a small portable combiator, and particularly to a display device and a display control device used in such a combiator.

[Technical background of the invention]

In recent years, the spread of small comviators and personal comviators has been remarkable. Compared to the combiators of just ten years ago, the seven-part combiator has had much more processing power at a fraction of the size.

Many of today's novel computer assemblies offered by leading manufacturers are based on the same or similar central processors fabricated as one or more integrated circuit chips using LSI or '/L'8 I. The device (CPU) is adopted.

This makes the CPU, in some respects, the current standard for this industry. Accordingly, one or more advanced operating systems have been developed for each CPU and are commercially available to users of personal combiators. Therefore, a standard CPU and operating system combination provides sufficient processing speed and flexibility for most personal combiator users.

With the standardization of CPt7 and operating systems, manufacturers of personal computer devices are focusing on other characteristics of personal computer devices to differentiate them among the available computer devices and increase their market share. It is becoming possible to improve it. Manufacturers have developed specialized data entry/editing equipment, peripherals, color graphics capabilities, and advanced application software programs.

However, with a few exceptions, all personal computer computers use CRT displays, whether specialized CRT displays or connected to standard television sets. CR'r has good resolution, can display in color, and can display more characters on the screen.

However, when using a C'RT display device, the downward size of the personal combiator is limited, and most of the CR'l's are very large, which hinders portability of the combiator and display device. It becomes. Some manufacturers offer displays with liquid crystal display (LCD) devices. LCDs are much smaller than CRTs and therefore lend themselves to the portability of personal combinatorics.

[Problems with background technology]

However, there are several drawbacks to using LCD displays. One is that the number of characters that can be displayed on the L,CD screen is very small compared to the CR'I' display device. or,
t, cD%llK character cells are generally square, whereas CRT character cells are square or rectangular long in the width direction or height direction. Also, LCDs cannot display colors like CRTs. The differences in the operating characteristics of CRT and LCD devices pose important problems. for example,
For example, for a personal combination with C'RT - Taka LC
D. Even if the personal computer has the same configuration as the personal combiator, i.e., the same CPU, the same operating system, and the same peripherals, the personal computer with an LCD will not allow programs to use the display device. If you have a CRT, you cannot run programs written for personal computers. This is a serious problem. This is because you need to modify the application software program or
This is because a program must be created for the comviator which has a separate LCD device. Therefore, there is no compatibility between comviators having an LCD and comviators having a CRT, which is disadvantageous in terms of market strategy for manufacturers of combiators having an LCD.

Therefore, heretofore, there has been no small, easy-to-operate portable comviator with an LCD that allows application software programs written for comviators with C'RT to be used without modification.

[Purpose of the invention]

An object of the present invention is to provide a portable combiator that is small and easy to operate.

Another object of the invention is to provide a compact display device for a portable combinator.

Another object of this invention is to provide a portable computer with a liquid crystal display made for comviators with CRTs and compatible with nine soft square programs.

Another object of the invention is to provide a portable combiator having a standard CRT display and a liquid crystal display for displaying the number of characters to be turned.

Another object of the invention is to control a liquid crystal display device to display a half-tone image.

C. SUMMARY OF THE INVENTION In the present invention, a first control circuit transfers display data from a screen image RAM to a multi-digit liquid crystal display such that the display data is simultaneously transferred to each segment of the display. The second control circuit converts the ASCII code data into screen image data using the font pattern RAM. This system was written for CRTs, operated under the control of a nine soft square program, and is capable of color display emitters.

[Embodiments of the invention]

FIG. 1(a) is a perspective view of a combinator using the present invention. For this combination, the main body part 11 and the display part 1
It has 3. This display section 13 is hingedly attached to the main body section 11, and displays a closed state, that is, a folded state. The miniaturization of computers and display devices has made them portable.

The combiator with the display section 13 in the operating position is the first
(b) As shown in the figure. The LCD device 15 is the display section 13
contained within. This LCD device 1t15 is a general CR
Although it displays the same number of characters as T, for example 25 lines x 80 characters, it is much smaller than the conventional combiator CRT display.

A keyboard 17 is provided on the lower front side of the LCD display device 15. When the display section 13 is closed, it becomes a protective cover that covers the keyboard 17.

FIG. 1(C) is a side view of the combiator with the display section 13 in the operating position. The support member 19 is attached to the main body 1 so that the keyboard 17 is positioned for optimal operation.
I support 1. two floppy disk drives 21
is located within body portion 11 and provides compatible storage capabilities for the comviator.

i 2 (a) is a block diagram showing a combinator system embodying the present invention. This combiator system has a processor 201, and this processor 20
1 is connected to an internal bus 203 for bidirectional transfer of data and control signals. This processor 201 is, for example, a model 8QC88 microprocessor manufactured by Isochil Corporation in the United States. This microprocessor has both random access memory (RAM) and read-only memory (ROU), which are used during the operation of the microprocessor and are
73-86 Can also be used with operating systems.

Peripherally, the computer system includes a keyboard and disk storage subsystem, each of which is separately connected to an internal bus. A suitable disk subsystem includes one or more small floppy disk drives 21 as shown in FIG. 1(C).

Liquid crystal display device (LCD) z 09 is a display control circuit 211
It is connected to the. This display control circuit 211 transfers data to be displayed and control signals to the LCD 2091C.

Next, the LCD z o'y sends a status signal to the display control circuit 211 along with a signal identifying the display format.

The display control circuit 211 is connected to the internal bus 203, and bidirectional signal exchange is performed. Display memo IJ 213
It is also connected to internal bus 203 and display control circuit 211 . As will be clear from the description below, data displayed on the LCD 209 can be stored in and read from the display memory 213 (by the display control circuit 2111C).

Processor 201 can also transfer data directly to display system 213 via internal bus 203.

FIG. 2(b) shows an exhibition control circuit 211 and a display device 21.
3 is a more detailed block diagram of FIG. As embodied here, the display control circuit 211 has a first LC'D control circuit 219. This first LCD control circuit 21
9 displays the display data from the display memory 213 on the LCD 2
Transfer to og. The status signal generated by the LCD 209 is transmitted from the LCD 209 to the first LCD control circuit 2.
Transferred to 19.

The second LCD control circuit 217 is connected between the internal bus 203 and the display memory 213, and is connected to the display memory 2°13.
Control when storing SCII code display data and AB
CI! Controls the conversion of knee 1 display data into screen image data suitable for display on the LCD 209.

The display memory 213 is divided into three sections.
Consists of M. In other words, the ASCII code RAM 221 stores the data displayed in the LCDKCD format, and the ASCII
I code RAM 221 IC is also a screen image RAM that stores all or part of the stored data in a format suitable for display on the LCD 209.
223, and a 7-onto-pattern RAM 225 that stores conversion data used when converting A3C0 code data into screen image data.

As will be described later, the second LCD control circuit 217 has a number of internal registers, which are accessible by the processor 201 and which control the LCD 209.
used to define and control One of these registers is an index register (not shown) that is used as a pointer to a memory location that stores the location of other registers. This index register is a register loaded by processor 201 by executing an OUT instruction. To load other registers, the index register is first loaded with the appropriate register address, the data register (not shown) is loaded with the information to be stored in the selected control register, and the OUT instruction is processor 20
1 is executed.

The table below shows the control registers and the values stored in these control registers for implementing and controlling the different modes of operation of the CD 209.

Register 1w Description Re Rate RI W Horizontal display (characters) R2 亭R3 亨R4 NING R5 NING R6W Vertical display (characters) R7 ￨R8* R9w 猷 scan line address (scan line) RIOW 'i,:''';4: '
EJJ'; Carrier/line address R11W
Cursor end scan line address (scan line) R12F, /v Start address (upper) R
13R/V Start address (lower) R14PA
W Carson dress (upper) R15vW Carson dress (lower) R16* R17 R18W Operation mode R19W Scan interface select R
20W Flashing interval select R21W
Underline position (scan line) R2
2W Font select R23W Background (R8) color table R24tll' Image memory start address (higher order) R25W Image memory start address (lower order) R28W Video RAI7 address mask R27W Test mode R28W Test status lR29W
Test status 2 R30W data loopback (higher order) R31
W Data loopback (low order) The rate in the table above indicates that it is currently not used.

The functions and meanings of the nine signal values stored in the control register will now be described.

R1: Horizontal display 7-0: Total number of characters displayed horizontally.

The range is 2 to 0FFf (0 stored The value is the actual screen size (low 40 in resolution mode. High resolution mode 80), an error occurs. 10 R6: Vertical display 7-0: Total number of characters displayed vertically.

Range is 2 to oFrao. Error if the stored value does not match the appropriate screen size (25 lines). R9: Maximum scan line address bits 7-4 Ignore bits 3-01 Less than the number of scan lines for the character. Stores the value corresponding to the number of lines. Range is 0 to Op'H0 RIO: Cursor start scan line bits 6-5
Controls enabling or disabling of the display cursor.

Bit 6 Bit 5 0 0 Cursor displayed 0
1 No cursor display 1 0 Cursor display 1 1 No cursor display bit, ignore bit 3-0 Cursor start scan line range is 0 to 0FFH6 Stored value is from bits 3-0 of R9 (character scan line size) When large, this kernel is not displayed.

R11; Cursor end scan line (write only)
Bits 7-4 Not ignored.

Bit 3-0 Cursor end scan address O Range is O to 0FFH The stored value is R10 (cursor star) Bits of scan buttresses When the number is smaller than 3-0, the cursor is Cannot be displayed.

R12: Character/image/text start address is upper (read/write) Bits 7-6 Ignored when written and returned to zero when read.

Bits 5-0 Upper 6 bits of character/image Ikufa's conflict start address.

R13: Character/Innodino (The start address of the Tufa register is lower (read/write) Bits to O Character/Innodino (The lower 8 bits of the relative start address of the Tufa register. The relative start address of the Tufa register is 14. Since the pivot width is 16 bytes, the character/innovation area can be accessed.

R14: Upper cursor address (read/f included)
Bits 7-6 Ignored on write, return to zero on read.

Bits 5-6 Upper 6 bits of cursor relative address.

R15: Lower cursor address (read/write)
Bits 7-0 Lower 8 bits of cursor relative address.

Relative address of cursor register is 14 bits wide.

That's why I have a part-time job at 16. data/image buffer area is accessible. this cursor If the address is off screen cursor is not displayed.

R18: Operating mode (write only) bit 7 Controls recognition of character attributes in character mode. When it is 0, black and white mode is selected. When set to 1, the color (emission range 1) mode is selected.

Bit 6 Enables color/image buffer scan function or controls disk pull. When 0, the scan function is disabled.

When 1, the scan function is enabled. When the main processor is changing the mode register of the second CD controller, the scan function is disabled (disabled) to prevent destruction of data stored in the screen image screen M223, ie, the video buffer.

Bit 5 When this bit is 0, the maximum scan line address for R9 is a prolog 2 mapple. When this bit is 1, the maximum scan line address is set to 7 (the R9 "OUT" instruction is ignored) rather than the prolog 2 mapple.

Select monochrome display mode This bit is set.

Bits 4-3 Ignored.

Bits 2-0 Code/Image Buffer Scano Address Mask Hit. The code/image buffer address is equal to the AND value of this mask value and the scan address register (14 bits). This feature allows changing the code/image buffer address structure.

R19: Scan interval select bits 7-4
It will be ignored.

3-0 If the time wait between each plane of the display unit 209 is 0, the first LCD controller 219 does not wait between scans of each plane.

R20: Flink interval select bit 7
Select the basic clock for pixel blinking. When 0, the character tab link timing is synchronized to the m2 LCD controller 217 scan frame y lock (not shown).

When 1, character printer lid Iminoji is a character/image Synchronized to buffer scan clock do.

Bits 6-4 are ignored.

Bit 3-2: Controls the fast blink cycle.

The blink cycle is specified as follows. determined.

Bit 3 Bit 2 Divisor 1
1 1/1 e bits 1-0 Control slow blink cycle.

The blink cycle is specified as follows. determined.

Bit 1 Bit 0 Divisor 0
0. 1/32R21: Under 2-in position and overscan write prevention pit 7
It will be ignored.

Bit 6-4 Image Memory Scan Limit Address This feature prevents the screen image RAM 209 from being overwritten when the mode register changes.

Bit 3: Underlined rask address. Range is 0 to OF
If the value stored in H is greater than the maximum scan line address of R9, the underline disappears.

R22: Address of font select and button 7-4 font pattern RAM 225. This bit string is used for bits 12-15 of the font RAM j 25 address.

Bit 3 Selects highlight mode function. When the stored value is 0, bit 11 of the address for font addressing is pit 1 of R22. (See below) When the stored value is 1, pit 11 of the font addressing address selects the character attribute 1 bit 2 highlight mode function. When the stored value is 0, fast blinking is disabled.

When the stored value is 1, fast block Link is enabled.

When bit 3 of bit IR22 is 0, bit 11 of the font addressing address is set to the same value. When bit 3 of R22 is 1, it is ignored.

When the scan line value of bit OR23 is 7 or less,
Used as bit 1G of the font selection address.

R23: Background color table bits 7-0 When the color mode is selected (when bit 7 of R18 is 1), part of the background color of the character attribute is decoded into this pit array.

Background attribute Background color reference pit RB () 000 bit 0 001 bit 1 0 1 0 bit 2 oti bit 3 100 bit 4 101 bit 5 1 1 0 bit 6 1 1 1 bit 7 Note Reference pit = 0 White background = 1 Black Background (reverse video) R24: Image buffer start address upper (write) bits Ignored bits 6-0 Image buffer start address least significant bits R25: Image buffer start address lower (write) bits 7-0 Image Bottom pit of buffer start address R26: Display memory 213 address mask (IF included)
Bit 7 Enables or disables read/write access to display memory 213.

Bit 6 Ignored Bit 55-3 RA Selector 1 Processor 20
Bits 15-13 of the display memory address supplied from 1 to the display memory are flushed by this bit array.

Bit 2 - ORAM selector 2 processor 20
Bits 15-13 of the display memory address supplied from 1 to the display memory are flushed by this bit array. This results in an increase in memory address configuration.

R27: Test mode (write) Bit 7 Displays test mode. When the stored value is 00, normal mode is selected. When the stored value is 1, test mode is selected. When in test mode, memory addressing is only enabled by the scan control safe scene, and memory addressing from the pond sexy scene is ignored.

Bits 6-3 Ignored Bit 2 Controls the video RAM read cycle time. When O, the read memory cycle time is 4 machine clock cycles.

Bit 0 Controls display memory 213 write cycle time. 1, the embedded memory cycle time is 5 machine clock cycles. 1, the write memory cycle time is 4 machine clock cycles.

R28: Test status 1 (read) bits 7-0
Test bits are used for diagnostic purposes.

R29: Test status 2 (read) bit? -0
These bits are used for diagnostic purposes.

R30: Data looseback upper (read) bit 7
-0 These bits are used for diagnostic purposes.

R31: Data loopback lower (read) bit 7
-0 These bits are used for diagnostics.

Mote Control Register This is a 6-bit register with an I10 address anH.

This register controls the status of display control circuit 211 as described below.

Bits 7-6 Ignored.

Bit 5 When the stored value is 1, this bit changes the character background brightness to a blink attribute function for alphanumeric mode. If the upper attribute bit is not selected, 16 background colors (or brightness colors) are available. During normal operation, this bit is set to 1 to enable the blink function.

Bit 4 When the stored value is 1, high resolution mode (640X200) is selected for black and white graphics mode. One of eight colors can be selected (for EMI IIL range 1) with the Direct Drive set in this mode using the mono mode register or the graphic mode register.

Bit 3 When the stored value is 1, video decoding is enabled on mode change.

Bit 2 When the stored value is 0, color mode is selected. When the stored value is 1, black and white mode is selected.

Bit 1 When the stored value is 0, 320X200
Graphics mode is selected. When the stored value is 1, alphanumeric mode is selected.

Bit 0 When the stored value is 0, the 40 character x 25 line alpha annumeric mode (low resolution) is selected. When the stored value is 1, the 80 character x 25 line alphanumeric mode (high resolution) is selected.

Below is a list of modes selected by this register.

Bit 543210 Selected function 10110040X25 white, black alphanumeric 10110180X25 white, black alphanumeric
FIG. 2 is a schematic diagram of a CD 209. In a preferred embodiment, the LCD
20g has a resolution of 640 pixels in the horizontal direction and a resolution of 256 pixels in the vertical direction. LCD 209 is 2
It has a display capability of 5 lines x 80 characters. This is a common configuration for CRT displays.

Pixels 301 are grouped into each character cell 301, which in the preferred embodiment is 3018 (width)
It has a pixel array of (height). A typical character cell for an LCD device is a square pixel array, such as an 8×8 array, as shown in cell 305. Using character cells that are larger in height than width increases the reliability of the LCD device. Therefore, the preferred embodiment uses square cells. However, as discussed below, the size of the character cell is programmable to provide flexibility in the application cache. The spacing between characters and lines in the preferred embodiment is one pixel each.

In the preferred embodiment, the display memo +7213 has a capacity of 48 bytes, the A3C0 code RAM 221Vc16 bytes, and the image BJM, 22s.
4 bytes and 8 bytes in font pattern RAM 225
Bytes are allocated to . The display control circuit 211 has 4
It has two main control modes. Namely, they are a black and white character mode, a color chemise character mode, a color chemise graphic mode, and a direct bitmap mode.

In either control mode, read or write operations of display data by the processor 201 are performed via the second Lcc+controller 217. When the character display mode is selected, the second LCD controller 217 scans the AnC0 code RAM 221- every free cycle and converts the ASCII code character data according to the correlated attribute bits into the font pattern RA! The font data stored in J225 is used to convert it into screen image data. The converted display data is stored in the screen image RAM 32g. When the graphic mode is selected, the second LCD controller 217
M221K Converts the stored ASCO code graphic data into appropriate pixel image data and writes it to the screen image RAM 22J.

glLcD controller 219 uses screen image R
The pixel image data stored in the AM 22j is scanned and all image data is transferred to the LCD 209 so as to be displayed according to the LCD scan timing. The font pattern 7 RAM 225 can be accessed by the processor f201 during free time.

The final processor zo1 sends the AJC1 code display data to the @2LCD'I controller 211 in the form of two bytes, a code (or data) byte and an attribute byte. In direct bitmap mode, processor 20
1 directly displays display data in screen image RAM 22
Send 3K.

If any control mode other than the direct bitmap mode is selected and the mode register indicates monochrome mode, the second LCD controller 21'l accesses the font pattern RAM 225 and stores the ArcI image. Convert code data to pixel data,
Performs four chic operations according to the value of the attribute byte. If the mode register is set to color chemistries, the operations performed are almost the same as for black and white, but a color table is used to convert data correlated to color attributes into a black and white pattern of selected pixels. To access registers,
Attribute byte processing □ is different. When the graphics mode of Karashi Island Mileshi 1 is selected, the data stored in the A3Cr echo RAM 221 is transferred to the 7-onto pattern RAM! ,? 5 to the appropriate location in the screen image RAM 22J.

Reverse video character is screen image Rkh
1223, the second LCD controller 2z1 changes the background color to black and makes the characters white. When characters with an attribute that instructs plinking are stored in the screen image RAM 223, the second LCD controller 217 displays character data with all white character cells or reverse characters in the designated area of the display device 209. When displaying as a video, character data of all black character cells are displayed alternately.

The second LC'D controller 217 displays highlighted characters and half-gradation images. In the case of emphasized characters, the second LCD controller 21'l uses font pattern R.
A second group of font data stored in AM 215, for example bold font l, is accessed during conversion of ASCII code data to screen image data. Half-gradation is performed by changing the display of the selected character to all white pixels and visually providing a half-gradation image.

In character display mode, character data has two characters: a character code byte and an attribute byte.

Next, the definition of 2 bytes during operation in monochrome control mode is shown.

BL RG B I RG B Character Attribute BL2 Character cells and, for example, all white pixel cells defined by background are alternately displayed and the attribute blinks.

This brightness allows characters to be highlighted by selecting alternating fonts or dimmed by blinking at a rate faster than the response time of the LCD 209.

The background and foreground attributes are coded as follows.

background foreground RGB
RGB 000000 No display, filled with white pixels 00000
1 Underline 000 111 Black text/White ground 111 000 White text/Black ground 111 111 No display, filled with black pixels Next, the definition of 2-byte character data in color shemulation mode is shown.LCD 209 Naturally, the color attributes cannot be displayed in multiple colors, so the color attributes are projected onto a specific black and white combination with a programmable threshold.

BLRGB Engineering RGB Character code /Tsukuground Attribute BL of foreground characters; To alternate between normal display character cells and cells filled with specific data of all white pixels, for example, defined by )(Tsukuground) Flashing attributes.

1: Select alternate fonts for emphasis or LCD209
Highlight attributes to display characters with either flashing at a higher rate and dimming the response time.

Background: Access the color table register using the 3-bit color attribute as a bit address.

RC)B Color Table Register Bit Address 0 fil 3 If the accessed bit of the Color Table Register is O, this character cell is displayed as a black character on a white background. Conversely, if it is 1, it is displayed as white characters on a black background. The correspondence between color attribute and cell display combinations is programmable (by loading appropriate values into the color table registers). Foreground has no meaning.

The font data stored in the font pattern RAM 225 is always treated as a cell, and the display cell size is programmable. However, the cell width is fixed at 8 pixels, but can be expanded to 166 pixels (low resolution mode) using 8-pixel resolution hardware. The height of the character cell is 1
It is programmable from pixel to F.

A character cell is defined as the total space including the character body, intercharacter space, and interline space. In the font pattern RAM 225,
Eight pixel rows within one cell are treated as one byte of display data, with MBB of the one byte display data displaying the leftmost pixel on the screen, and LSB representing the rightmost pixel.

8 bytes of font pattern RAM 225 td To realize multiple font selection, l1li! 8 pixels,
It can be managed as four 2048-byte segments corresponding to 256 character patterns of 8fiii elements in height. By using character cells with a height greater than 8 pixels, two different fonts can be separated and stored in two 4096 byte segments.

The actual byte address in hexadecimal for a particular row within a display cell is generated as follows.

Address =, C6000H+ (Psi heather 1000H)
+(FSO*800H)+(ROW Z Tei 4GOof(
)+(ROWI Toru 200H)+(CD*2)+ROw
OFSI: Upper bit of the font pattern RAIJ segment selection bit, if emphasis font is enabled, this bit changes to the brightness bit.

FSO: Lower bit of font pattern RAM segment selection bit, if a character height larger than 8° pixels has been selected, this bit changes from ROW 3 K.

ROW'3-ROffO: These 4 bits represent a particular row of character cells. If the character height is less than or equal to 8 pixels, ROW3 has no meaning.

CD: An 8-bit character code that allows the identification of 256 different characters containing symbols.

In the graphics display mode, the graphics data to be displayed is handled as bytes corresponding to 8 pixels and is transferred directly to storage locations in the 16 bytes of screen image RAM 225. Screen image R
The AM 225 is divided into two segments of 8 bytes, each segment corresponding to an odd row image memory and an even row image memory. Even row image memory is 80
byte x 100 lines (line O2 line 1... line 198
), and the odd-numbered row image memory stores image data of 80 bytes x 100 rows (row 1, row 2, . . . , row 199).

1 for a specific group of 8 horizontal elements on the screen
A hexadecimal byte address is generated/seconded as follows.

At L/S=uoD(Row/2)*BAOOOH+u
oD((Row+t)/2)KyoB8000+INT(R
OW/2)*50F(+C0LIJOD INT representing Nimo JOD function: ROW representing integer function Vertical location count of a row on the screen with the topmost property on the screen being row 0.

COL: 8 when the leftmost group of 8 pixels is O
Horizontal location count in pixels.

Sections 3(b) to 3(d) schematically illustrate further features of the invention. LCD 209 is 1.2. - or may consist of 4 segments or planes. LCD 209 is displayed. However, LC! If D 209 is divided into multiple planes, as many characters as the number of planes can be transferred from screen image RAM 223 to LCD 209 in parallel.

As shown in Figure 3(b), a single plane LCD is
lines (eg 25), each line having N words (eg 80). Each word corresponds to one character displayed. Assuming that the first character to be displayed is stored at memory address A in screen image RAM 323, A+tJ-1 is the address of the last character on the first line, and A+(L-1) N is the address of the first character of the last line, and the last character of the last line is stored at address A+LN-1. Therefore, the value is the line number, and the value N is the line offset, meaning the character position within the line.

FIG. 3(C) shows an embodiment in which the LCD 209 is divided into plane A and plane B. FIG. Line 1-1 is included in plane A, and line L+1-2L is included in plane B. Data word 1 of line 1 is stored at plane offset address A, e.g. 0, and data word 1 of line L+1 is stored at plane offset address B, e.g. B:A.
+LN K is stored.

FIG. 3(d) shows an embodiment in which the LCD 209 consists of four planes: plane A1 plane B1 plane C and plane D. In this example, the maximum line offset (N) is 1/2 of the value in the embodiments of FIGS. 3(b) and 3(c). Plane A1 Plane B1 First line of plane C and plane D
The addresses of the data words are A, B =:
(L+1)2N.

c=a, D=(L+1)2N+N.

FIG. 3(e) shows the address of the screen image RAM 22J and the LCD in an embodiment in which the LCD 209 has two planes, plane A and plane B.
209 schematically shows the correspondence between addresses of 209. Plane offset address A is screen image RAM 22
Assuming that address O in J is equal, words are transferred from screen image RAM 223 to plane A of CD 209, starting at address 0 and ending at address L(N-1).

P v -y B inner Teha, 7)' l/CLN-2N
L-I K stored data words are displayed.

If the LCD 209 is composed of four planes, the plane offset addresses of planes A*B, C and D are O and N, respectively.

(L+1)N', and (L+1)N+N.

In Figure 4, the display data is stored in the screen image RAM 32.
3 is a block diagram of a first LCD controller 219 transferred from LCD 209 to LCD 209; FIG.

This block diagram shows the circuitry that generates the display location of LCD 209 for displaying data and transferring display data from screen image RAM 22J to LC'D 209.

At the start of the computer system, for example, Pro 1 is transferred to Recime 403 and Theorem 1411 δn. This control value relates to the number of planes within LCD 209 and the number of words within each plane. For example, Figure 4 shows the LCD
20g is an embodiment of the first LCD controller 219 having planes A to A. Therefore reg A 4
03 stores the plane offset A described above. The value of A is 0 if the first storage word in screen image RAM J l j stores a character that can be displayed in location 0 of row 0 of LCD 209 .

Similarly, reg B 405, reg C407 and reg D 409 are plane offset B1, plane offset C and plane offset C, respectively).
Store the value of D. These values are LC when displaying the first character of plane C1 plane B and plane D.
It corresponds to the location on D 209.

reg E411 is loaded with a value equal to the number of characters in each line of the plane. Assuming that LCD 209 displays 80 characters per row, for the embodiment of LCD 209 shown in Figures 3(b) and 3(c), reg E 411
The value stored in is 80 υ, and in Figure 3(d) ra
The value stored in g E 411 is 40.

The outputs of registers 403 to 409 are sent to multiplexer 41
3 input. Signals PLN8ELO and PLNSE[,1 control the multiplexer 413 to add the values stored in the registers 403 to 409 to the adder 415.
0 selectively outputs one input. multiplexer 41
The value output by 3 constitutes a 16-bit pace offset address for one of planes A through A.

The output of adder 415 constitutes the 16-bit address of the character ill on LCD 209 for one of planes A through A. The first value output by the adder 415 for each plane A is the L value in each plane A to
Corresponds to the first display location on CD 209 and is equal to the offset value stored in registers 403-409.

For each pond character in a line, the pace offset value must be incremented. This increment is performed by adder 417, register 419 and counter 421.
This is done by

The value stored in reg E 411 is
input. The other input of adder 417 receives the output of register 419, LINSAO-15. The output of the register 419 is further a line load signal L I
The counter 421 is loaded under the control of NELD. Register 419 stores the output of adder 417 and loads its value under control of line end signal LINEEND.

In this example, the values stored in the various registers and adders are 2. It is expressed as the complement of . First, register 4
19 and the value of the counter 421 are set to O. The value of the counter 421 is incremented by 1 based on the data ready signal DATARDYK. The occurrence of DATARDY will be described below.

For the first time, line word register 423 is loaded with a value equal to 1/2 the number of characters to be displayed on the line of each plane.

Therefore, in the embodiments of Figures g 3 (1:+) and 3(C), the stored value is 40, assuming that the LCD 209 displays 80 characters in one line. In the example of FIG. 3(d), each row has two planes, so
The value stored in line word register 423 is 20. This stored value is determined considering that two 8-bit words or characters are transferred from the screen image RAM 22J as signal VRAaO-15 at a time.

The two's complement of the value stored in the line word register 423 is output to the timing counter 4 by the occurrence of L INKLD which is generated when the counter 425 overflows.
25. The timing counter 425 is D
It is incremented by control of the output of OR gate 429, which receives the ATARDY signal and local clock signal LOCLK as inputs. The value stored in the timing counter is transferred from the screen image RAM 22J to the LC.
This corresponds to the number of 2-word data transferred to D209.

Line number register 429 is initially loaded with the number of lines to be displayed within the plane. In the embodiment of FIG. 3(b), this number is equal to the maximum number of lines that can be displayed on LCD 209. In the embodiments of FIGS. 3(C) and 3(d), the value stored in register 429 is
1/2 of the maximum number of lines that can be displayed on LCD Z 09
It is. This is because the LCD 209 is vertically divided into two planes. The value stored in register 429 is expressed as a two's complement number, and is incremented when all data in the display line of LCD 209 is transferred. When an overflow occurs, the timing counter 4
31 is reloaded with the value stored in the line number register.

1 display parameter 1 as will be clear to those skilled in the art
In other words, the number of lines of the LCD 20G and the number of characters per line are programmable. This allows for flexibility in the computer, which in turn provides flexibility for the user.

Screen image RAM 32g to LCD 209
In the actual transfer of display data to registers 441 and 44
3.445 and 447 are used. Each of these registers is correlated to a different plane of LCD 209. Therefore, if the displayed data is plane A, register A441, and if displayed data is plane B, register B443.
．． In the case of the 7' lane C, the data is stored in the register C445, and in the case of the plane D, the data is stored in the register D447.

- In the embodiment shown in Fig. 3(C), only two planes are L.
Since it is not provided in CD Z 09, register A4
41 and register B443 are required. Similarly, the third (b)
) In the single plane embodiment shown, only register A 447 is utilized.

The four data transfer paths shown in FIG. 4 are all the same;
Since they operate in parallel, only one data transfer path will be described in detail.

The 27-code data VRAs 0-15 from the screen image RAM 223 is loaded into the register 441 and is sent to the parallel to serial converter 448 by the signal PLANASTB.
Shift input is performed for . By shifting the data from register A441 to parallel/serial converter 448, signal DATA
RDYA is generated and supplied to the input of AND gate 4ao.

Parallel-to-serial converter 448 is comprised of shift register 449A and multiplexer 451A.

The 16-bit data ADO-15 input to the shift register 449A is the selection signal NBLSELO and NBLS.
ELI is in 4-bit units, i.e. NAOO-3°NA
Output as O4-7, NAO8-11, and NAO12-15.

The output of multiplexer 451A is data PLANADO.
-3 to plane A of the LCD 209 and further to the buffer 452.

As is clear from FIG. 4, the registers 443, 445 and 447 receive ready signals DA'rARDYB, respectively.
, DATAARDYC' and DATARD are further input to AND gate 430, which increments timing counter 425 after the display data shifted from each of registers 441-447. A high level signal DATARDY that can be used is generated. LCD 2
If there is one or two planes in 09, the appropriate value is A.
Applied to the input of ND gate 430.

During operation, the initial values corresponding to the embodiment of the LCD 209 are:
As mentioned above, registers 403, 405, 407, 401
1,411.423 and 429. This value is reflected not only in the number of planes included in the LCD 209 but also in the number of characters in one line and the number of lines in the LCD 209. Adder 415 outputs display addresses in each plane of LCD 209, and multiplexer 451A-45
1D transfers screen image data to LCD 209.

, assuming that the LCD 209 is composed of four planes, as shown in FIG.
1C and 451D to LCD 209. Two data words, or 16 bits, are stored in register 44.
1,443,445 and 441 to shift register 4
49A, 449B.

When transferred to 449C and 449D, the signal DATA
RDY becomes high level and increments timing counters 425 and 421.

When 20 2-word data transfers are made to each shift register, timing counters 421 and 425
causes an overflow.

As a result, a signal LINELD is generated and the counter 42
5 is reset to the value stored in line word register 423, increments timing counter 431, sets counter 421 to the value stored in register 419, and loads register 419 with the current output value of adder 417.

As a result, counter 421 outputs an incrementing address that is added to the plane pace address stored in registers 403-409 to generate the screen address for the second row of each display plane. next,
The data words displayed on the second line of each plane are transferred to the screen location output by adder 415. The second of each plane of LCD 209
Once the line of data is displayed, the third and next line is displayed. When the last line of each plane is displayed, the timing counter 431 overflows.
It is reset to the value stored in line number register 429.

The result register 419 is reset to zero.

The data in the screen image RAM 223 is transferred to the LC again.
'D 209 to refresh the display and nitrate the displayed data to reflect changes in the data stored in the screen image RAM 223.

FIG. 5 is a detailed block diagram of the second LCD controller 217. The second LCD controller 217 includes the above-mentioned status register and control register, and the CPU
Address and data transfer path for 201 and ASCII
Echo RAIJ 221 and Screen Image RA
IJ 22j, font pattern RAM 225, and circuitry for modifying data according to correlated attributes.

Status and control section 501 register R1
, R6, R9-R15, and R18-R27. The functions of these registers have been described above. This embodiment will be described below.

The 8-bit data bus from the CPU 20Z is the signal DB.
Supply O-7. Three RAiJs in memory 213
The data bus for 221, 223 and 225 is indicated by signals 1.1EO-1'5. CPU201
, memory 213, and second LCD controller 21
Memory bus 1 shared by 7 is indicated by signal AO-15.

When initialized, select register logic 5
DBO-03 is controlled by the 5-bit address signal AO-7 and loads the initial values for the status and control values into the control and status registers on the CPU data bus DBO-7. After initialization, if it is necessary to change the value of any of the status and control registers, select register block 503-1)i is enabled to reload the appropriate register or register group.

Data supplied from CPU 201 can be transferred directly to memory 22g via two write data latches 503 and 505. The data latch transfers the two 8-bit data transferred from the CPU in parallel onto the 16-bit memory bus as memory data 4 MBO-15.

Similarly, 16 pinot data transferred from memory 213, namely 1. (gMIo-15 can be output to CPU 201 as two 8-bit data words CPUDIO-7 via a pair of linear data latches 507, 509. Memory data IJEIJIO-15 is further divided into the upper 8 bits), MEIJI8- ASI to enter 15: “I
I code latch 511 and lower 8 bits MIO-7
may be provided to an ASCII attribute latch 513 that inputs.

A19CII latches 511 and 513 are used to input data from ASC'■ecode RAM 221.

The contents of the ASCI I code latch 511 are the lower 8 bits AO- of the address of the font pattern RAIJ 225.
7 and is transferred to the memory bus. The upper eight bits are provided by font select logic 515, which receives input from font select register RZ2. The 16-bit address is the font pattern RA that stores the screen image data corresponding to the Arc II code data.
Used to access a specific memory locus in M225. The actual bit representation of the ASCI encoded data is used as part of the address in font pattern RAM 225.

The two words of data returned from font pattern RAM 225 are latched into font data clutches 517-519. The lower 8 bits are input to attribute processing circuit 521 and latch 519 which supplies the lower 8 pictowords AO-7 to the memory bus. Font data latch 6
17, the upper 8 bits are sent to the attribute processing circuit 521 and the upper 8 bits.
The data bits transferred directly from the font data latches 517, 519 are transferred to the memory screen image VAM2z as bit words A3-15.

The attribute processing circuit 521 receives 8 bits of data at a time from the data latches 517 and 519, and the attribute control circuit 523
Modify by. Qualified data is provided to the memory bus via output legi error mode font data latches 525,527 or bold mode data latches 529T531. In bold (low resolution) mode, each displayed character is twice the size of the character cell.

The address in screen image RAM 223 for storing screen image data is generated by counter 541, which receives image start address l5AO-15 from image start address registers R24, R25. An adder circuit 543 adds the offset value to the output of the counter 541. This offset is added by adder 5
45 and stored in a latch 547 connected to this adder 545. The output of adder 543 consists of a 16-bit image plane address 11JPAO-15 and is provided to the memory bus.

A pair of data latches 549 and 55J are provided to output C from the memory bus as data LBD0-15.
Transfer the image plane address to PU 201.

Line address latches 553 and 555 then receive the address from the memory bus and pass it to counter 541 via adder 557 or as loopback data to CPU 20.
Supply to 1.

FIG. 6 is a logic diagram of a preferred embodiment of the second LCD controller 2NOA shown in FIG. As shown in FIG. 6, the memory bus includes a pair of 8-bit latches 601, 603 that receive memory bus @AO-15 from CPU 201 and memory 213. This signal AO-7 is transferred to latch 605 and becomes the 1a4BO-7 signal. Bits A, 8-11 are transferred to latch 607 and bits M
B becomes 8-11. The upper four bits MEMB12-15 from latch 607 are supplied by display memory address mask register R26. The 8-bit data bus DO-7 connected to the CPU 201 carries C'PU data C
Input by input latch 609 outputting PUDOO-07. Data is sent to the CPU via the output latch 611.
201. The clock signal used within the second LC'D controller is generated by oscillator 613 and output from latch 5rsVc.

The select register logic 5a3 (; gs diagram) includes decoders 621, 623 and NAND gates 625-64.
Composed of 5°. Inputs to decoders 617-623 include signals RgosgLo -RgC)iL4. This signal consists of the CPU data bit UDIO-CPUD14 output by latch 647. Latches 621, 623 generate an enable signal U R18 that produces a write of the corresponding status and control register.
Outputs WR-UR27WR. The decoder 623 further outputs a read enable signal UR28RD-UR3.
Output 1RD.

NAND gates 625-σ29 and 639-645 output LCD control register write enable signals UR9WR-UR25WR, respectively. HAND gates 631-637 are LCD control registers +J
-1' control signal UR12RD-UR15RD
Output.

FIG. 7 shows a circuit 701 for generating a CPU access request signal. This circuit is the second LCD controller 2
Although it plays a certain role in the operation of No. 17, a detailed explanation thereof will be omitted as it is not necessary for understanding this invention.

Furthermore, FIG. 7 shows CPU data C! as input. PUD0
0-07 respectively memory bus 151vf138
An example of write data latches 503 and 505 output to MBO-15 and MBO-7 is shown. Similarly, CPIJDIO-7 receives JMB8-15 and IJMBO-7 and is transferred to CPU 201 as output.
Read data latches 507 and 509 are shown that output .

FIGS. 8 through 10 illustrate embodiments of the status and control registers described above. The mode control register controls the link enable signal (BLKENB), video enable signal (vIDENB), graphic mode signal (GRAPHIC) and high resolution signal (HIRJ11) according to CPU data CPUD 00-07.
3) is realized by an edge trigger flip-flop ttox that selectively outputs. Similarly, the horizontal display register R1 and vertical display register R6 are CPUDOQ-0.
Edge-triggered flip-flop 803 . FI
It will be realized in 05.

Character/image buffer start address (upper)
The register R12 that stores the input signal CPtTDOO−
07 and a transceiver 1109 that receives input signal CPTJDIO-7. The data to be written to register R12 is provided by flip-flop 807, and similarly the data in register R12 is transferred via transceiver 809.

Character/image buffer start address (lower edge)
The register R13 that stores the R13 is realized by an edge trigger flip-prop 811 and a transceiver 813. Data written to register R13 is provided via edge triggered flip-flop air, and data read from register R13 is transferred via transceiver 813.

The cursor address (lower edge) register, register R14, is supplied by an edge trigger flip-flop 815. Transceiver gZ7 transfers the value stored in register R14 to CPU 201. Similarly, register R15 that stores the cursor address (lower edge) is connected to edge trigger flip-flop 819 and transceiver 112.
1.

Register R9, which stores the maximum scan line address, is implemented by an edge-triggered flip-flop 901. A register RIO that controls the cursor start scan line is implemented by an edge trigger flip-flop 903. AND gate 905 connected to flip-flop 903 via inverter 906 generates cursor inhibit signal 08RINH. The register R11 that controls the cursor end scan line is implemented by an edge trigger flip-flop 907.

Flip-flops 901, 903, and 907 all receive CPU data CPUDOO-07 as input.

Operating mode register R18, scan interval select register R19, and blink interval select register R20 are implemented by edge trigger flip-flops 909, 911, and 913, respectively.

The underline and overscan protection register R21, font select register R22, and background color register R23 are implemented with edge-triggered flip-flops 915, 917, and 919, respectively.

FIG. 10 shows edge trigger flip-flop 1, respectively.
Image buffer start address (upper) register R24, image buffer start address (lower) register R25, display memory mask register R26, which are realized by 001, 1003, 1005 and 1007,
and test mode register R27. Multiplexer 1009 receives the output of flip-flop 1005 and supplies it to AND gates 1011, 1013, and 1015 to generate three upper address mask bits.

First test status register R28, second test status register R29, data loopback (upper) register R30, data loopback (lower) register R
31 configures transceivers 1017.101991021 and 1023 and selectively transmits data CPUDIO-7
Output.

11 and 12 show a second LCD controller 217 that includes timing signals for accessing memory 213.
Generates timing and control signals used within r. Furthermore, FIG. 11 shows an LCD 209, a CPU
Signals that control access to 201 and memory 213 LCD8fCL, CPU8EL and 5CNSEL
A priority encoder 1101 is shown including a D-type flip-flop 1103 that outputs . Since the function of the timing circuit is not necessary for understanding the present invention, a detailed description thereof will be omitted.

FIG. 13 further shows circuitry for generating timing and control signals. Scan control sequencer 1301 reads ASCI I code RAM 221,
The font pattern RAM 225 is accessed and the screen image data is stored in the screen image RAM 22.
Generate timing and control signals for writing to 3.

FIG. 14 shows an embodiment of the counter and comparator (FIG. 5) connected to horizontal display register R1, vertical display register R6 and maximum scan line address register R9. The horizontal character counter 1401 corresponds to the contents of the register R1 and the second character generated by the first human power group HDISPO-7 and the counters 1405 and 1407.
It has a comparator 1403 with a human power group. Counters 1405 and 1407 are incremented each time an ASC'II code character is converted into a screen image character Kf by the second LCD controller 217. The count values stored in counters 1405 and 1407 are equal to the current value stored in register R1. Line end signal IJNEND is generated by D flip-flop 1409.

The vertical line counter 14z1 is connected to the vertical display register R6.
It has a comparator 1413 having a first human power group 15PO-7 supplied by 15PO-7 and a second human power group supplied by counters 1415 and 1417. counter 1
415°1417 is incremented by the L I MgND signal and stores the line number stored in the screen image RAM 22J. counter 1415
゜1417/C When the stored line number is equal to the current value of the vertical display register R6, the D free lag flop 14
19 generates a frame end signal %tJFRAIJEND.

Character line address counter 1421 consists of a comparator 1423 having a first group receiving the contents of maximum scan line address register R9 and a second group receiving the value stored in counter 1425. counter 1423
The output of is the maximum row control signal MAXROW.

Figure 15 shows font data latch 517°519, AS
An example of a CII code latch 511 and an attribute latch 513 is shown. The value of the attribute correlated to the ASCII codeword is output by the attribute latch and the plink bit (BL
BIT ), background red (BGRED
), background green (BGGRN),
Background blue (BGBLU), bright change pit (xBrT), foreground red (FC) RED
), Four Brown Dogs! J-n (FGGREN)
), and Forground Blue (FGBLU
) control signals.

Signals BGRED, BGGRN and BGBLU are used as selection signals for color emulator multiplexer 1510. The input to multiplexer 1510 consists of the output of edge triggered flip-flop 919, which is an embodiment of background table register R23. Since the LCD 209 cannot display red, green, and blue colors, the color emitter multiplexer 1501
RgD.

It is selected whether to make the background on the display 209 brighter or darker depending on the BGG surround and the BGBLU value.

FIG. 15 shows how the output ROWO-3 of the counter 1425 is combined with the kakunt value of the cursor start scan line register RIO and the cursor end scan line register R1.
Comparator 150 for comparing 1Ocacunto values respectively
Cursor timing circuit 15 with 5 and 1507
Example 03 is shown below. The input of AND gate 1509 is connected to the outputs of comparators 1505 and 1507. AND game) J509 output C3RPO8 company LC
Controls the display of the cursor on D 209.

The monochrome mode attribute decoder 1511 performs a non-display white control tW UNDWH' that displays all pixels of the character as white.
A non-display darkening control word NDBLK for displaying l' and all pixels of the character in black is generated.

The decoder 1511 further outputs an inverted video signal RVVI that displays all elements of the correlated character cells with inverted values.
Generates D.

The underline timing generator xs1sh has a counter 1515, one set of inputs receiving the output value of the counter 1425, and the other set of inputs receiving the value stored in the underline position register R21. AND game) J5Z7 connected to the output of counter 1513 and decoder 1511
generates an underline control signal LNUNDgR.

FIG. 16 is an embodiment of the attribute circuit 521 shown in FIG. 1
Transceivers 1601 and 1603f--J receive two data words (16 bits) in parallel from font data lines 5Z7 and 519 and form them into two serial data words of 8 bits each. Each 8-bit data word is then processed in parallel according to the attribute bits to generate 8-bit font data word FWRDO-7. Since each bit is processed in the same way, only the (beep) OK bit will be described in detail.

Bit O is applied as one input to a two-way OR gate 1605. The other input of OR gate 1605 has
signal, NUNDER and NDBLK as inputs
R game) 75177 output is input. LNUNDg
When either R or NDBL is set to 1 (TRUE), the output of the OR gate 1605 becomes 1, and the pixel of the display section 209 corresponding to bit 0 is displayed in a frozen state.

The output of OR gate 1605 is applied to one input of AND gate 1609. AND game) 1609 is
It performs several functions based on blinking control of pixels at selected positions on the LCD'θ9. This one function is
There is a half tone that blinks very rapidly so that it appears as one tone between black and white. This function is accomplished by a NAND gate 1611 that receives a high frequency dimming enable signal DrWM and a high frequency dimming blinking click signal DIBRLK. AND gate 1611 functions as a switch and turns on and off the pixel corresponding to bit O at high speed. This switching is done via the second input of the AND gate.

Pixels can flash at a rate that is visually perceptible. This is AND gate 1613 and HAND gate 1
615. Pixel blinking is controlled by the blinking bit BLBIT, which is one input to HAND gate 1615. The other input of NAND gate 1615 is the output of AND gate 1613. AND gate 16
13 Outputs a blinking frequency signal according to the blinking clock signal CHARBLK.

The output of AND gate 1609 is applied to one input of OR gate 1617. The output of the cursor blinking AND gate 1619 is applied to the other input of the OR game 1617. If the cursor position has a pixel correlated to bit O, then the pixel is
It blinks at a rate determined by 8RBLK. The frequency of the cursor blinking clock signal C3RBLK is different from the frequency of the character blinking clock signal CHARBLK, for example, 2
It is desirable to double the amount. As a result, the two signals can be visually distinguished.

The output of OR gate 1617 is provided to one input of NOR gate 1621. The other input of 1621 is the output of an OR gate that receives the color emitter signals BGDARK and RVV ID. OR
Gate 1613 changes the value of bit 0 to emulate a color display (by selecting the background color, black or white).

FIG. 12 shows an example of the implementation of the circuits and latch circuits 525-531 that implement the high resolution mode of the LCD 209.

In high-resolution mode, each character has two characters in low-resolution mode.
It has twice as many character cells. This is done by generating data words having values that control four pairs of pixels, one pair of pixels being identical.

The output of the attribute processing circuit 521, that is, the font data signal FWRDO-7 is sent to the data latch circuit 527°525(
(FIG. 17), and in high resolution mode are output as signal bodies 1a8-15 and MgMBO-7, respectively.

In normal resolution (low resolution) mode, bits FWRD4-7 of the font data word are fed to the latch circuit 529, and bits FWRD8-3 of the font data word are fed to the latch circuit 529.
is supplied to the latch circuit 531. Data bit FWR
Since D7 is supplied to inputs 6 and 7 of latch circuit 529, MEMB14 and 4MB/15 have equal values. Similarly, inputs 4 and 5 of latch circuit 529 are set to the value of FWRD6, so bit MEM
B12 and 140MB13 have equal values. ) Each bit of FWRDO-5 is similarly connected to the launch circuit 52.
9 and 531 output bits are copied to VEMBO-11.

Attribute bit E selects whether high resolution mode or low resolution mode
It is carried out by REB. Graphic mode font data input FDO-15 is latch circuit 1701.1
703 to the memory bus MBO-15.

FIG. 18 shows that the ASCII code RAM 221 is used to access the ASCII code word stored in the ASCII code RAM 221 so that display image data can be accessed by referring to font data.
21 shows a circuit that generates 21 addresses. The ASCII code RAd start address is code buffer address counter Z1? OZ, 1803°1805 and Z80'7 are provided as inputs to registers R12, R13. counter 1sor, xttos, 1t
The value stored in tos and 1807 is incremented and the value stored in ASCII code RAV 221 is
Sequentially outputs addresses of SCI I codewords.

Comparators 1809 and 11111 compare the output of the ASCII code buffer address with the current cursor address and set signals CURfEIOR and UCUR8OR accordingly. As mentioned above, CUR
The 80R signal is used to control the blinking of selected pixels to identify the location of the cursor.

FIG. 19 shows a display screen 1 for converting ASCII code data by accessing font data stored in the font data RAM 225 and storing the obtained image data; and a screen 1 for generating an address in the RAM 22j.
Figure 3 shows a circuit using an image data address generator. The next line address latch circuits 653 and 555 receive the memory address IJEMBO-15 from the memory bus and transfer the address to the test loopback data LBDO-15.
The data is transferred to the latch circuits 549 and 551 as such. The output of the latch circuit is further incremented by circuits 1901-190.
7, where the value of ME1, (BO-15 is +1
be done. The incremented address is provided to transceivers 1909.1911.

A pair of transceivers 1913.1915 is connected to register R2
4. Receive the picture iron start address from R25. The contents of transceivers 1909 and 1911 or the contents of transceivers Z 923 and 1915 are stored in counters 1917-
1923 is selectively supplied to the image plane base address counter comprising 1923. Counter 19 Z 7-19
23 is incremented by 1 every time all pixels in the character cell are converted from As(J echo data to screen image data. Therefore, the counter 1917-1
923 stores the address corresponding to the top row pixel in the character cell. Counters 1917-1923 are set in transceiver 1913.1915 when the last character of the last line of ASCII code RAM 22l is processed.
is set to the value stored in .

FIG. 20 shows a circuit for generating an address in screen image RAM 223 that corresponds to the end of a line of characters displayed on LCD 209.

Transceivers 2001.2003 store values corresponding to the number of characters in the display line of LCD 209 in high resolution and low resolution modes. This value is preset by register R1.

If high resolution mode is indicated by f(rRgs,
Value E (DISPO-) stored in transceiver 2001
7 is transferred to the row offset latch circuit 2005. If low resolution mode is indicated by signal IJHrRES, HDISPI-HDISP? That is, I-ZDI! stored in transceiver 2003! A value equal to half the value of 3PO-7 is provided to row offset latch circuit 2005.

The row offset latch circuit is an adder 2007゜2009
adders 2001-2011 and latch circuits 2013, which generate image offset signals rMOFFO-11 corresponding to one time the value initially received as input;
- Consists of 2017. The value N is equal to the line number currently stored in screen image RAM 223. Therefore, IMOFFO-11 is the value that always corresponds to the start of the line displayed on LCD 209.

Screen image RAM 2 that stores the execution address, that is, the screen image data currently being processed.
2 Physical address in J MPAO-15 is added by adder 20
19-2025.

Adders 2019-2025 convert the line address represented by signal engineer MOFFO-11 to character address IIJP.
Add to AO-15.

FIG. 21 uses a scan address control signal generator to generate a signal UCBRBNB that controls whether an address in ASCI I code AyuM 221 or an address in screen image RAM 223 is being processed. 1 road 2101 is shown.

The font selector circuit 2103 receives the memory address I output by the pair of transceivers 2105 and 2107.
JEMBO-15 pit MEIJBIO and ME)
It is provided to generate JBII. In this manner, one of the two font data stored in the 7-ont data RAM 225 may be selectively accessed.

FIG. 22 shows the signal SC! stored in the scan interval register R19. A scan interval selector circuit 2201 is shown including a combiner pzzosf having a first set of inputs receiving NIVO-7 and a second set of inputs receiving the outputs of a pair of counters 2205, 2207. The signal UCHI8T is used for scanning the memory 213 and for ASCII
generated from the output of comparator 203 to initiate the conversion from code data to screen image data. The scan interval is selectable via the counter in register R19. Power can be saved by refreshing memory at the longest interval.

Clock frequency divider circuit 2209 generates clock signals RATEO-7 having different frequencies. This results in the above-mentioned blinking control signals CHARBLK, CHARBLK, having different frequencies.
Enable blink interval selector circuit 2211 for generating C3RBLK and DIMBLK.

23 and 24 show an embodiment of memory 213 and circuitry for memory and input/output decoding.

Mode of operation of memory 213 and FIGS. 23 and 24
The various circuits shown in the figures will be understood by those skilled in the art
It is clear from the description of the LCD controller 217 that the second
No additional description of FIGS. 3 and 24 is necessary.

[Brief explanation of drawings]

1(a) to 1(C) are diagrams of a portable combinator using a display device and a display control circuit to which the present invention is applied, and FIGS. 2(a) to 2(b) are diagrams of this A block diagram of a combiator and a display system to which the invention is applied; FIGS. 3(a) to 3(e) are diagrams schematically showing the relationship between a display device and a display memory in the system to which the invention is applied; , WJ4 is a detailed block diagram of a control circuit that transfers screen image data to the LCD in a comviator system to which this invention is applied, and FIG.
Detailed block diagram of a control circuit that converts CI I code data into screen image data, and FIGS. 6 to 24
This figure is a detailed circuit diagram showing an embodiment of the control circuit of FIG. 5. 201... Processor, 203... Internal lotus, 20
9...LCD, 211...Display control circuit, 213.
...display memory, 219...first LCD control circuit,
217...Second LCD control circuit, 221...AB
CI I code RAM, 225... Font pattern RAM 0 Applicant's agent Patent attorney Suzue Takehiko 1,
Display of the case Japanese Patent Application No. 183152/1983 2 Title of the invention System for controlling a liquid crystal display device for hand-tone image display 3 Person making the amendment Relationship to the case Patent applicant data Taino Energy Corporation 4, Agent November 26, 1985 6, subject to amendment

Claims (1)

[Claims] 1. The display device has either a first value for displaying a first gradation on a display device or a second value for displaying a second gradation, and is displayed on the display device. means for receiving data to be displayed; means for supplying the data to the display device; and connected between the means for receiving data and the means for supplying data, wherein the data to be displayed is a first value. , the displayed data and the data having the second value are switched at a switching rate sufficient to make it appear as if the data having the third gradation is being displayed constantly. switch means for alternately supplying the data, and is capable of displaying the first gradation data and the second gradation data in order to display third gradation data intermediate between the first gradation and the second gradation. Control system for liquid crystal display devices. 2. The display device includes a display pixel that is turned on to display the first gray scale in response to data having the first value, and a second display pixel that is turned on to display the first gray level in response to data having the second value. comprising a matrix of display pixels turned off to display a gray scale, said switching means comprising: a clock pulse source having a frequency equal to said switching rate; and a first input receiving said data from said data receiving means. a first AND gate circuit having a terminal, a second input terminal, and an output terminal connected to the means for providing data; and selectively providing the clock pulse to the second input terminal; a gate circuit that causes the output terminal to alternately output data having the first value received by the receiving means with data having the second value at a repetition rate created by the frequency of the clock pulse; The first claim characterized in that it consists of
System described in section. 3. The gate circuit has a first input terminal that receives the clock pulse and enables display of the third gray level.
3. The system of claim 2, further comprising a second input terminal for receiving a dull color enable signal and an output terminal connected to the second input terminal of the first AND gate circuit.