JPS61123881A - Display data generation system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a small portable combination computer, and more particularly to a display device and a display control device used in such a computer.

[Technical background of the invention]

In recent years, the spread of small computers and personal computers has been remarkable. Compared to Combitas of just 10 years ago, the 4-7 Numeral Combi has significantly greater processing power at a fraction of the size.

Many of today's digital computers from various manufacturers are based on LSI or VLSI.
They employ the same or similar central processing units (CPUs) fabricated as two or more integrated circuit chips. This is C
PU is in some respects the current standard for this industry. Accordingly, one or more advanced operating systems have been developed for each CPH and are commercially available for all computer systems. Therefore, a standard CPU and operating system together provide sufficient processing speed and flexibility for most personal computer users.

With the standardization of CPUs and operating systems, computer manufacturers can focus on other features of the Combitas that differentiate them from the available Combitas and increase their market share. It's starting to look like this. Manufacturers specialize in data processing/editing equipment and peripherals.

We have developed color tag 2 fix functionality and advanced application software programs.

However, with a few exceptions, all personal computers use CRT displays, whether they are specialized CRT displays or connected to standard television sets. CRTs have good resolution, can display color, and can display more characters on the screen.

However, when using a CRT display, /4'
- The downward size of personal computers is limited, and most CRTs are very large, impeding the portability of computers and displays. Some manufacturers are using liquid crystal display (LCD) devices LCDs are much smaller than CRTs and therefore contribute to the portability of the motherboard computer.

[Problems with background technology]

However, there are several drawbacks to using LCD displays. First, the number of characters that can be displayed on an LCD screen is very small compared to a CRT display. Also, LCD
Whereas character cells in devices are generally square,
The character cells of a CRT are square or rectangular with a length of 16 degrees in the width direction or height direction, and LCDs cannot display colors like CRTs. The differences in the operating characteristics of CRT and LCD devices pose important problems. For example, analogy, CR
Personal computer with T p2>f LCD
Even if it is configured identically to a personal computer with an LCD, that is, with the same CPU, the same operating system, and the same device, a personal computer with an LCD can be programmed. If you use a display device, you will need a computer with a CRT.
I can only run programs written for Sonalcombi-ta. This is a serious problem. Because,
This is because the applicator software program must be modified or a program must be created for a converter with a separate K LCD device. Therefore, LCD
The lack of compatibility between converters with LCD and computers with CRT is a strategic disadvantage for manufacturers of computers with LCD.

Therefore, conventional software programs written for computers with CRTs can be used without modification.
- There has never been a portable computer that is so small and easy to operate.

[Purpose of the invention]

An object of the present invention is to provide a data pull combination that is small and easy to operate.

Another object of the invention is to provide a compact display device for a portasol computer.

Another object of this invention is to provide a portable computer with a liquid crystal display that is compatible with software programs made for computers with CRTs.

Another object of the invention is to provide a portable computer having a liquid crystal display that displays the same number of characters as a standard CRT display.

Another object of the invention is to provide a system for generating data to be displayed on a liquid crystal display.

[Summary of the invention]

In this invention, the first control circuit controls the screen image
) Transferring display data from the RAM to a multi-digit liquid crystal display such that display data is transferred to each segment of the display simultaneously. The second control circuit converts the ASCII code data into screen image data using a 9-turn phono RAM. This system operates under the control of a software program written for CRTs and is capable of emulating color displays.

[Embodiments of the invention]

FIG. 1(a) is a perspective view of a combination machine utilizing the present invention. This computer has a main unit 11 and a display unit 1.
st- has. This display section 13 is hingedly attached to the main body section 11, and displays a closed state, that is, a folded state. Efforts have been made to make the converter and display device more compact and portable.

A computer having a display section 13 in an operating position is a first computer.
6) As shown in the figure. LCD device 15 is included within display section 13 . This LCD device 15 displays the same number of characters as a general CRT, for example, 25 lines x 80 characters, but is much smaller than the conventional CRT display device.

A keyboard 12 is provided on the lower front side of the LCD display device 15. When the display section 13 is closed, it becomes a protective cover that covers the key gate 17.

FIG. 1(c) is a side view of the computer with the display section 13 in the operating position. Is the support member 19 a key? -Do I
7 is positioned so that it can operate optimally.
t-support. Two 70 tsupi disk drives 21
is located within the main body 11 and provides compatible storage capabilities for the computer.

FIG. 2(a) is a block diagram showing a computer system embodying the present invention. The computer system has an internal 203 for bi-directional transfer of data and control signals.
It is connected to the. This processor 201 is, for example, a Model/lr 80C88 microprocessor manufactured by Intel Corporation in the United States. This microbromo has random access memory (rt, m) and read-only memory I.
J (ROM), these memories are used during microprocessor operation, and MSDO8 and C
It can also be used with the P/M-86 operating system l-.

At the periphery of the computer system are key card and disk storage subsystems, each connected to a separate internal path. A suitable disk subsystem includes one or more small floppy disk drives 21t, as shown in FIG. 1(c). .

Liquid crystal display (LCD)? os is connected to the display control circuit 211. This display control circuit 211 transfers data to be displayed and control signals to LCD 209. The LCD 209 then sends a status signal to the display control circuit 211 along with a signal identifying the display 7t-mat.

The display control circuit 21 is connected to the internal path 203, and bidirectional signals are exchanged. Display code memory 213 is also connected to internal path 203 and display control circuit 211. As will be clear from the explanation below,
The data displayed on the LCD 209 is controlled by the display control circuit 21.
1 allows storage and reading from the display memory 213.

Bromo 201 can also directly transfer data to display memory 213 I/'C via internal path 203.

FIG. 2(b) shows the display control circuit 211 and the display device 21.
3 is a more detailed block diagram of FIG. 3. As embodied herein, the display control circuit 211 includes a first LCD control circuit 219. This first LCD control circuit 219
is display data f from display memory 213, LCD 20
Transfer to 9. I, the status signal generated by the CD 209 is transmitted from the LCD 209 to the first LCD control circuit 21
Transferred to 9.

The second LCD control circuit 217 is connected between the internal path 203 and the display memory 213, and is connected between the display memory 213 and the AS
Control when storing CII code display data and ASC
Controls the conversion of II code display data into screen image data suitable for display on the LCD 209.

The display memory 213 is divided into three sections.
Consists of M. In other words, the ASCII code RAM 22 stores the data displayed on the LCD, and the ASCII code RAM 22 stores the data displayed on the LCD.
A screen image RAM 22 that stores all or part of the data that is also stored in the I-code RAM 221 in a format suitable for display on the LCD 209.
3, and a font node RAM 225 that stores conversion data used when converting ASCII code data into screen image data.

As will be described later, the second LCD control circuit 217 has many internal registers, and these registers can be accessed by the LCD 209.
used to define and control One of these registers is an index register (not shown) that is used as a pointer to a memory location that stores the locations of other registers. This index register is a register that is loaded by processor 20 by executing an OUT instruction. To load other registers, the index register is first worded to the appropriate register (R10) and the data register (not shown) is worded to the selected control register (R8R2).
5 Tatami R7W Maximum scan line address (scan line) R26 W Cursor start scan line address (scan line) W Cursor end scan line address (scan line) R/W Start address (upper) R/NV Start address (lower) R/ W Cursor address (upper) R/'W Cursor address (lower) W Operation mode W Scan interval select W Blinking interval select W Underline position (scan line) W
Font selection W Background (BG) color table W
Image memory start address (higher order)
.・W Image memory start address (low order) W Video RAM address mask R27W Test mode R2, W Test status I R2, W Test status 2 R5゜ W Data loopback (high order) R,
1W 7'-Taluppa, ri (low order) Indicates that the above-mentioned central bone is currently not in use.

The functions and meanings of the signal values stored in the control register will now be explained.

R1; horizontal display Pit 7-0: Total number of characters displayed horizontally.

Range is 2 to 0FFH, the stored value is the actual screen size (40 in low resolution mode, 80 in high resolution mode)
If it doesn't match.

error.

R6; Vertical display Bits 7-0: Total number of characters displayed vertically.

Range is 2 to 0FFH, error if stored value does not match the appropriate null clean size (25 rows).

R,: Maximum scan line address pit 7-4: Ignored pit 3-0: Number of scan lines for one character) also corresponds to a small number of lines and stores a friend value.

Range is 0 to OFH.

R1゜2 cursor start scan line piff)6-
5: Control enable or disable of display cursor.

Bit 6 Bit 5 0 0 Cursor display 0 1 No cursor display 1 0 Cursor display available 1 1 No cursor display Bit 4: Ignore Bits 3-0: Cursor start scan line.

The range is 0 to 0FFH0. When the stored value is larger than pit 3-0 of R, (character scan line size), this cursor is not displayed.

R1, - cursor end scan line (write mi)
B, )7-4: Not ignored.

Bits 3-0 = cursor end scan address.

The range is 0 to 0FFH0. When the stored value is smaller than bits 3-0 of R1° (cursor start scan address), the cursor cannot be displayed.

R42: Character/image buffer start address is upper (read/write) Beep) 7-6: Ignored when writing, returns to zero when reading.

Bits 5-0: Meaning of character/image buffer
Top 6 pits for starting addresses.

R13: Character/image buffer start address is lower (read/write) Bit 7-O: Lower 8 bits of character/image buffer relative start address. Since the relative start address of the middle character/image buffer 7 register has a width of 14 bits, a 16-byte character/image buffer area can be accessed.

R14: Upper cursor address (read/write door 6: Ignored when writing, returns to zero when reading.

Bits 5-6: Upper 6 bits of the relative address of the cursor.

R15: Cursor address lower (read/write) bits) 7-0: Lower 8 bits of cursor relative address.

The relative address of the cursor register is 14 bits wide. Therefore, a 16 byte character/image buffer area is accessible. When this cursor address is off-screen, the cursor is not displayed.

R18: Operation mode (write only) Biwadoor: Controls recognition of character attributes in character mode. When it is 0, black and white mode is selected. When set to 1, color (emulation) mode is selected.

Biwatoro: Color/Image puffs! - Controls enabling or disabling of yin functions. When set to 0, the scan function is disabled. When set to 1, the scan function is enabled.
When changing the mode register of the LCD controller, the scan function is disabled to prevent destruction of data stored in the screen image RAM 22j, ie, the video buffer.

Bit 5: When this bit is 0, the maximum scan line address of R9 is programmable. When this bit is 1, the maximum scan line address is set to 7 (R, @OUT' instructions are ignored), rather than programmer 1.

This bit is set when monochrome display mode is selected.

Bits 4-3: Ignored.

Bits 2-0: Mask bits for the start address of the code/image buffer. The code/image buffer address is determined by this mask value and the scan address register (1
4 bits).

This feature allows changing the code/image buffer address structure.

R1, Niscan interval select bits 7-4:
It will be ignored.

Bit 3-0: Time wait between each plane of display unit 209 If 0, the first LCD controller 219 does not wait between scans of each plane.

R20' blink interval select pit door:
Select the basic clock for pixel blinking.

When 0, the character plink timing is the second LC.
D controller 217 is synchronized to the scan frame clock (not shown). When 1, the character plink timing is synchronized to the character/image buffer scan clock.

Bits 6-4: Ignored.

Bit 3-2 = Control Fast Plink Cycle The plink cycle is defined as follows.

Bit 3 Bit 2 Divisor Bi, )1-0: The plink cycle that controls the slow plink cycle is defined as follows.

Bit 1 Bit 0 Subtractor R21: Unlined position and overscan write prevention pin door: Ignored.

Bits 6-4: Image memory scan limit address.

This feature prevents screen image RAM 209 from being overwritten when the mode register changes.

Pit 3: Underlined raster address.

Range is 0 to OFH.

If the stored value is greater than the maximum scan line address in R2, the underline disappears.

R2□: Font select bits 7-4: Address of font pattern RAM 225.

This bit string is used for bits 12-15 of the address of font RkM225.

Pit 3: Select the highlight mode function.

When the stored value is O, bit 11 of the address for font addressing is bit 1 of R22 (see below).

When the stored value is 1, bit 11 of the font addressing address is the character attribute "I" (luminance).Pit 2: Selects the highlight mode function.

When the stored value is O, fast plinking is disabled. When the stored value is 1, high speed linking is enabled.

Bit 1: When bit 3 of R2□ is O, bit 11 of the font addressing address is set to the same value.

When bit 3 of R22 is 1, it is ignored.

When the scan line value of pit O:R23 is 7 or less, it is used as bit 10 of the font addressing address.

R2,:Background color table y)7-o:When color mode is selected (R1
8), part of the background color of the character attribute is decoded by this bit array.

Background attribute Background color reference bit BG 0 0 0 Bit 0 001 Bit 1 010 Bit 2 011 Bit 3 100 Bit 4 101 Bit 5 110 Bit 6 1 1 1 Bit 7 Note: Reference bit = 0 White background
7=1 Black background (reverse video) R24: Image buffer start address upper (write) bit (ignored) 6-0: Most significant bit of image buffer start address R25: Image buffer, 7a Start address lower (write) bit 7-O: Lowest bit of image buffer start address R26: Display memory 213 address mask (write) pit 7: Enables or disables read/write access to display memory 213.

PITRO: Ignored bits 5-3: Bits 15-13 of the display memory address supplied from the processor 20 to the display memory by RAM select +1 are masked by this bit array.

Bits 2-0: Bits 15-13 of the display memory address supplied from the processor 201 to the display memory by the RAM select 4P2 are masked by this bit array. This results in an increase in memory address configuration.

R27: Test mode (write) Biwa door: Displays test mode. The stored value is 00
When normal mode is selected. When the stored value is 1, test mode is selected. When in test mode, memory addressing is enabled only by the scan control section, and memory addresses and sinks from other sections are ignored.

Bits 6-3: Ignored Pit 2: Controls the video RAM read cycle time. When O, the read memory cycle time is 4 machine clock cycles.

Pit 0: Controls the write cycle time of the display memory 213. When 1, the write memory cycle time is 5 machine clock cycles. 1, the write memory cycle time is 4 machine clock cycles.

R28: Test status 1 (read) bits 7-0:
Test bits are used for diagnostic purposes.

R29: Test status 2 (read) bit 7-O:
These bits are used for diagnostic purposes.

R3゜Ni data loopback upper (read) bit 7-
0: These bits are used for diagnostic purposes.

R3,: Data route pack lower (read) bit 7-
0: These bits are used for diagnostics.

Mode Control Register This is a 6 pin, register with I10 address 3D8He. This register controls the status of the display control circuit 211 as described below.

Bits 7-6: Ignored.

Pit 5: When the stored value is 1, this bit turns the character background brightness into a plink attribute function for alphanumeric mode. If the upper attribute bit is not selected, 16 background colors (or brightness colors) are available and kill. In normal oiling, this bit is set to 1 to enable the plink function.

Pit 4: When the stored value is 1, high resolution mode (640X200) is selected for black and white graphics mode. The mono mode register allows one of eight colors to be selected (for emulation) in the direct drive set in this mode using the graphics mode register.

Bit 3: When the stored value is 1, the video signal is enabled upon mode change.

Bit 2: When the stored value is 0, force 2-mode is selected. When the stored value is 1, black and white mode is selected.

Pit 1: When the stored value is 0, 320X2
00 graphics mode is selected. When the stored value is 1, alphanumeric mode is selected.

Bit O: When the stored value is O, a 40 character x 25 liner/L/7 annumeric code (low resolution) is selected. When the stored value is 1, 80 characters x 25 lines alpha anonymous mode (
high resolution) is selected.

The list below is a list of one mode selected by this register.

Bit 543210 Selected function 40X2
5 Color Alf 101000 Anumeric (Emulation) 80X25 Color Al 7 100001 Anumeric (Emulation) The third (&) figure is an LCD 209 composed of pixels 301
FIG. In the preferred embodiment, LCD 209 has a horizontal resolution of 640 pixels and a vertical resolution of 256 pixels. LCD 209 has 25 lines x 80
It has the ability to display characters. This is a common configuration for CRT displays.

Pixels 301 are grouped into each character cell 301, which in the preferred embodiment is 3018 (width)
It has a pixel array of (height). A typical character cell for an LCD device is a square pixel array, such as an 8×8 array, as shown in cell 305. Using character cells that are larger in height than width increases the reliability of the LCD device. Therefore, the preferred embodiment uses square cells. However, as discussed below, the size of the character cells is programmable to provide application flexibility. The spacing between characters and lines in the preferred embodiment is one pixel each.

In the preferred embodiment, display memory 213 has a capacity of 48 bytes, ASCII code RAM 221 has a capacity of 16 bytes, screen image RAM 223K and 24K.
byte, and font pattern RAM 225° to 8
Part-time jobs are being given away. The display control circuit 21 is 4
It has two main control modes. Namely, they are a black and white character mode, a color simulation character mode, a color simulation graphic mode, and a direct bitmap mode.

In either control mode, reading or writing of display data by the processor 201 is performed using the second LCD controller: 17. ? This is done via J7. When the character display mode is selected, the second L
The CD controller 217 performs AS every free cycle.
The CII code RAM 221 is scanned and the ASCII code character data is converted into screen image data using the font data stored in the font pattern RAM 225 according to the correlated attribute bits.

The converted display data is stored in screen image RAM 3.
23. If the graphics mode is selected, the second LCD controller 217 converts the ASCII code graphics data stored in the ASCII code RAM 221 into appropriate pixel image data and writes it to the screen image RAM 223.

The first LCD controller 219 scans the pixel image data stored in the screen image RAM 22J and transfers the image data to the LCD 209 for display according to LCD scan timing.

Font pattern RAM 2Z5 is accessible by processor 201 during idle time.

Process, S20 is ASCII code display data fc2
bytes, ie, a code (or data) byte and an attribute byte, to the second LCD controller 217.

In the direct bitma, demo-P, the processor 201
The display data is directly transferred to the screen image RAM 22.
send to j.

If any control mode other than the direct bitmap mode is selected and the mode register indicates monochrome mode, the second LCD controller 217 stores the font pattern RAM j2.
5, converts the ASCII code data into pixel data, and performs the lock operation according to the value of the attribute/guit. When the mode register is set to color/seamulation, the operation performed is almost the same as for black and white, but the power 2
The processing of the attribute byte is different because it accesses the color table register for converting the data correlated to the - attribute into a black and white sequence for the selected pixel. If color simulation graphics mode is selected, A
Data stored in SCII code RAM 22 is transferred to the appropriate location in screen image RAM 223 without accessing font arm RAM 225.

Su-Gu-Spideo character is screen image RA
If stored in M 223, the second LCD controller 217 changes the background color to black and makes the characters white.

When a character with an attribute that instructs plinking is stored in the screen image RAM 223, the second LCD controller 217 displays character data having all white character cells in a designated area of the display device 209. Alternatively, when characters are displayed in reverse video, character data of all black character sections are alternately displayed.

The second LCD controller 217 displays highlighted characters and half-gradation images. In the case of emphasized characters, the second
The LCD controller 217 is a font nog turn RA.
For example, the second font data group stored in M215?
- Accessing bold fonts during conversion of ASCII code data to screen image data. Half-gradation is performed by changing the display of the selected character to all white pixels and visually providing a half-gradation image.

In character display mode, character data has two characters: a character code byte and an attribute byte.

Next, the definition of 2 bytes during operation in monochrome control mode is shown.

BLRGBIRGB Character attribute BL: Character cells and, for example, all white pixel cells defined by the background are alternately displayed and the attribute blinks.

■: This brightness displays characters that are emphasized by selecting an alternating font or dimmed by blinking at a rate higher than the response time of the LCD 209.

The background and foreground attributes are coded as follows.

Background Foreground RG B RG B ooooooo No display, filled with white pixels 00000
1 Underline 000111 Black text/white background 1 1
1000 white text/black pack ground 1111
11 No display, filled with black pixels Next, the definition of 2-byte character data in the Power 2-Simulation mode is shown. Since the LCD 209 cannot display many colors,
Color attributes project to specific black and white combinations with programmable thresholds.

BL RG B I RG B Character code Background Foreground character attribute BL: To alternate between a normal display character cell and a cell defined by the background, for example, a cell filled with specific data of all white pixels. Flash attributes.

I: Select alternate fonts for emphasis or LCD 20
Highlight attributes to display characters with either dimming by blinking at a rate higher than the response time of 9.

Background: Access the color table register using the 3-pit color attribute as a bit atlas.

RGB color table register bit address ooo.

If the accessed pit of the color table register is O, this character cell is displayed as black characters on a white background. Conversely, if it is 1, it is displayed as white characters on a black background. The correspondence between color attribute and cell display combinations can be programmed by loading the appropriate values into the color table registers. Foreground pits have no meaning.

The font data stored in the font pattern RAM 225 is always treated as a cell, and the display cell size is programmable. However, although the cell width is fixed at 8 pixels, it can be expanded to 16 pixels (low resolution mode) by using a .--1 square with an 8-pixel resolution. The height of the character cell is programmable from 1 to F pixels.

The middle Yarakuta cell is defined as the total space including the character body, inter-character space, and inter-line space. Font A? In the tandem RAM 225, eight pixel rows within one cell are treated as one byte of display data, with the MSB of the one byte display data representing the leftmost pixel on the screen, and the LSB representing the rightmost pixel.

The 8-byte font pattern RAM 225 has four 204-byte font patterns corresponding to 256 character turns with a width of 8 pixels and a height of 8 pixels to realize multiple font selection.
It can be managed as an 8-byte segment. 8
By using character cells with a height greater than a pixel, two different fonts can be separated and stored in two 4096 byte segments.

The actual byte address in hexadecimal for a particular row within a display cell is generated as follows.

Address=C6000H+(FS 1脣1000H)-
) - (FSO 800H) + (ROW2 Sho 400H
) + (ROWI Ax 200) () + (CD -) 2
)+ROWOFSI: Upper pit of font pattern RAM segment selection pit. If the emphasis font is enabled, this pit will turn into a luminance pit.

FSO: Lower pit of font pattern RAM segment selection pit. If a character height greater than 8 pixels is selected, this pit changes by ROW 3.

ROW 3-ROW O: These 4 bits represent a special row of characters. ROW 3 has no meaning if the character height is less than or equal to 8 pixels.

CD: An 8-bit character code that allows the identification of 256 different characters, including singel.

In the graphics display mode, the graphics data to be displayed is handled as 9 bytes corresponding to 8 pixels and is transferred directly to storage locations in 16 bytes of screen image RAM 225. The screen image RAM z ; t s is divided into two segments of 8 bytes, each segment corresponding to an odd row image memory and an even row image memory. Even row image memory is 80 bytes x 100 rows (row 02 row 1... row 19
8) image data is stored, and the image memory of odd rows is 80 bytes x 100 rows (row 19 row 2...row 199
) image data is stored.

16 for a specific group of 8 horizontal pixels on the screen
The /Jite address in decimal is generated as follows.

Address=MOD(R bias r/z)*BAOOOH+MO
D((ROW+1), etc.) Cost B8000 + INT(
ROW/2) 4I50H+ COLMOD: Represents a modulo function INT: Represents an integer function ROW Vertical location count of a row on the screen with row 0 being the top row on the second screen.

COL: Horizontal location count in units of 8 pixels when the leftmost group of 8 pixels is set to 0.

Sections 3(b) to 3(d) schematically illustrate further features of the invention. LCD 209 is 1, 2. Or it can be composed of 4 segments or planes. LCD 209 is displayed. However, if LC0209 is divided into multiple planes, many characters equal to the number of planes can be transferred in parallel from screen image RA'' 223 to I, CD 209.

As shown in Figure 3(b), a single plane LCD is
lines (eg 25), each line having N words (eg 80). Each word corresponds to one character displayed. Assuming that the first character to be displayed is stored at memory address A in the screen image RAFd 32 J, A+N-1 is the address of the last character on the first line υ, A+(L- 1)N
is the address of the first character of the last line, and the last character of the last line is stored at address A-1-LN-1. Therefore, the value is the line number, and the value N is the line offset, meaning the position of the character within the line.

FIG. 3(c) shows an embodiment in which the LCD 209 is divided into a plane B and a plane B. FIG. Line 1-L is included in plane A, and line L+1-2L is included in plane B. Data word 1 on line 1 is stored in a plane offset address e.g. 0 and data word 1 on line L+1 is stored in a plane offset address B e.g.
=A+LN.

FIG. 3(d) shows that the LCD 209 has four planes, ie! An example consisting of lane A, plane B, plane C and plane D is shown. In this embodiment, the maximum line offset (N) is the value A for the embodiments of FIGS. 3(b) and 3(c).

Grain A, plane B, f lane C and plane D
The addresses of the first data word of the first line are A, B=(L+1)2N, C=N, respectively.

D=(L+1)2N+N.

FIG. 3(e) shows the address of the screen image RAM 22J and the LCD in an embodiment in which the LCD 209 has two planes, plane A and plane B.
209 schematically shows the correspondence between addresses of 209. Plane offset address A is cleared.

- screen image RAM 223, the word is equal to address O in screen image RAM 223.
2 From j, start at address 0, address L (N-1
) is transferred to plane A of the LCD 209. Within plane B, the data word stored at address LN-2NL-1 is displayed.

If the LCD 209 is composed of four planes, the plane offset addresses of planes A, B, C, and D are O and N, respectively.

(L+1)N% and (L+1)N+N.

In Figure 4, the display data is stored in the screen image RAM 32.
3 is a block diagram of a first LCD controller 219 transferred from LCD 209 to LCD 209; FIG. This professional diagram is
Display data and convert display data to screen image RA
LCD to transfer from M 223 to LCD 209
209 display locator.

The circuit that generates the signal is shown.

At the start of a computer system, for example, the processor 20
1, a certain control large value is transferred to the register 403'4A 411 when powering up.

This control value relates to the number of planes within LCD 209 and the number of words within each plane.

For example, FIG. 4 is an embodiment of the first LCD controller 219 in which the LCD 209 has planes A to A. Therefore, r*gk 403 stores the above-mentioned plane offset At-. This person's value is screen image R
The first storage word in AM 323 is LCD 20
If the character to be displayed at location 0 of row O of 9 is stored, it is O.

Similarly r, egB405. r@gc407 and rag
D409 stores the values of plane offset B, plane offset C, and plane offset D, respectively. These values are for plane C.

This corresponds to the location on LCD 209 when displaying the first character of Plane B and Plane D.

r@gg411 is loaded with a value equal to the number of characters in each line of the plane. Assuming that LCD 209 displays 80 characters per line, for the embodiment of LCD 209 shown in Figures 3(b) and 3(c), the value stored in reg E411 is 80, and the value stored in reg E411 is 80; d) regE for figure
The value stored in 411 is 40.

The outputs of registers 403 to 409 are sent to multiplexer 41
3 input. Signals PLNSELQ and PLNSELI control multiplexer 413 to selectively output the values stored in registers 403-409 to one input of adder 415. multiplexer 413
The values output by constitute a 16-pit pace offset address for one of planes A through A.

The output of adder 415 constitutes a 16-pin address of a character position on LCD 209 for one of planes A through A. The first value output by the adder 415 for each plane A to LC in each grain A to
D 209 and is equal to the offset value stored in registers 403-409.

For each other character on a line, the base offset value must be incremented. This increment is performed by adder 417, register 419 and counter 421.
This is done by

The value stored in regE 411 is supplied to one input of adder 417. The other input of adder 417 receives the output of register 419, LINSAO-15t-. The output of the register 419 is also a line load signal LINEL.
It is loaded into the counter 421 under the control of D. Register 419 stores the output of adder 417 and loads its value under control of line end signal LINEEND. In this embodiment, the values stored in the various registers and adders are represented in two's complement. First, register 4
19 and the value of the counter 421 are set to O. The value of the counter 421 is incremented by 1 in response to the data ready signal DATARDY. The occurrence of DATARDY will be described below.

First, the line word register 423 is loaded with a value equal to A, the number of characters to be displayed on the line of each plane. Therefore, in the embodiments of Figures 3) and 3(C), L
Assuming that the CD 209 displays 80 characters per line, the stored value will be 40. In the example of FIG. 3(d), each row has two planes, so the value stored in line word register 423 is twenty. This stored value is determined considering that two 8 bits, two words or galactors are transferred from the screen image RAM 22j as signals VRAM0.0-15 at a time.

The two's complement of the value stored in line word register 423 is loaded into timing counter 425 upon the occurrence of LINELD, which is generated when counter 425 overflows. The timing counter 425 is DATA
It receives the RDY signal and the local clock signal LOCLK as inputs. It is incremented by controlling the output of 0Rp-to 429. The value stored in the timing counter is transferred from the screen image RAM J23 to the LCD2.
This corresponds to the number of 2-word data transferred to 09.

Line number register 429 is initially loaded with the number of lines to be displayed within the plane. In the embodiment of FIG. 3(b), this number is equal to the maximum number of lines that can be displayed on LCD 209. In the embodiment of FIGS. 3(c) and 3(d), the value stored in register 429 is
This is the maximum number of lines that can be displayed on the LCD 209.

This is because the LCD 209 is vertically divided into two planes. The value stored in register 4291C is expressed as a two's complement number, and is incremented when all data in the display line of LCD 209 is transferred.

When over 7a- occurs, line number register is displayed on Rina timing counter 43 □
The value stored in the star is reloaded.

As will be apparent to those skilled in the art, the display parameters, ie, the number of lines on LCD 209 and the number of characters per line, are programmable. This gives flexibility to the computer, which in turn gives flexibility to the user.

Screen image RAM 323 to LCD 209
In the actual transfer of display data to registers 441 and 44
3.445 and 447 are used. Each of these registers is correlated to a different plane of LCD 209. Therefore, if the displayed data is plane A, register 1441. For f lane B, register B443
, f jJ% of lane C is stored in register C445, and in the case of plane D, register D447 is stored, respectively.

In the embodiment of FIG. 3(c), there are only two planes of the LCD.
209, register A44 and register B443 are required. Similarly, in the single plane embodiment of FIG. 3(b), only register A 441 is utilized.

All four data transfer paths shown in the fourth diagram are the same,
Since they operate in parallel, only one data transfer path will be described in detail.

2 words from screen image RAM 223)'
7”-fi VRAMD+0-15 is vJ sp441
is shifted into parallel to serial converter 448 by signal PLANASTB. Register A441
The signal DATAARDYA is generated by shifting the data from to parallel to serial converter 448, AND p-)
430 O supplied to human power.

The parallel-to-serial converter 448 is composed of a shift register 449A and a multiplexer 451. shift register 4
The 16-bit data ADQ-15 inputted to 49 people is divided into 4-bit units, that is, NAOO-3, NAO4-7°N, by selection signals NBLSEL O and NBLSEL 1.
They are output as AO8-11 and NAO12-15. The output to multiplexer 451 is data PLANA.
It is supplied to plane A of the LCD 209 as D O-3, and further supplied to the buffer 453.

As is clear from FIG. 4, registers 443, 445 and 447 receive ready signals DATARDY B, respectively.
, DATARDY C and DATARDY D are further ANDed) f −) 4
36, resulting in a high level signal DATARDY capable of incrementing the timing counter 425 after the display data shifted from each of the registers 441-447 is shifted. L
If the CD 209 has one or two planes, appropriate values are applied to the inputs of the ANDrato 430.

During operation, initial values corresponding to the embodiment of LCD 209 are stored in registers 403, 405, 407, 40, as described above.
9,411.423 and 429. This value includes not only the number of planes included in the LCD 209 but also 1
This is reflected in the number of characters on the line and the number of 2-inches on the LCD 209. The adder 415 outputs the display address in each plane of the LCD 209, and outputs the display address in each plane of the LCD 209 to the multiplexer 451.
transfers screen image data to LCD 209.

Assuming that the LCD 209 is composed of four planes, as shown in FIG. 3(d), the data word is
multiplexers 451A, 451B.

451C and 451D to LCD 209. When two data hoods, i.e. 16 pits, are transferred from registers 441, 443, 445 and 447 to shift register 449, 449T3, 449C and 449D, signal DATARDY goes to I to E level. Timing counters 425 and 4211fr: increment. . When the 20 2-word data transfers are made to each shift register, the timing counter 42
1 and 425 cause overflow. This generates signal LINELD, resets counter 425 to the value stored in line word register 423, increments timing counter 43, and increments counter 425 to the value stored in line word register 423.
21 is set to the value stored in the register 419, and the current output value of the adder 417 is loaded into the register 419.
1 As a result, counter 421 outputs an ink address, which is added to the plane base address stored in registers 403-409 to generate the screen address for the second row of each display plane. The data word displayed on the second line of each plane is then transferred to the screen location output by adder 415. Once the second line of data for each plane of LCD 209 is displayed, the third and subsequent lines are displayed. When the last line of each plane is displayed, the timing counter 431 is reset to the value stored in the overflow, line number noster 429.

As a result, register 419 is reset to zero.

The data in the screen image RAM 223 is transferred to the LC again.
D 209 to refresh the display and change the displayed data to reflect changes in the data stored in the screen image RAM ;t ;t s.

FIG. 5 is a detailed block diagram of the second LCD controller 217. The second LCD controller 217 controls the CPU on the above-mentioned status register and control register.
Address and data transfer path for 201 and ASCII
I code RAM 221 and screen image RAM
223, a font and turn RAM 225, and circuitry for modifying data according to correlated attributes.

Status and control section 501 register R1
, "A", R9-R15, and R18-R27. The functions of these registers have been described above.

This embodiment will be described below.

The 8-pit data node from the CPU 201 is the signal DBO.
-7t-supply. 3 RAMs in memory 213 2
The data bus for 21, 22 J and 225 is indicated by signal MBO-15. The memory processors shared by CPU 201, memory 213, and second LCD controller 217 are indicated by signals A0-15.

When initialized, select register logic 5
03 is controlled by five bits of address signal AO-7 and loads initial values for status and control values from CPU data bus DBO-7 into the appropriate control and status registers. After initialization, if it is necessary to change the value of any of the status and control registers, select register fac 503 is enabled to reload the appropriate register or register group.

Data supplied from CPU 201 can be transferred directly to memory 213 via two write data latches 503 and 505. Data latch is transferred from CPU2
The two 8-pit data are transferred in parallel onto the 16-pit memory log as memory data M pins B0-15.

Similarly, the 16-bit data transferred from memory 213, ie, MEMI 0-15, can be output to CPU 201 as two 8-bit data fields CPUDI O-7 via a pair of read data latches 507 and 509. Memory data MEMI 0-15 is further upper 8
ASCII coder that inputs pit, MEMI8-15, chip 511 and lower 8 pits MEMI O-7t-
A manually operated ASCII attribute latch 513 may be provided. A
SCII latches 511 and 513 are ASCII code RA
Used to input data from M221.

The contents of the ASCII code latch 511 are transferred to the memory path as the lower eight bits AO-7 of the font pattern RAM 225 address. The upper eight bits are provided by font select register 515, which receives input from font select register R2□. 16 Pi, Toad L/Sii ASCI! Font number and turn R that store screen image data corresponding to code data
Used to access specific memory locations within AM 225. The actual bit representation of the ASCII code data is used as part of the address in the font motherboard RAM 225.

The two words returned from font turn RAM 225 are latched into font data registers 517 and 519. The lower 8 bits are input to an attribute, 1 processing circuit 521 and a latch 519 which provides the lower 8 bit word AO-7 to the memory path.

The font data latch 512 supplies the upper 8 bits to the attribute processing circuit 521 and the upper 8 bits to the memory path as words A3-15.

The data bits transferred directly from the font data latches 517, 519 are transferred to the screen image RAM 223 (via a memory path).

The attribute processing circuit 52 receives 8 pits of data at a time from the data latches 517 and 519, and the attribute control circuit 523
Modify by. The qualified data is provided to the memory path via the output regular mode font latch 525.527 or gold (emphasis) mode data latch 529.531. In bold (low resolution) mode, each display character is displayed using two of the middle Yarakuta cells.
Double.

The addresses in screen image RAM 22J that store screen image data are generated by counter 541, which receives image start addresses ISA 0-15 from image start address registers R24, R25. An adder circuit 543 adds the offset value to the output of the counter 541. This offset is generated by an adder 545 and stored in a chip 547 connected to the adder 545. The output of adder 543 is 1
It consists of a 6-bit toy turn plane address IMPAO-15 and is supplied to the memory path. A pair of data latches 549, 551 are provided, roof hack data LB
The image plane address is transferred from the memory path to the CPU 201 as DO-15. Next line address latches 553 and 555 receive addresses from the memory path and provide them to the counter 54 via an adder 557 or to the CPU 201 as a router.

FIG. 6 shows the second LCD controller 21 shown in FIG.
FIG. 7 is a logic diagram of the preferred embodiment of FIG. As shown in FIG. 6, the memory paths are CPU, ? (111 and memory 2
A pair of 8s receiving memory path signals A 0-15 from 13
It has bit latches 601 and 603. This signal AO-
7 is transferred to the latch 605 and becomes the square groove BO-7 signal. Beep) A3-11 is transferred to latch 607 and becomes MEMB 8-11.

The upper four bits MEMB12-15 from latch 607 are provided by display memory address mask register R26. The fc 8-bit data bus DO-7 connected to the CPU 201 is input by an input latch 609 that outputs CPU data CPUDOO-07t''.

Data is transferred to CPU 201 via output latch 611t. The clock signal used within the second LCD controller is generated by an oscillator 613 and a latch 6
15.

Select register logic 5OS (Figure 5) includes decoders 621, 623 and NANDr-toro 25-645.
Consists of 1C. Inputs to decoders 617-623 include signals RIX sum EL O-REGSEI,4. This signal characteristic is the CPU output from Chiro 47.
P-tabiy) CPUD 10- CPUD 1
Consists of 4. Latches 621, 623 output enable signals UR18WR-σR27WR that control writing of the corresponding status and control registers. Decoder 62
3 is a read enable signal UR28RD
- Output UR31RD.

NAND f-toro 25-629 and 639-645
output register write enable signals UR9WR-UR25WRt-, respectively.

NANDr-Toro 31-637 is LcD control register read control signal UR12RD-UR1
Output 5RD.

FIG. 7 shows a circuit 70 for generating a CPU access request signal. This circuit is the second LCD controller 2
Although it plays a certain role in the operation of No. 17, a detailed explanation thereof will be omitted as it is not necessary for understanding this invention.

Furthermore, FIG. 7 shows the CPU data CPUDOO as input.
-07t- Write data latch 5 outputs to memory path ME station 8-15 and MEMB O-7 respectively
An example of 03.505 is shown below. Similarly, as input ME
MB B-15 and MEMB O-7'i receive and output "CCPU2011fC transfer" CPUDI
Read data latches 507 and 509 that output O-7'
It is shown.

FIGS. 8-10 illustrate embodiments of the status and control registers described above. The mode control register 1 outputs the link enable signal (BLKENB) according to the CPUf-data CPUDOO-07.
F enable N signal (VIDENB), graphic mode signal (GRAPHIC) and high resolution signal (HI
RES) tl-Selective output, Nodoria! /7
This is realized by the rig 7cIf801.

Horizontal display register R1 and vertical display register R6 are similarly implemented with edge f flip-frog 803.805 receiving CPUDOO-07.

Character/image buffer start address (upper)
The register R1□ that stores the input signal CPUDOO-0
This is implemented by a transceiver 809 that receives an edge trigger, gflo, fttσ7, and an input signal CPUDI O-7t-. The data to be written to register R12 is provided by flip-flop 1107, and similarly the data in register R1□ is transferred via transceiver 809.

Character/image buffer start address (lower)
The register R13 that stores the
．． This is realized by a tap 811 and a human transceiver 813. The data written to the register R13 is the edge trigger flag 70. Data provided via f811 and read from register R43 is transferred via transceiver 813.

The cursor address (upper) register, which is register Rf4, is supplied with an edge (by register 815). Transceiver 817 transfers the value stored in register R14 to CPo 201 GC. Similarly, the register R15 that stores the cursor address (lower) is connected to the edge trigger 7 lip 7a tab 819 and the transceiver 1
121 yen C) will be realized.

Register R9, which stores the maximum scan line address, has an edge of 7! This is realized by frog 901. The register R10 that controls the cursor start scan line has an edge of 71J7'7O block 903.
It will be realized. AND gate 905 connected to free lag flop 903 via inverter 906t generates cursor inhibit signal C3RINH. The register R1, which controls the cursor end scan line, is implemented by the edge trigger flip 70 tube 907.

Flip flora f901, 903, and 907 all receive CPU data CPUDOO-07''Ik as input.

The operating mode register R48, scan-in p-pulse select register R17, and link interval select register R2G are implemented by free-lag flops 909, 911, and 913, respectively.

Underlining and overscan proxies.

The font select register old R2□ and background color register R23 are respectively edge trip frid defrost f915゜917.
and 919.

In Figure 10, each edge is a free lag flop 1.
001, 1003, 1005 and 1007. Image buffer start address (upper) register R1 Image pack start address (lower) register R25, display memory mask register R26, and test mode register R27 are shown. The multiplexer 1009 receives the output of the f1005.
ANDf−) 1011, 1013, and 1015 to generate 3 upper address mask bits. 1st test status register R28, 2nd test status register 1229, data route pack (upper) register R5°, data route pack (lower) register
$1 configures transceivers l017.1019.1021 and 1023, selectively data CPUDIO-7
Output.

11 and 12 show a second LCD controller 217 that includes timing signals for accessing memory 213.
generate timing and control signals used within the

Furthermore, in FIG. 11, an LCD j 09, a CPU 20
D-type f7 lig 70 g 11 outputs signals LCD5EL, CPU5EL and 5CNSEL controlling access to 1) - 1% I) 213g'
03 is shown. Since the function of the timing circuit is not necessary for understanding the present invention, a detailed description thereof will be omitted.

FIG. 13 further shows circuitry for generating timing and control signals. The scan control sequencer 1301 reads the ASCII code RAM 221, accesses the font/arm turn RAM 225, and stores the screen image data in the screen image RAM 22.
Generate timing and control signals for writing to J.

FIG. 14 shows an embodiment of the counter and controller (FIG. 5) connected to horizontal display register R1, vertical display register R6 and maximum scan line address register R7. The horizontal character counter 1401 corresponds to the contents of the register R1 and the second character generated by the first manual group MDISPO-7 and the counters 1405 and 1407.
It has a comparator 1403 with a human power group. Counters 1405 and 1407 are incremented each time an ASCII code character is converted to a screen image character by the second LCD controller 217. The count value stored in counter 14os, z4ovK is equal to the current value stored in register R4. The line end signal LINEEND is generated by the D-flip flop 1409.

Vertical line counter 1411 is vertical display register R6
It has a comparator 1413 with a first power group supplied by ISP O-7 and a second power group provided by counters 1415 and 1417. Counters 1415, 1417 are incremented by the LINEEND signal and store the line number stored in the screen image RAM 22j. Kara/ri1415,
The line number stored in 1417 is the vertical display register R.
When equal to the current value of 6, D7 Rig 70 Tub 1419
generates a frame end signal UFRAMEND.

Character line address counter 1421 consists of a comparator 1423 having a first group receiving the contents of maximum scan line address register R7 and a second group receiving the value stored in counter 1425. counter 1423
The output of the maximum line control signal is the kite ■ ward.

Figure 15 shows font data latch 517.519°AS
An example of a CI coder, a chip 51 and an attribute latch 513 is shown. The value of the attribute correlated to the ASCII codeword is output by the attribute latch and the plink bit (B
LBIT), Nogutsugu ground gray, do (BGR mark)
, Pack Ground Green (BGGRN), Pack Ground Blue (BGBI, U), Luminance Pit (IB
IT), foreground red (rGRED), foreground red (rGRED), foreground blue (FGBLU), and foreground blue (FGBLU).

Signals BGR, BGGRN and BGBLU are used as selection signals for color emulator multiplexer 1510. The input to multiplexer 1510 is
It consists of the output of the register F919, which is an embodiment of the pack ground table register R25. I, CD 209 is red.

Since green and blue colors cannot be displayed, the color emulator multiplexer 1501 uses BGRKD and BGGRN.
.

And it is selected whether to make the background on the display 209 brighter or darker depending on the value of BGBLU.

Fig. 15 shows the power c)n 11425 (D output ROW O-
3 shows an embodiment of a cursor timing circuit 1503 having comparators 1505 and 1507 that compare the count values of a cursor start scan line register "jO" and a cursor end scan line register R1, respectively.

The input of AMDI'-to 1509 is ':17)41/-
It is connected to the output of 1505° and 1507. The output C3RPO8 of the dart piece 1509 controls the display of the cursor on the LCD 209.

The black and white mode attribute decoder 1511 outputs a non-display white control signal mT that displays all pixels of the character as white and a key ↓.
No-display, no-control signal ND that displays all pixels of the vector in black
BLKt- occurs. Decoder 1511 further generates an inverted video signal IVID that displays all pixels of the correlated character cells with inverted values.

The underlined timing generator 1513 has a counter 1515 whose one input group receives the output value of the counter 1425 and whose other input group receives the value stored in the underlined position register R2. AND f-to 151 connected to the outputs of counter 1513 and decoder 1511
7 generates an underline control signal LNUNDER.

FIG. 16 is an embodiment of the attribute circuit 5219 of FIG. 1
Paired transceivers 1601+ and 1603 convert two data words (16 bits) in parallel from font data lines 512 and 519 into two serial data words of 8 bits each. Each 8-pit data word is then processed in parallel according to the attribute bits to generate 8-pit font data word FWRDO-7. Since each bit is treated in the same way, only bit O will be described in detail.

Pit 0 is applied as one input of the two-man power 0Rr-to 1605. The other input of 0Rr-to 1605 has
O with signals LNUNDER and NDBI, K as inputs
R Goo) 1607 output is input.

Either LNUNDER or NDBLK is 1 (TR
When set to UE), the output of 0Rf-)160B is 1
Therefore, the pixel of the display section 209 corresponding to the p)O is displayed in black.

The output of OR gate 1605 is applied to one input of subsequent gate 1609. AND r-) J t; 09
performs several functions based on blinking control of pixels at selected positions of LC0209. One such feature is half-gradation, which flashes very rapidly to appear as a gradation between black and white. This function receives the high-frequency dimming enable signal DIMBLK and the high-frequency dimming blinking signal DIMBLK (NANDf-) 1611
This is realized by AND f −) 1611 functions as a switch and turns on and off the pixel corresponding to bit O at high speed. This switching is performed via the second human power of AND r -).

Pixels can flash at a rate that is visually perceptible. This is AND gate 1613 and NAND gate) 1
It will be held on 615th. Blinking of pixels is NANII”-
BLBIT
Controlled. NAND? -) 16150 The other input is ANDe-to 1613 (D output. A[)
The r-tono 613 outputs a blinking frequency signal according to the blinking clock signal CHARBLK.

AND r-to16o9 output is ORff-to117
17 is applied to one input. The output of the cursor blinking AND gate 1619 is applied to the other input of the OR gate 1617. If the cursor position has a pixel correlated to bit O, the pixel is blinked at a rate determined by the cursor blink black signal C3RBLK. The frequency of the cursor blinking clock signal C3RBLK is preferably different from, for example twice, the frequency of the character blinking clock signal CHARBLK. As a result, the two signals can be visually distinguished.

ORe-) 1617 (D output is N0Rf-to 1621
is fed to one input of The other input of the NOROR goo 1621 receives the color emulator signal BGDARK.
and RVVID Ig-receives 0Rf-to output. 1613 emulates a color display by changing the value of bit O and selecting the background color, black or white.

FIG. 12 shows an embodiment of the circuits and latch circuits 525-531 that implement the high resolution mode of the LCD 209.

In high-resolution mode, each character has two characters in low-resolution mode.
It has twice as many character cells. This is done by generating data words having values that control four pairs of pixels, one pair of pixels being identical. Attribute processing circuit 5
2 output, that is, the font data signal FWRDO-
7 are supplied to the data controller and child circuits 527 and 525 (Fig. 17), and in high resolution mode, the signals MEMB8-
15 and ■MBO-7. In normal resolution (low resolution) mode, 717 ) 7'! ')
P(1)ey)FWRD4-7"' is supplied to the latch circuit 529,
(D Hyy) FwRDO-3Fi7 Y child circuit 53
1. Data Bi, ) FWRD7 is supplied to inputs 6 and 7 of latch circuit 529, so Bi.

) MEMBI4 and MEMB]5 have equal values.

Similarly, inputs 4 and 5 of latch circuit 529 are FWRD
is set to a value of 6, so P, ) MEMB12 and MGMB ]3 have equal values. Bit FW
Each bit of RDO-5 is similarly copied to output bit MEMBO-11 of latch circuits 529 and 531.

Attribute bit H selects high resolution mode or low resolution mode.
This is done by IRES. Graquikmo F font data input F D 0-15 Yes.

Child circuit 1701.1703f, memory path research MB via
Transferred to O-15. .

FIG. 18 shows the data stored in the ASCII code RAM 221 and stored in the ASCII code RAM 72:
2 shows a circuit that generates an address of 221.

ASC'I I code RAM star door Vless is used as an input to the code J4 7 tear address counter 11301.1803°1805 and 18o7.
Supplied from FLIJ11/C. counter 1g01
, 11103° 1805 and 18o7, the running value is incremented, and the ASCII code RAM 22
Outputs the address of the ASCII code r word stored in 1.

Comparators 1809 and 11111 compare the output of the ASCII code buffer address with the current cursor address, and depending on the result, output signals CUR8OR and UCUR.
80Rt-set. As mentioned above, the cvnson signal is used to control the blinking of selected pixels to identify the cursor's agility.

FIG. 19 shows how to access the font data stored in the font data RAM 225 using the ASCII
3 shows a circuit using an image data address generator to convert the code data and generate an address in the display image RAM 223 to store the resulting personnel data. The next line address latch circuits sss and sss receive the memory addresses MEMB 0-15 from the memory path and transfer the addresses to the latch circuits 549 and 551 as test loop data LBDO-15. The output of the latch circuit is further incremented by circuits 1901-1907.
The value of MEMBO-15 is then incremented by +1.

The incremented address is the transceiver 1909
．． Supplied in 1911.

A pair of transceivers 1913.1915 to register Ft
24. Receives the image start address from R25. The contents of transceiver 1909.1911 or transceiver 1913.1915 are stored in counter 1917-1.
923 is selectively supplied to the image brain base address counter comprising 923. Counter 19 tour 1923 is incremented by 1 each time all pixels in a character cell are converted from ASCII code data to screen image data. Therefore counters 1917-1923
stores the address corresponding to the top row of pixels in the character. Counters 1917 and 1923 are ASC
When the last character of the last line of II code RAM 221 is processed, it is stored in transceivers 1913-1915 and set to a ratio value.

I! Figure 20 shows a screen image RAM 223 corresponding to the beginning of one line of characters displayed on the LCD 209.
The circuit that generates the address in is shown.

Transceivers 2001.2003 store values corresponding to the number of characters in the display line of LCD 209 in high resolution and low resolution modes. This value is reset by register R1.

When high resolution mode is indicated by HIRES, the value MDISPO-7 stored in transceiver 2001 is transferred to row offset latch circuit 2005. If low resolution mode is indicated by signal UHI RES, H
DII3P1-HDIIP? That is, the transceiver 20
A value b equal to half of the value of 'KDIsPO-7 stored in row offset latch circuit 2005 is supplied to row offset latch circuit 2005.

Row i″7″・)2・7 circuit″′・Adder 2°°′・
.・N of the first value received as input by 2009
Adder 2007-201 that generates image signals IMOFFFO-11 corresponding to
1 and latch circuits 2013-2017.

fll[N is the current screen image RAM 223
equal to the line number stored in . Therefore, IMO
FFO-11 is the value that always corresponds to the start of the line displayed on LCD 209.

Screen image RAM 2 that stores the execution address, that is, the screen image data currently being processed.
Physical address within 23! MPAO-15 is adder 201
Generated by 9.2025.

Adders 2019-2025 convert the line address represented by signal IMOFFO-11 into character address IMPA.
O-15K ship equipment.

FIG. 21 shows a circuit 2101 that uses a scan address control signal generator to generate a signal UCBRENBi that controls whether addresses in ASCII code RAM 221 or screen image RAM 223 are being processed. shows. The font seven-shictor circuit 21o3 uses bits MEMBIO> and MEMB of the memory address MEMBO-15, which can output multiple outputs from a pair of tiger/seapers 2105 and 2107.
II. In this manner, two pieces of font data stored in the font data RAM 225 can be selectively accessed.

! Figure 22 &! , a scan interval selector circuit 2201f that includes a four-way controller xxost having a first set of inputs for receiving the t signal 5CNIVO-7 stored in the scan interval register 819, and a second set of inputs for receiving the output tubes of a pair of counters 2205, 2207. :show. Signal UCI (IST) is the scan of memory 213 and ASC
is generated from the output of comparator 203 to initiate the conversion from II code data to screen image data. The scan interval is selectable via the counter in register R19. Power can be saved by refreshing the memory at the longest interval.

The cyclo-frequency divider circuit 2209 is a CHAR with different frequencies.
BLK, C3RBLK and DIMBLK t - blinking interval selector circuit 2211t for generating
- Enable.

Figure 23 and! FIG. 24 shows an embodiment of memory 213 and circuitry for memory and input/output decoding.

Dynamic state of memory 213 and FIG. 23 and @24
The various circuits shown in the figures will be understood by those skilled in the art
It is clear from the description of the LCD controller 217 that the second
No additional description of FIGS. 3 and 24 is necessary.

[Brief explanation of drawings]

@ 1 (a) to K 1 (a) Figure is a diagram of a portable combinator using a display device and a display control circuit to which the present invention is applied; Figures 2 (a) to 2 (b) are A professional diagram of a combination device and a display system to which this invention is applied; Figures 3(a) to 3(e) show the relationship between a display device and a display memory in a system to which this invention is applied. A factor that schematically shows; ! Figure 4 is a detailed diagram of a control circuit that transfers screen image data to the LCD in a comviator system to which this invention is applied; Figure 5 is a detailed diagram of a control circuit that transfers screen image data to an LCD in a comviator system to which this invention is applied; Control circuit details professional, converting into data
and FIGS. 6 to 24 are detailed circuit diagrams showing embodiments of the control circuit shown in FIG. IE5. 201-...Brose? , 203... Internal path, 20
9...LCD, 211...Display control circuit, 213.
...display memory, 219...first LCD control circuit,
2 No...2nd LCD control circuit, 221...AS
CII code M, 225...font pattern, 2R
AM Applicant's Representative Patent Attorney Takehiko Suzue Director General of the Patent Office Michibe Uga 1. Case Indication Special No. 983-183153 2, Invention Name Indication Data Generation System 3, Person Making Amendment Relationship with the Case Patent Applicant Data Fentel Corporation 4, Agent November 26, 1985

Claims (1)

[Scope of Claims] 1. A code memory for storing data words to be displayed by a display device; and a font conversion memory addressable by an address made from the data words and outputting pixel data corresponding to the data words. a display image memory storing pixel data for driving a matrix of display pixels to display the data word; and accessing the data word stored in the code memory to generate the address and generate the seven fonts. A display device comprising a matrix of display pixels in rows and columns, characterized in that it is constituted by a control circuit that accesses corresponding pixel data of a conversion memory and stores the output pixel data in the display memory. A system that generates the data displayed by. 2. Each data word stored in the code memory has a correlated attribute word in the code memory, and the system further includes a plurality of registers for controlling a control circuit according to the value of the attribute word correlated to the data word. The system according to claim 1, characterized in that it has the following. 3. The system according to claim 2, further comprising a register initialization circuit that selectively supplies control data to the control register. 4. further comprising an address generation circuit for generating addresses of data words and correlated attribute words stored in said code memory, said control circuit generating said data words at addresses of said code memory generated by said control circuit; 4. The system of claim 3, further comprising a code memory read latch circuit for latching an attribute word correlated with a code memory read latch circuit. 5. The control register has a font selection register that provides selected bits of the address of the font conversion memory, and the control circuit is configured to transfer the selected bits from the font selection register to the code memory read latch circuit. 5. The system of claim 4, further comprising font address circuitry for generating the address of said font conversion memory by combining with a received data word. 6. A font data latch circuit that receives pixel data output by the font conversion memory; and an attribute processing path that selectively changes the value of the pixel data according to an attribute word that correlates with a data word corresponding to the pixel data. 6. The system according to claim 5, further comprising: 7. The attribute processing path includes: a first pixel data output latch circuit that outputs a character displayed with a first width corresponding to a first number of pixels; and a second pixel larger than the first number of pixels. 7. The system according to claim 6, further comprising a second pixel data output latch circuit that outputs a character displayed with a second width corresponding to the number. 8. a first font section for outputting first pixel data corresponding to the data word when addressed by an address made from the data word; and a first font section for outputting first pixel data corresponding to the data word when addressed by the address made from the data word; 2. The system of claim 1, further comprising a second font section that outputs second pixel data corresponding to a word. 9. The system of claim 1, wherein the code memory, font conversion memory and control circuit are comprised of random access memories of different segments. 10. The system of claim 4 further comprising an image data path for transferring data words received by said code memory latch circuit to said display image memory for direct storage.