CA1241135A - System for controlling a liquid crystal display to display half tone images - Google Patents

Abstract

Abstract of the Disclosure A system for controlling a liquid crystal display of a small, portable computer. A first control circuit transfers display data from a screen image RAM to a multiple segment liquid crystal display such that display data is transferred simultaneously to each segment of the display. A second control circuit translates ASCII-coded data to screen image data through the use of a font pattern RAM. The system is capable of being operated under the control of software programs written for cathode ray displays and is capable of color display emulation.

Description

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Field o the Invention This invention relates to small, porta~le computers, and more speci~ically, to displays and to display controls used with such computers.

_ackground of the Invention In recent years, there has been unprecedented growth in the use of small, personal cornputers. When compared ~o computers o only a decade aqo, personal computers are a small fraction of t~e size and yet have maintained significant processing capabilities.

Many of the personal computers of today available from different manufactures employ the same or similar central p{ocessing units ~cpu's) abricated as one or more inte~rated circuit chips using lar~e scale integration (LSX) or very la~e scale integration (VLSI) peocesses. These cpu's have in some respects become ~he present standards for the industry. As a natural conse~uence, one or more sophisticated operating systems has been developed for each brand of cpu and is commercially available to users of the personal computers. When u5ed toqether the standard cpu's and the operating systems there~or provide su~ficierlt processing speed and flexibility or ~ lar9e majority ; of the users o~ personal computers~

I`he standardization of cpu's and operating sys~ems has permitted manu~aeturers o~ personal computers ~o foeus their attention on other eatures of the computers in order ~o differentiate among the available computers and to establish avorable marke-ting shares. Manu~acturers have developed speeialized data entry and editing devices, peripheral deviees, color graphics capabilities, and sophisticated application so~tware programs.

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Wi~h ~ew exeeptions, however, personal computers all use cathode ray tube (CRT) dic.plays either through special CRT
displays or by connection to a standard television receiver. A
C~ is capa~le of good resolution, color display, and can display many characters on the screen.

The use of a CRT display, however, limits the downsizing of a personal computer and, since most CRT's are quite lar~e, prevents the computer and display from being trul~ portable.
Some manuacturers have su~stituted other types o~ disp~ays including liquid crystal display (LCD) devices. An LCD is much more compact than a CRT and, there~ore, con~rtbutes -to ~he portability o~ the personal eomputers.

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Nonetheless, there are several drawbacks r~lated to the use o LCD devices. One is ~hat the number o charaeters displaya~le on ~n ~CD sc~een is normally mueh smaller than the number whieh .. - 2 -3~

can be displayed on a CRT display. Also, the character cells in LCD devices are t~pically square whereas char~cter cells for a C~T ca~ be square or rectangular with the longer dimension in eithe~ width or height. An LCD does not have the capability to display color as is possible with a CRT display.

~ hese differences in the operating character~stics o~ a CRT
display and an LC~ device have significant r~mi~ica~ions. For exarnple, even i~ a personal computer with a CRT display is configured identically to a personal computer with an LCD device, i.e., the same c~u, ~he same o~eeatiny s~stesl, ard the same peripherals, the latter will not be able to run application programs written for the ~ormer when, as in almost all cases, the program requires the use of a display. This is a serious problem because it either requires modification of application software programs or the independent development of programs ~or use by computers with LCD devices. The lack o compatability between computers with on LCD device and computers with the more popular CRT display places a manufacturer of the former in an unfavora~le market position.

Thus, the prior a~t o~ personai computers is wît~out a small, easily portable computer with an LCD device which may be used without revising application so~tware prvgrams written for computers with CRT displays.

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Obiects and Summary of the Invention An object of the present inven~ion is a small, easily portable computer.

Another object of the present invention is a compact display for a portable computer.

~ further objec. of the present invention is a portable computer with a liquid crystal display which is co~patible with software programs preparecl for computers with cathode ray tube displays.

Still another object o~ the present invention is a portable computer with a liq~id crystal display that displays as many characters as the standard cathode ray tube display.

' An additional object of the present invention is to control a liquid crystal display to display half tone images.

-These and other objects are accomplished by a system forcontrolling a liquid crystal device capa~le of displaying data with a irst ~isual tone or a second visual tone to display data with a third visual tone between the first and second visual tones, the system comprising means for receiving data to be - ,3a -(~

displayed on the display, the data having either a first value for causing the di.splay to display the first visual tone or a second value for causing the display to display the second visual tone, means for supplying the display data to the display, and switch means, con~ected between the receiving means and the supplying means, for alternately supplying the display with the data to be displayed and the second value at a switching rate sufficient to cause the display to visually appear to be constantly displaying data with the third visual tone when the data to be displayed has the first value.

I - 3b Brief_~cription_o~ the Drawinqs Th~se and other objec~s, features and advantages of the present invention, as well as the invention itself r will become more apparent to those skilled in the art when considered in t~e light o~ the accompanying drawings, wherein:

Figures l(a) - l(o) are views of a portable computer using a display and display control circuitry including the present invention;

Figures 2(aJ - 2(b) are ~lock diagrams of a computer and a display subsystem, respectively, utilizing the present invention;

Figures 3~a) - 3(e) schematically illustrate the relations~tip between the display and display memory within a system utilizing the present invention;

~ i~ure 4 is a detaiLed block diagram o~ control circui~ry ~or transerring screen image data to an LCD in a compu~er system utilizing the present invention;

~ igure 5 is a high level block diagram o~ control circuitry for conve~ting ~SC~I-coded data to screen image data in a computer system utilizing the present invention; and Figures 6-24 are detailed circuit diagrams illustrating an embodiment o~ the control circuitry of Figure 5.

Detailed D~scription of the Preferred Embodiment Figure l(a) is a perspective illustration of a computer utilizing the present invention. ~he computer inc~udes a base portion 11 and a display portion 13. The display portion 13 is hinged to the base portion 11 and is shown in the closed, i.e., folded, position. The compact nature of the computer and display testifies as to its easy portability.

T~e computer is shown in ~igure l(b) with the display portion 13 in the operative position. An LCD device 1~ is included within the display portion 13. The LCD device 15 displays as many c~aracters as a conventional CRT, for example ~5 lines of 80 characters each, but can easily ~e seen to be much smaller than the CRT display aLone of most prior art computer. A
keyboa~d 17 i9 provided ben~ath and in ~ront o~ the LCD device 15. The display portion 13 when closed is a protec~ive cover over the keyboard 17. ¦~

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Figure l(c) is a side view of the computer with the display portion 13 in the operative position. A sup~rt mem~ec 19 supports the base portion 11 in such a manner that the keyboard 17 is posit~oned for optimum operation. Two floppy disc drivers 21 are provided within the base portion 11 to provide interchang~able storage capability ~or the computer.

Figure 2(a) is block diagram illustrating the computer s~stem em~odying the present invention. The computer system includes a processor 2bl which is connected to an interna bus 203 ~o~ the bidirectional transfer of da~a and cont~ol signals therebetween. A suita~e processor is the Mo~el 80C~B
microprocessor commercially availa~ie from In~el. This microprocessor includes both a random access memory (RAM~ and a read-only memory (ROM) which are used in the operation o ~he mioroprocessor, and may ~e used in conjunction Wit~l th~ ~SDOS and ~he CP/M-86 operating systems.

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Included ~ith the periphera7s for the computer system are the keyboard and the disk storage subsystem both of which are individually coupled to the internal ~us. A suita~le disk su~sys~em includes one or more comp.ict elOppy disk drives 21 as shown in Pigure l~c).

- 6 - , A li~uid crystal display (LCD) 209 is connected to display control circuitry 211. ~he display control ci{cuitry 211 transfers data t,o be displayed and control si~nals to the LCD
209. The LCD 209, in turn, sends status signals ~o the display control 211 along with signals identifying the Eormat of ~he display.

The display control 211 is ~onnected to the internal bus 203 for bidirectional communication therebetween. A display memory 21~ is also connected to the internal bus 203 and to the display control circui~ry 27 1~ ~5 Will be eviden~ from the description which follows, data to be displayed on the LCD 209 can be stored in and retrieved from the display memory 213 by the display control circuitr~ 211. The processor 201 can also transfer data to the display memory 213 directly over the internal bus 203.

Fiyure 2(b~ is a more detailed block diagram of the display control circuitry 21L and the display 213. As embodied herein, the display control circuitry 211 includes LCD control-l 219 which transfers data to be displayed from the display me~ory 213 to the LCD 209. Status signals generated by the ~CD 209 are transferred ~rom the LCD 209 to the LCD con~rol-l 219~

LCD-control~2 217 is connected between the intecnal bus 203 and the display memory 213 and controls ~he storiny of ASCII-Ij;
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coded display data in the display memory 213 as well as the conversion of the ASClI-coded display data to screen image da~a suitable for displa~ on the ~CD 209.

The display memory 213 comprises a RAM divided into three sections, an ASCII code ~AM 221 for storing data to be displayed on the LCD, a screen image RAM 223 for storing all or part of the data also stored in the ASCII code RAM 221 but in a format suitable for display on the LCD 209, and a font pattern RAM 225 or storing conversion data used in convertinq ASCIX-coded data into sc~een image dat~.

As will be described later, LCD control-2 217 includes many internal registers which are accessi~le by the processor 201 and are used to def ine and control the LCD 209. One o these registers is an index register (not shown) which is used as a pointer to the memory locations storing the locations o~ the other registers. The index register is a register which is loaded by the processor 201 by executing an OUT instruction. In order to load any o~ the other contcol registers, the index register is first loaded with the appropriate regis~r address, a data register ~not shown) i.s loaded with in~ormation to be stored in the selected control re~ister, and an OUT instruction ;6 executed by the processor 201.

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The follo~ing table identifies the control re~isters and t~e values which are stored therein to implement and contrc~
di~erent operation modes of the LCD ~09.

Name R/W Description R0 *
Rl W Horizontal displa~ed (character) R2 *
~3 *
*
~5 * .
R6 W Vertical displayed (character~
R-7 *
R8 *
R9 W Maximum scan line address (scan line) R10 W Cursor start scan line address (scan line) Rll W Cursor end scan line address (scan line) ~12 R/W Start address (high) R13 R/W Start address (low) R14 R/W Cursor address (hiyh) R15 R/~ Cursor address (low) ~16 *
~17 *
R18 W Operation mode ' :

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Rl9 W Scan interval select R20 ~ Blink interval select R21 W Underline position ~scan line) ~22 W ~ont select R23 W ~ackground (BG) color table ~24 W Image memory s~art address (high) ~25 W Image memory start address (low) R26 W Video RAM address mask R27 W Test mode R~8 W Test status 1 R29 W Test status 2 R30 W Data loop back ~high) R31 W Data loop ~ack (low) * Not currently utilized.

The function and interpretation o~ signal values stored within the control ~egisters is explained next.

orizontal displayed Bits 7-0 Total horizontal displayed chara~ters. ~ange is ro~ 2 ~o OFFH. I the stored value does not match ~he real scrcen size ~40 at low resolution Mode, 80 at high resolution mode), then ERROR.

3 t~3 R6: Vertical displayed Bits 7-0 ~otal vertical displayed characters. Range is frorn 2 to OFFH. If the stored value does not match the proper screen size (25 rows~, then ERROR.

R9: Maximum scan line address Bits 7-~ Ignored Bits 3-0 Stores a value corresponding to one less khan ~he scan line number o~ a character. Range is from 0 to OFH.

R10. Cursor start scan line Bits 6-5 Controls the enabling or disabling of ~he display cursor.

~.' ~ Bit b ~it 5 _____ _____ 0 0 Display the curs~r 0 1 Non-display the cursor 1 0 Display the cursor 1 1 Non-displa~ ~he cursor Bit 4 rgnored Bits 3--0 Start scall line o the cursor. Range is from 0 to OFFEI. ~hen the stored value is greater than bits 3-0 o ~9 tcharacter scan line size), t~e cuesor may not ~e displayed.

~2~ 3~ -Rll~ Cursor end scan line (write only) Bi~s 7~4 Not ignored Bits 3-0 End scan address of the cursor. Range is from O
t~ OFFH. When the sto~ed value is less ~han bits 3-0 of R10 (cursor start scan address), ~he cursor-may not be displayed.

212: S~art address of chaeacter/image buf~er high (read/write) Bits 7-6 Ignored at write, return zeros at read.
Bits 5-0 Most signiEicant 6 ~its of relative start address o character~'image ~uffer ~13; Start address of character/image buffer low (read~write]
Bits 7-0 Least significant ~ ~its of relative s~art address of character/image buffer. Relative start address of character/image buffer register is 14 bits in - width, therefore, 16K bytes of character~image _~..
buEer ared are accessible.

R14: Cursor address high (read/write) Bits 7-6 Ignore~ at wri~e, return zeros at read.
Bi~s 5-0 Most significant 6 bits o~ relative address of the cursor.

~15: Cursor address low (read/write) ~ 12 -:a2~

Bits 7-0 Least significant 8 bits o~ relative address of the cursor. Relative address of the cursor reyister is 14 bits in width. Therefore, 16K bytes of char,acter/image buffer area aee accessi~le. When this cursor address is of~ screen, the cursor may not be displayed.

~18: Opèration mode (write only) Bit 7 Controls t~e r~cognition o character attributes in character mode. When it is 0, black and white mode is selected. When it is 1, color (emulation) mode is selec~ed.
Bit 6 Controls the ena~ling or disabling of the color/image ~uffer scanning faciLity. W~en it is 0, scan function is disabled. When it is 1, scan function is enabled. When main processor is changing the mode regis~ers of the LCD-control-2, the scan ; function may be disa~led to inhibit the destruction of data stored in the screen image RAM 223, i.e., the video buf ~er.
~it 5 When this bit is 0, maximum scan line address in R9 is prG~rammable. When this bit is 1, maximum scan line address is not progr~mmab~e ("OUT"
instruction of R9 is ignored) and is set equal to ~ 13 -7. This bit may be set when selecting monochrome display mode.
Bi2:s 4-3 Ignored ~its 2-0 Mask bits of scan address of codejimage bu~fer.
~ode/image buf fer address e~uals this mask value .AND. scan address register ~14 bits~.
This ~acility enables chan~ing code/imaqe bu~er add ~ e ~ t C ~ C ~ .

n interval select Bits 7-~ Igno~ed Bits 3-0 Wait time between the scan of each plane of the display 209. If it is ~, then LCD-control-l 219 ; does not wait between each plane scan.

R2~: Blink interva~ select Bit 7 Selects ~ase clock for pixel blinking. When it is 0, character blink timing is synchronized with LCD-control-2 217 scan frame clock (not shown~.
When it is l, character blink timing is synchronized with character/image buf~er scan clock.
Bit 6-4 Ignored Bits 3~ trols ~he high speed blinking cycle. Blink cycle is speci~ ollows:

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Bit 3 Bit 2 Divisor .. ... . . . .

O 1 1/~

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; Bits 1-0 Controls the low speed blinking cycle. Blink cycle is specieied as ~ollows:

Bit 1 Bit 0 Divisor 1 o 1/128 21: Underline position and over-scan write protection Bit 7 Ignored Bit.s 6-4 Limit address o~ ima~e memory scanning. ~y this function, the screen image RAM 209 is protected from being overwritten when mode register is changed.

Bit 3 Raster address of underscore. Range is feom 0 ~o OFH. When the stored value is greater than the maximum scan lisle address in R9, underscore may disappear.

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R22: Font select Bits 7-4 Address of the ~ont pattern ~AM 22S. This bit series will be used for bits 12-15 o~ the address for font RAM 225.
Bit 3 Selects function of highlight mode. When the stored value is 0, bit ll of add~ess for font addressing is bit 1 of R22 (see below). When the stored value is 1, bit 11 of the a~dress for font addressing is "In ~intensity) bit of character attribute.
Bit 2 Select function of hlghlight mode. ~hen the stored value is 0, high speed blink is disabled.
~7hen ~he s~ored value is 1, high spee~ blink is enabled.
Bit 1 When bit 3 of R22 is 0, bit 11 of the address for font addressing is set to the same value. When bit 3 of R22 is 1, it is ignored.
Bit O When the value of the scan line in R23 is equal or less than 7, it is used for bit 10 of the address for font addressing.

R23. Background color table Biks 7-0 When color mode is selected (~i~ 7 of R18 is one), back~round color part o~ character attributes is decoded by this bit accay.

- 16 - ' ~ackground attribute BG color R B G reEerence ~i~
O O O bit O
O O 1 bit 1 O 1 0 bit 2 O 1 1 bit 3 1 0 0 ~it 4 1 0 1 ~it 5 1 1 0 bit 6 1 1 1 bit 7 note:Reference bit = O White background - 1 Black background ~reverse video) ~24: Start address of image bu~fer high (write) Bit 7 Ignored Bits 6-0 Most significant bits of start address of image huffer.

~25- Start address of image buffer low (write) Bits 7-0 Least significant bits o~ start address of image bu~fer.

R26; Display memory 213 address m~sk ~write) . .

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Bit 7 ~na~les or disables read/write accessing of display memory 213.
Bit 6 Ignored Bits 5-3 Bits 15-13 o display memory address fro~
processor 201 to display memory through the RA~
select #l is masked by this bit array.
Bits 2-0 Bits 15-13 of display memory address from processor 201 to display memory theough the RAM
select ~2 is masked by this bit array. By this feature, con~ig~ration o~ memory address can be increased.

R27: Test mode (write) Bit 7 Indicates test mode. When the stored value is 0, normal mode is selected. When the stored value is 1, test mode is selected. When in test mode, memory accessing is enabled only by scan control section and memory addressing from ot~er sections is ignored.
~its 6-3 Ignored 8it 2 Controls read cycle time of video ~AM. When it is 0, read memory cycle time is 5 machine clock cycles.
When it is 1, read memory cycle ~ime is 4 machine cloc~ c~cles.
Bi~ 0 Control6 w~ite cycle time o~ display memory 213.
When it is 1, write memory cycle time is ~ machine , -clock cycles. When it ic ~ ~rite memory cycle time is 4 machine clock cycles.

~28: Test status - 1 (read) Bits 7-0 ~hese bits are used for diagnostic purposes.

R29: Test status - 2 ~read~
Bits 7-0 These bits are used or diagnostic purposes.

R30: Dat~ loop back hi~h (read) Bits 7-0 These bits a~e used for diagnostic purposes.

R31: Data loop back lo~ (read) Bits 7-0 These bits are used for diagnostic purposes.

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Mode control register This is a 6 bit regist-er with the I/O address 3D8E7. This register controls status of the display control circuitry 211 as follows:

Bits 7-6 ~gnored Bit S When the stored value is 1, this bit will change the character background intensity to the blinking attribute function for alphanumeric ~odes. When the high order attribute bit is not selected, 1 background colo~s (or intensified colors) are available. For normal operation, this bit is set to 1 to allow the blinking function.
it 4 When ~he stored value is 1, high-resolution mode (640 by 200) is selected for black and white graphic mode. One color o~ 8 can be selected ~for emulation) on direct drive sets in this mode by using the mono mode register or graphic mode register.
it 3 When .he stored value is 1, the video signals at times o~ mode changes are enabled.
it 2 When the stored value is 0, the color mode is selected. When the s~ored value is 1, black and white mode is selected.
Bit 1 When the stored value is 0, 320 by 200 graphic mode is seLected. When the stored value is 1, alphanumeric mode is selected.
it 0 When the stored value is 0, 40 character ~y 25 line alphanumeric mode (low resolution) is se~ected.
~Yhen the stored value is 1, 80 charac~er by 25 lin~: alphanumeric mode (high resolution) i5 se~ec~d.

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The following is a listing o~ the modes selected by this register:

Bits 5 4 3 2 1 0 Selected function ~ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 0 1 1 0 0 40 by 2S alphanumeric black & white 1 0 1 0 0 0 40 by 25 alphanumeric color temulation) 1 C 1 1 0 1 80 by 25 alphanumeric ~la~k and whi~e 1 0 0 0 0 1 80 by 25 alphanumeric color ~emulation) x 0 1 1 1 0 320 ~y 200 black and white graphics x 0 1 0 1 0 320 by 200 color qraphics (emulation) - x 1 1 1 1 0 600 by 200 black and white g~aphics Figure 3~a) is a schematic illustra~ion of the LCD 209 which is comprised of an array of pixels 301. In the preferred embodiment, the LCD 209 has a resolution of 640 pixels in the horizontal direction and 256 pixels in the vertical direction. The LCD 209 has a capacity to display 25 cows o~ characters with 80 chacacters in each row. This is a common configuration or a CRT display.

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~ he pixels 301 are qrouped into respective character cells 303 which, in the preferred embodiment, include an array o~ pixels 3Ql ~ wide by 10 high. The normal character cell for an LCD device is a square array o~ pixels such as an 8 by 8 array shown in cell 305. The use of a character cell greater in height than in width ' - 21 --. .

contributes to the readability of an LC~ device and is the reason that a rectangularly shaped ceLl was selec~ed for the preferred embodiment. As will be explained below, however, the size of a character cell is programmable ~or 1exibility in application.
The intercharacter and interline spacing in the preferred embodiment is one pixel each.

In the preferred embodiment, the display mem~ry 213 has a capacity of 48~ bytes divided in segments of 16~ bytes or the ASCII ~ode RAM 221, 24K Bytes foe the screen image RAM 223, and 8K B~tes EGr the font pat~ern RAM 225. The display control 211 has ~our major control ~odes including: chara~ter mode in black and white (B & W), character mode in color simulation, graphic mode in color simulation, and direct bit map mode.

In any of the control modes, read or write operations of the display data by the processor 201 are done through the LCD-control-

2 217. If the character display mode has been selected, the LCD-sontrol-2 217 scans the ASCII code R~M 221 at every idle cycle and converts ASCII-coded character data, in acordance with associated attribute bits, into screen image data by using the ~ont data stored in the font pattern RAM 225. The converted display data is stored in the screen image ~AM 323. If the graphic mode has been se~ected, the LCD-control-2 217 conver~s ASCI~-coded graphic data stored in the ASCrI code RAM 221 into appropriate ~ 3 ~

pixel image data and writes the pixel ima~e data into the screen iinage RAM 223.

The LCD-control-l 219 scans the pixel image data stored in the screen image RAM 223 and transfers the image data to the LCD
209 Eor display in accordance with LCD scan timing~ The font pattern RAM 225 is accessible by the processor 201 during idle time~

The p~ocessor 201 sends ASCII-coded display data to the LCD-cont.rol-2 217 in the ~orm of two bytes, a code (or data) byte and an attribute byte. In a direct bit map mode, the processor 201 sends display data directly to the screen image RAM 223.

When any control mode except the direct bit map mode is selec~ed, and if the rnode register indicates the B & W mode, the ~CD-control-2 217 converts the ASCII-coded data into pixel data by accessing the ~ont pattern ~AM 225 and performing lo~ical operations in accordance with the value of the attcibute byte.
If the mode register indicates color simulationt the operations per~ormed are almost iden~ical to the B & 5~ mode but processing of the attribute byte is dif~erent due ~to access of the color table register ~or converting the data associated with the color attribute to a selected pattern o~ B & 5~ pixels. I~ graphic mode in color simulation is selected, the data s~oced in the ASCII-- ~3 -.

3~i cocle ~AM 221 is trans~erred to appropriate locations in the screen image RAM 223 without accesses of the font pattern RAM
2~5.

If reverse video characters are to be stored in the screen image RAM 223, the LCD Control-2 217 changes the background color in~o black and the color o the character stroke into white. In the e~ent characters with attributes desi~nating blink are to be stored in the screen image RAM 223, the LCD-control-2 217 will cause selected portions of the display 209 to display character data alternately with an all white character cell, or an all black character celL in ~he event the character is to be displayed with reverse video.

The LCD-control-2 217 also implements the display of highlighted characters and half-tone ima~es. In the case of hiqhlighted characters, the LC~-control-2 217 accesses a second set of font data sto~ed in the font pattern RAM 215, e~g., a bold font, during the conversion of ASCII-coded data to screen image data. Half-toninq is accomplished by alternating the display of a selected character with all white pixels to provide a visual hal~-tone image.

In the character display mode, character data i~cludes 2 bytes consistin~ o~ a charac~er code ~yte and an a~tribute byte.

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The following shows the definition of the 2 ~ytes during operation i.n the B & W control mode.

BL R G B I R G B
CElARAC~ER CODE - - - - Background Foreground -- -- CHA~CTER ATTRIBUTE -- --,~ .
BL: Blink attribute causing the alternate displa~ of a character cell and a cell filled by unique data. e.g., all ~hi.te pixels, defined by background.

I : Intensity attribute to display characte~ with either high-light ~y selecting an alternate font or dimmer ~y blinking at a h;gher rate than the response time of the LCD 209.

Background and foreground attribute portions are coded as follows:

Background Foreground R G B R G B
0 0 0 0 0 0 Non-display, ~ill by white pixels O O O O O 1 Underlirle 0 0 0 1 1 1 Black character/white ~ackground 1 1 1 0 0 0 White character/black background 1 1 1 1 1 1 Non-display, ~ill by bl~ck pixels , ~2~

The followin~ shows the deinition of 2 bytes of character data in ~he color simulation mode. Because the LCD 209 cannot represent multi-colors naturally, the color attribute will project to specific black and white combinations with programmable threshold.

lS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ~ R G B I R G B
- - - - CEI~RACTER CODE - - - - Background ~oreground - - - CHA~CTER ATTRIBUT~

BL: Blin~ attribute to alternate norma~ display character cell and a cell filled by unique data, e.g., all white pixels, de~ined by background.

I: Intensity attribute to display character ~ith either highlight by selecting an alternate font or dimmer by blinking at a higher rate than the response time of the LCD
209.

Background; 3 bit color attri~ute is used as bit addr~ss ~o access the color table regis~ec.

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R G B Bit Address in Color Table Register O O O O

If accessed bit in the color table regis~er is O this character cel~ will be displayed as a black character on a white background, and if it is 1 then the cell will be displayed as a white character on a black background. The correspondence between color a~tribute and the cell display combination can he programmed by loading appropriate values into the color table register. The foreground ~its have no meaning.

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Font data stored in the font pattern ~AM 225 is always treated as a cell, and a display cell size is programmable with ~he exception that the celL width is~fixed as 8 pixels, but may be elon~ated ~o 16 pixels (low ~esolution mode) with B pixe:l resolution by hard~are. Character cell heigh~ is programm~le ro~n 1 ~o F pixels.

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A character cell is de~ined as total space including charactee body, inter-character space and inter-line space. In the font pattern RAM ~25, an 8 pixel row in a cell is treated as a byte o display data and the MSB in a byte o~ display data represent~ the Left most pixel on the screen and the LSB the right most pixeL.

The 8K bytes of the ~ont pattern RAM 225 can be managed as our 2048 bytes segments corresponding to 256 character patterns with widths of 8 pixels and heights o~ 8 pixels to realize multiple font selection. rhe usage oE a character cell with height greater than 8 pixels will enable up to two diferent fonts to be s~ored in two 4096 byte segments.

The actual byte address in hexadecimal for a particular row in the display cells is generated ~s follo~s:

Address = C6000H + ~FS I * 1000H) + (FSO * 800~) +
(ROW2 * 400H) + (ROWl * 200H) -~ ~CD * 2) + ROWO

FSl: Xt is the high order bit of the Eont pa~tern RAM
seyment select bits. If highlighted ~ont is enabled, this b}t is altered by the interlsity bit.

-- 2~ --- ~ 2~3 ,t2 ~SO: It is the low order bit of the font pattern RAM segment select bits. If a character height greater than 8 pixels is selected, this bit is altered by RO~3.

ROWl-ROW0: These 4 bits represent a particular row in the character cell. I~ the character height is less than or e~ual to 8 pixels, then ROW3 does not have meaning.

CD: It is an 8 bit character code enablin~ the definition o~ up to 256 distinct charac~ers, including symbols.

In the graphic display mode, graphic data to ~e displayed is treated as a byte corresponding to 8 pixels, and is directly trans~erred to storage locations within the 16~ bytes of the screen image RAM 225. The screen image RAM 225 is separated into two segments of 8~ bytes each corresponding to an odd row image memory and an even row image memory. The even row image memory stores 80 bytes by 100 rows (rowO, row2, .... rowl98) o image data, and the odd row image memory stores 80 bytes by 100 rows (rowl, row2, ... rowl9g) oE image data.

The actual byte address in hexadecimal ~or a particular group o 8 horizontal pixels on the screen is generated as ~ollows:

.3 r~

Address = MOD(ROW~2) * BAOOOH + MOD(ROW~1)/2) ~ B8000 INT~E~OW/2) * 50H ~ COL

MO~: It represents a modulo function IN~: It eepresents an inteqer func~ion ROW: It is the vertical location count of rows on the sc~een assuming that the topmost row on the screen is row O
COL: It is horizontal location count in 8 pixel units assuming that the leftmost group of 8 pixels is 0.

Figure 3(b) through 3~d) schematically illustrate a further ~eature of the present invention wherein the LCD 20~ can comprise 1, 2, or 4 segments or planes. If the LCD 209 comprises a single plane, data is transferred to and displayed thereon character by character and line by line. If the LCD 209 is divided into multiple planes, however, a number of chaeac~ers e~ual to the number of planes can be transferred in parallel from the screen image RAM 223 to the LCD 209.

~ s shown in Figure 3~b~ a single plane LCD includes L lines (e.g., 25) with each line ,including`N words (e.~. r ~0) . Each word cor~esponds to a cllaracter to be displayed. Assuming that the first character to be displayed is s~ored in memory address A

3~

in the screen image ~AM 323, t~en A+N 1 is the address of the last character of the first line, A~(L-l)N is the address o~ the ~irst character o~ the last line and the last character in the last line is stored at address A+LN-l. Thus, the val~e L is ~he line number and the value N is the line ofset meaning the character position within a line.

Figure 3(c) illustrates an embodiment wherein the LCD 209 is divided into plane-A and plane-B. Lines l - L are included in plane-A and lines L+l - 2L are included in plane-B. Data word l in line l is stored at plane-offset address A, e.~ r r and data word l in line Lfl is stored at plane-offset address B, e.g.
~=A~L~.

Figure 3(d) illustrates an embodiment wherein the LCS 209 comprises fo~r planes, i.e., plane-~, plane-B, plane-C, and plane-D. In this embodiment, the line offset maximum, N, takes a value of one-half oE that with respect to the embodiments of Figures 3(b) and 3(c). The addresses of the first data word in the first line o~ plane-~, plane-B, plane-C, and plane D are A, B=(L-~l)2N, C=N, and D=(L+l)2N~N, respectively.
`t F;gure 3(e~ schematically illustrates the correspondence between addresses in the screen image RAM 223 and the LCD 209 in an embodiment wherein the LCD ~09 includes two planes, i.e., ., I

plane-A and plane-~. Assuming tha~ the plane offse~ address A is equal to address 0 within the screen image ~AM 223, words are transEerred fro~ the screen ima~e RAM 223 ~o plane-A of the LCD
209 beginning at address 0 and concluding at addcess L~N-l).
Within plane-B, the data words stored a~ addresses LN - 2LN-l are displayed.

IE the LCD 20g is comprised of four planes, the plane-offse~
addresses for planes A, B, C, and D would be o, N, (L+lJN, and ~L+l)N+N, respectively.

Figure 4 illustrates a block diagram of LCD-control-l 219 wherein display data is transEerred from the screen image RAM 323 to the LCD 209. This block diagram illustrates t~e circuitry for generating the display location in the LCD 209 for the data to be dis~layed and for transferring display data from ~he screen image RAM 223 to the ~CD 209.

During initiation of the computer system, e.g., at power-up o~ the processor 201, certain control values are transferred to the registers 403-411. The control values relate to the numbec oÇ planes within the LCD 209 and to the numbec o~ wocds included in each plane. For example, Fi~ure 4 illustcates an embodiment o~ the LCD-control-l 219 wherein the LCD 209 includes planes A
th~ougb D. Thus, re~ ~ 403 stores the above-discussed plane -- 3 ~

. .

~2~ 35 o~set ~, which may take on ~ zero value when the ~icst storage word in the scceen image RAM 323 stores the character ~o be displayed at location 0 of row zero oE the LCD 209.

Similarly, reg B 405, reg C 407, and reg D 409 store the values of plane-o~fset B, plane-offset C, and plane-offset D, respectively. These values correspond to the location on the LCD
209 or the display of the irst character in ~lane B, plane C, and plane D.

~ eg F. 411 is loaded with a ~alue equal .o the oumber of characters in each row o~ a plane. Assuming that the LCD 209 displays 80 characters in a row, the value stored in reg E 411 for the embodiments o~ the LC~ 209 shown in ~igs. 3(b) and 3(c~
will be 80 and the value stored in reg E 411 ~oc the embodiment of Fig. 3~d) will be 40.

The outputs of the registers 403-409 are supplied as inputs to a multiplexer 413. The signals PLNSELO and PLNSELl control the multiplexer 413 to selectively output the values s~oced in the regicters 403~409 to one input of an adder 415. ~he value out~ut~ed by the multiplexec ~13 com~rises a 16 bit base offset address ~or one o~ the planes A through D.

. - 33 -31~

The output of the adder 415 comprises a 16 ~it address o~ a character position on the LC~ 209 for one of the planes A through D. The first value outputted hy the adder 41~ for each o~ the p~anes A through D corresponds to the first display location on the LCD 209 within each of the planes A through D and will equal the offset values stored in the registers 403 - 409. For each of the other characters in a row, it is necessary to increment the base o~fse~ values. The increment is generated by the adder 417, register 419, ~nd the counter 421.

~ he value stored in the reg S 411 is supplied to one input of the ~dder 417. The other inp~t to the adder 417 receives the output of the reqister 419, ~I~S~0-15. The output of the register 419 is also loaded into the counter 421 under the control of the line load signal, LINELD. The register 419 stores the output of the adder 417 and is loaded with that value under the control of the line end signal LINEEND. In the embodiment described herein, the values stored in the various registers and adders are expressed in twos-complement. At initiation, the values stored in the register 419 and the counter 421 are set to zero. The value s~ored in the counter 421 is incremented by one under the control of the data ready signal, DATARDY. The generation oF D~TARDY will be described hereina~ter.

- 3~ ~

3 ~ ~

A line word register 423 is loaded at initiation wit~ a value eq~al to one-half of ~he number o~ characters displayed in a row o~ each plane. ~hus, in the embodiments of Figs 3(b~ and 3(c) the stored value is 40 based upon the assumption of the LCD
209 displaying 80 characters in a ro~. In the embodiment of Fig 3(d), each row includes two planes and, therefore, t~e value stored in the line word register 423 is 20. The stored value takes into account the ~act that two 8-bit words or characters are transferred at one time rom the screen image RAM 223 as t~e signals VRAMDO-15 .

The two's complement of the value stored in the line word register 423 is loaded into a timing counter 425 upon the occurrence of LINE~D which is generated when the counter 425 overflows. The timing counter 425 is incremented under the control o~ the output of an OR gate 429 which receives as inputs DATARDY and the local clock siqnal, LOCLK. The value stored in the timing counter corresponds to the number o~ two-word clata transers from the screen image RAM 223 to the ~CD 209.

A line number register 429 is loaded at initiation with the number of lines to be displayed within a plane. In the em~odiment of ~ig. 3(b), ~his number i5 equal to the maximum number of lines that can be displayed on the LCD ~09. In the embodiments of Figs. 3(c) and 3(d), the value stored in the ~2f~ r~
register 429 is one-half the maximu~ number o~ lines that can ~e displayed on the LC~ 209 because the LCD ~09 is vertically divided into two planes. The value stored in the registee 429 is expressed in two's complement and is incremented when all data words within a display line o~ the LCD 209 have been transferred. Upon overflow, the timing counter 431 is reloaded with the value stored in the line number register.

As will be ~pparent to one skilled in the art, the display ~arameters, i.e~, the number o~ lines and characters per line, of the LCD 209 are progrcmmable. ~his provides flexibility to the computer and ultimately to the user.

~ he registers 441, 443, 4~5, and 447 are used in the actual trans~er of display da~a from the screen image RAM 323 to the LCD
209. Each of these registers is associated with a different one of the planes of the LCD 209. Thus, data to be displayed in plane-A is received by register A 441, plane-B by register B 443, plane C by register C 445, and plane D by register D 447.

In the embodiment of Fig. 3 (ci, only two planes are provided in the LCD 209 and, therefore, only`register A 44l and register B
443 would be necessary. Similarly, in the single plane embodimen~ o Iig. 3(b), only register A ~41 would be utilized.

3~
Since the four da~a t~ansfer paths shown in Figure 4 are identical and operate in parallel only one data ~ath will be described in detail.

Two words of data, VRAMD0-15, from the screen image RAM 223 are loaded into the register 441 and are shifted ~o a parallel-to-serial converter 448 under the control of the signal PLANASTB.
~rhe shifting o~ the data from the register ~ 441 to the parallel-to-serial converter 448 generates the signal DATARDYA which is supplied to an input of an AND gate 430.

The parallel-to-serial converter 448 comprises a shift register 449A and a multiplexer 451A. The 16 bits of data, AD0-15, eeceived as inputs by the shif~ register 449A, are outputt~d in groups of four bits each, i.e., N~00-3, NA04-7, NA08-11, and NA012-15, under the control of t~e selection signals N~LS~L0 and NBLSELl. The output of the multiplexer 4SlA is supplied ~o plane-A o~ the LCD 209 as ~he data PLANAD0-3 and to a buffer 453.

As evident rom Figure 4, the registers 443, 445, and 447 generate respective da~a ready signals DATARD~B, DATARD~C, and DATARD~D. These ~igna~ are also sùpplied as in~uts to the AND
gate 430 with the resul~ that the signal DA~ARDY will be generated with a high value capable of incrementing the timing eounter 425 aft~L the displa~ data has been shifted from each of the registers 441~447n In the case o~ single or du~l plane embodiments o~ the LCD 209 ~he appropriate values for the inputs signals to.

~ n operation, the initial values corresponding to the ernbodiment of the LCD 209 are loaded into the registers 40~, 405, ~07, 409, 411, 423, and 429, as described above. ~he ~a7ues re~lect not only the number of planes included in the LCD 209 but al.so the number o~ characters in a row and the number of lines in the LCD 209. The adder 415 outputs the display addresses within each plane of the LCD 209 and the multîplexers 451A-451D begin to transfer screen image data to the LCD 209.

Assuming the four p7 ane embodiment of the LCD 209 as shown in Figure 3(d~, the data words are transferred to the LCD 209 by the four multiplexers 451A, 451B, 451C, and 451D. Each time two data words, that is 16 data bits, are transferred from the registers 441, 443, 44~, and 447 to the shift registers 449A, 449B, 449C, and 449D, respectively, the signal DATARDY is generated with a high value ~o increment the timing counte~s 425 and 421~ After 20 two word data transfers have been made to the respective shift registers, the timing counters 421 and 425 will overflow. ~his resul~s in the generation oE the signal L~NELD
which resets the counter ~25 to the value stored in ~he line word regis~er 423, increments the timing counter 431, sets the co~nter 421 to the value stored in the register 419, and Loads the register ~19 with the current output of the adder 417.

As a result, the counter 421 outputs the incremental address which, when added to the plane base address stored in the registees 403-409, generates the screen addresses of the LCD 209 in the second row o each display plane. Subsequent operations trans~er the data words to be displayed in the second line o each plane at the screen locations outputted by the adder 415. After the data comprisin~ the secon~ llne in each plane o~ the LCD 2G9 have been displayed, the third and subsequent lines are displayed.
When the last line in each plane has been displayed, the timing counter 431 overf~ows and is reset to the value s~ored in the line num~er register 429. This causes the register 419 ~o be reset to zero. The data in the screen image RAM 223 is again transferred to the LCD 209 ~o refresh the display and to change the displayed data to re~lect changes in the data stored in the screen image ~AM 223.

Figure ~ is a high level block diagram o~ the LCD-control-2 217. The LCD-control~2 217 includes the status and control regi~ters previously described, address ~nd data paths to and ~rorn the CPU 201, the ASCII code R~M 221, the screen image RAM

~2~
223, the font pattern RAM 225, and circuitry for modifying data in accordance with associated attributes.

The status and control section 501 includes the registers Rl, R6, R9-~15, and R18-R27. The functions of these registers have been described above, and the embodiment thereof will be discussed hereinafter~

An B bit data hus from the CPU 201 provides the signals DB0-7. The data bus to the three RAMs 221, 223, and 225 within the memory 213 i5 indicated by the signals MBO-lS. A memory bus shared by the CPU 201, the memory 213, and the LCD-cont~ol-2 217 is indicated by the signals A0-15.

Upon initialization, select register logic 503 is controlled by five bits of the address signal AO-7 to enable initial values for the status and controL values to be loaded into the appropriate conteol and status registers from the CPU data bus DB0-7. A~ter initialization, when it becomes necessary to change the values in any of the status and control registers, the select register logic 503 is enabled to ~eload the appropriate register or re~isters.

Data supplied ~rom the CPU 201 can be directl.y trans~erred ~to ~he memory 213 through ~wo write data latches S03 and SOS.

The data latches enable two 8 bit data trans~ers from ~he CPU, .

i.e., CPUDO-7, to be trans~erred in parallel on the 16 bit memory bus as memory data MEMBO-15.

Similarly, a 16 bit data transfer from the memory 213, i.e.~
MEMIO-15, can be outputted to the CPU 201 as two 8 bit data words, CPUDI0-7, through a pair o~ read ~ata latch~s 507, 509. The memory data, MEMIO-15, can also ~e supplied to an ASCII code latch 511 which receives the high order 8 bits, MEMI8-15, and an ASCII
attribute latch 513 which receives the low order 8 bits, MEMI0-7 The ASCII latches 511, 513 are employed to receive data from the ASCII CGd~ RAM 221.

The contents of the AS~II code latch 511 are transferred to the memory bus as the low order 8 bits, AO-7, o~ an address in the font pattern RAM 225. The high order 8 bits, A8-15 are supplied by font select lo~ic 515 which eeceives inputs from the font select register, R22. The 16 bit address is used to acce~s specific memory locations within the font pattern ~AM 225 which store screen image data correspondin~ to ASCII-coded data. The actual bit representation of the AscIr-coded data is used as part of the address within the font patte~n R~ 225.

~ 'he two wo~ds o data returned rom ~he ont pattern RAM 225 are received by the ~ont data latches 517, 519. The low order 8 ~it5 are received by the latch 519 whic~ supplies them to the atteibute processing circuitr~ 521 and to the memory bus as t~e low order 8-bit word AO-7. The font data latch 5~ supplies the high order 8 bits to the a~tribute processing circuitry 521 and ~o the memory bus as the high o~der 8-bit word A8-15. The data bits transferred directly from the font data latches 517, 519 are transferred by the memory bus to the screen image RAM 223.

The attribute processinq circuitry 521 receives the data from the font data latches 517, 519 eight bi~s at a time and modifies the ~eceived data under the control of the attribute control circuitry ~23. The modified data is supplied to the memory bus through the output regular mode font data latches 525, 527 or through the ~old mode font data latches 529, 531. In the bold ~low resolution) mode, each displayed character is two character cells wide.

The addresses wi~hin the screen image RAM 223 for storing screen image data are generated by a counter 541 which receives the image start address, ISAO-15 from the image start address registers R24, R25. An o~fset value can be added to the output of the c~unter 541 by an adder circuit 543. The offset is generated by an adder 545 and is stored in a latch 547 coupled thereto. The ou~put of the addec 543 comprises a 16 bit image plan address, IMPAO-15, which is supplied ~o the memory bus. A
pair oE data latches S~9, 551 is ~rovided to transfer the ima~e - 42 - ~

3~

plan addcess from the memory ~us to the CPU 201 as loop back data LBD0-lS. A next line address latch 553, 555, is provided to receive an address ~rom the memory bus and to supply the received address to the counter 541 through an adder 557 or to the CPU 201 as loop back data.

Figures 6-224 comprise detailed logic diagrams of a preferred embodiment of the LCD-control-2 217 as shown in Figure 5 and generally described above. As shown in Figure 6, the memory bus includes a pair of 8 bit latches 601, 603 which receive the memory bus signals A0-1~ from the CPU 201 and the memory 213. The signals AO-7 are transferred to a latch 605 and are subsequently designated M~M~0-7. The bits AB-ll are transferred to a latch 607 to become the bits MEMB8-11. The four high order bits, MEMsl2-ls outputted by the latch 607 are supplied by the display memo~y address mask register R26.

The eight bit data bus, D0-7, coupled with the CPU 201, is received by! an input latch 609 which outputs the CPU data, CPUD00-07. Data is transferred to the CPU 201 via an output latch 611. Clock signals employed within the LCD-control-2 are generated by an oscillator 613 and outputted by a latch 615.

The select register logic 503 ~Figure 5) is embodied by decoders 621, 623 and N~ND gates 625-645. The inputs ~to the 3 ~1 decoders 617-623 include the signals REGSEL0 ~ REGSEL4 which comprise the CPU data bits CPUD10 - CPUD14 outputted by a la~ch 647. The latches 621, 623 out~ut enable signals U~18WR-UR27WR
or controlling writing of corresponding status and control registers. The decoder 623 also outputs the signals UR28RD-UR3LRD which are read enable signals.

~ he NAND gates 625-629 and 639-645 output LCD control register write enable signals UX9W~-U~25WR, respectively. The NAND gates 631-637 output ~CD control register read con~rol signals U~12RD-UR15R~, respectiveLy.

Figure 7 illustrates circuitry 701 for ~enerating CPU access request signals. While this circuitry plays a role in the operation of the LCD-control-2 217, a detailed description thereof will not ~e set forth because such description of the circuitry 701 is not necessary for an understanding of the present invention.

Figure 7 also illustrates embodiments of the write data latches 503, 505 which receive as inputs CPU data, CPUD00-07, and respect~vely output to the memory bus MEMB8-15 and MEMB0-7. Similarly, the read data latches 507, 509 are shown as receivin~ as inputs MEMB8-lS and MEMB0-7, respectively, and generating as outputs CPUDI0-7 which are transmitted to the CPU 201.

3~
-Figures 8-L0 illustrate embodimentS of the sta~us and control registers discussed above. The mode control register is embodied as an edge-triggeeed flip-flop 801 which selectively outputs the blink enable signal (BLKENB), the video enable signal (VI~ENB), the graphic mode signal (~RAPHrC~, and the high resolution signal (EIIRES) in accordance with the CPU data, CPUD00-07. The horizontal displayed regis-ter Rl and the vertical displayed register R6 are similaely embodied as edge-triggered flip-flops 803, 805, respectivel~, which receive as inputs CPUD00-07.

The register R12 storing the start address of the character/image buffer (high) is embodied as an edge-triggered flip-flop 807 receiving the input signals CPUD00-07 and a transceiYer 809 receiving the input signals CPUDI0-7. Data to be written into the register R12 is supplied by the flip-flo~ 807 whereas a read out of the register R12 is trans~erred t~rough the t~ansceiver 809.

The register R13, which stores the start address of the character/image bu~er (low), is embodied as an edge-triggered flip-flop 811 and a transceiver 813. The data to ~e written into the register R13 is supplied throug~ the edge-triggered flip-flop 811 ancl data ~o be r~ad from the ~e~ister R13 is transferred throu~h the transceiver 313 - ~5 -~. 2, ~ . 3 ~

The cursor address (high) register, which is the register R14, is supplied by an edge-triggered flip-flop 815. A transceiver 817 is emplo~ed to transfer the values stored in the register ~14 to the CPU 201. Similarly, the register R15 storing the cursor address (low) is em~odied as an edge-triqgered flip-flop 819 and a transceiver 821.

The register R9 storing the maximum scan line address is embodied as an edge-triggered flip-1Op 901. The register R10 controlling the cursor start scan line is embodied as an edge-triggered flip-flop 903. An ~ND gate 9~5 coupled to the ~lip flop 903 through an inverter 906 generates the cursor inhibit signal C~RINH. The register Rll controlling the cursor end scan line i5 embodied as an edge-triggered flip-flop 907. The flip flops 901, 903, 907 all receive the CPU data, CPU~00-07, as inputs .

The operation mode register ~18, the scan interval select register R19, and the blink interval select register R20 are embodied as edge-triggered flip-flops 909, 911, and 913, respectively.

The underline position and over-scan protection re~i.ster R~l/ the ~ont select re~ister ~22, and the background color - ~5 -register R23 are embodied by the edge-triggered 1ip-~lops 915, 917, and 919, respectively.

Figure 10 illustrates the image buffer start adaress (high~
register R2d, the image buffer start address ~low) eegiste{ R25t the display memory mask register R26, and the test mode register ~27 as being embodied by edge-triggered flip-flops 1001, 1003, 1005, and 1007. A multiplexer 1009 receives the outputs of the flip-flop 1005 and is coupled to the AND gates 1011, 1013, and 1015 to generate the three high order address mask bits. The test-status-l register ~28, tesc-status-2 register R29, d~ta loop back (high~ register R30, and the data loop back (low) register R31 are embodied as transceivers 1017, 1019, 1021, and 1023, respectiYely, to selectively output the data CPUDI0-7.

Figures 11 and 12 illustrate circuitry for generating timing and control signals used within the LCD-control-2 217, including timing signals or accessing the memory 213. Also shown in Figure 11 is a priority encoder 1101 including a D flip-flop 1103 which outputs the signals LCDS~L, CPUS~L, and SCNSEL to control access to the LCD 209, CPU 201, and memory 213, eespecti~ely. The function of the timing circùitry will not be~described in detail because such description is not necessary ~or an understanding of the present invention.

~ ~7 -~L~1'`*~ ~Q.D~

Figure 13 illustrates ciccuitry for generatinq additional timing and control sic3nals. A scan control sequencer 1301 9enerates timing and control signals ~or reading the ASCII code RA~ 221, accessinc3 the Eont pattern RAM 225, and writing screen imag~ data into the screen image RAM ~23.

Figure 14 illustrates an em~odiment of the c~ounters and comparators (shown in Figure 5) connected to the horiæontal displayed registef Rl, the vertical displayed register R6, and the maximum scan line address register R9. As embodied herein, a horizontal character counter 14~1 includes a compara~or 1403 having one set of inputs HDISP0-7 corresponding t~ t~e contents o the register ~1 and a second set of inputs generated by counters 1405, 1407. The counters 1405, 1407 are incremented each time an ASCII code character is converted to a screen image character by the LC~-control-2 217. The count stored in the counters 1405, 1407 is e~ual to the present value stored in register Rl. An end ~f line signal, LINEND, is generated by a D
flip--1Op 1409.

A vertical line counter 1411 includes a comparator 1413 having one set o inputs, VDISP0-7,`~supplied by tlle v~rtical displayecl rccJister ~6 and a second set o inputs supplied ~y the coutlters 1415, 1417. The counters 1415, 1417 are incremented ~y the LINEND signal and s~ore an indication of the line num~er - ~3 -- -being stoced within the screen imaqe RAM 223. When the line number stored in the counters 1415, 1417 is equal to the preset value in the vertical displayed register R6, a D flip-~lop 1419 generates a frame end signal, UFRAMEND.

A character row address counter 1421 comprises a compacator 1423 having one set of inputs receiving the contents of the maximu~ scan line address register ~9 and a second set o~ inputs receiving the value stored in a counter 1425. The output oÇ the counter 1423 is the maximum row control signal, MAXROW.

Figure lS illustrates an embodiment oÇ the font data latch S17, SL9, the ASCII code la~ch Sll, and the attribute latch 513.
The values of the attributes associated with an ASCII code word are outputted ~y the attribute latch and include the control signals ~or the blink bit (BLBIT~, bac~ground red (BGRED), bac~ground green (BGGRN), background blue (BGBLU), intensity bit ~IBIT), Çoreground red (~GRED), foreground green ~FGG~EN), and foreground blue (FGBLU1 The signals BGRED, BGGRN, and BGBLU are employed as the selector signals of a.color emulato~.multiplexer 1510. The inputs to the multiplexer 1510 comprise the outputs of the edge triygered Çlip-Çlop 91g Which is an em~odiment oÇ the background ~color table register R23. Since ~he LCD 209 is not capa~le oÇ

_ ~9 _ .

' . ' ~2~3 ~ -displaying the colors red, green, and blue, the color emulator multiplexer 1501 is p~ovided to select either a light or dark background on the display 209 depending upon the values o~ BGR~D~
BGG~N, and BGBLU.

Figure 15 further illustrates an embodiment of a cursor timing circuit 1503 which includes comparators 1505 and 1507 which compare the output, ~OW0-3, of the counter 1425 to the counters o~ the cursor s~art scan line register R10 and the cursor end scan line register ~11, respectively. The inputs of an AND gate 150g are connecte~ to the outputs o' the comparato~s lS05, 150~. The o~tput, CSRPOS, of the AND ~ate 1509 controls display of the cursor on the LCD 209.

!

; A black and white mode attri~ute decoder 1~ enerates the control signals no-display white, UND~T, which causes all pixels in a character cell to be displayed as white and no-display black, NDBLK, which causes all pixels of a character cell to be displayed as black. The decoder 1511 further generates the reverse v:ideo control signal, ~WID, which causes all pixels in an associated character cell to display reverse values.

An underline timing gf:llerator lS13 includes a counter 1515 which at one set o~ inputs receives the outputs of the counter l~S and at anot~er set of inpu~s receives the value stored in - 50 - , I

3~

the underline position register R21. An ~ND gate 1517 coupl~d to the outputs of the counter 1513 and the decoder lSll generates the underline contro~ signal, LNUNDER.

Figure L6 is an embodiment of the attribute circuit 521 o~
Figure 5. A pair of transceivers processing 1601, 1603 receive the two data words (16 bits) in parallel rom the ont data latch2s 517, Sl9 and converts them into two serial da_a words of eight bits each. ~he eight bits o~ each data word are then p~ocessed in parallel in accocdance with the values o~ the attribute bits to qenerate an eight bit .fort data, ~lo~d, FWRD0-7.
~ecause each bit is identically processed, only the processing of bit 0 will be discussed in detail.

Bit zero is supplied as one input of a two inpu~ OR gate L605. The other input to the O~ gate 1605 is the output of an O~
gate 1607 having as inputs the signals LNUNDER and NDBLK. I
either LNUNDER or NDBLK is set equal to 1 (T~UE) then the output of the OR gate 1605 will be 1 indicatins that the pixel in the display ~09 corresponding to bit 0 s~ould be displayed as blac~.

The output of the OR gate 160~is s~lpplied t~ one input of an ~N~ gate 1609~ The AND gate 1609 implemenks several ~unctions which are based upon the controlled blinking of pixels o t~e ~CD
209 ~t selected positions. One unction is half-toning which - 51 ~

~ 3~3 entails blinking of pixels a~ a very high ra~e so that the visual appearance is of a continuous tone be~ween white and black. This function is embodied by a NAND gate 1611 which receives the dim enable signal, DIMEN, and a dim blink clock siqnal, DIMBLK, of high fre~uency. The ~ND gate 1611 unctions as a switch to turn on and of the pixel corresponding to bit zero at a high rate.
~his switching is done through the second input of the AND gate 1609.

A pixel can also be blinked at rate discerni~le visually.
This is accomplished by an AND gate 1613 and a NAND gate 1615.
Blinking of the pixel is controlled by the blink ~it, BLBIT, which is one input to the NAND ~ate 1615. The other input of the NAND gate 1615 is the output of the AND gate 1613. The AND gate 1613 outputs the blink frequen~y signal in accordance with the blink clock signal CHA~BLK.

The output of the AND gate 1609 is supplied to one input o~
an 0~ gate 1617. The other input to the O~ gate 1617 is the output of a cursor blink AND gate 1619. I~ the cursor position includes the pixel associated with bit 0, the pixel will be blinked at a rate determined by the cursor blink clo~k signal, CS~LK. The frequency of the cursor blink clock signal, CSRBL~, i.5 pre~erabl~ dif~erent ~rom, e.g., twice the ra~e of, ~he ..3~

requency of the character blink clock signal, CHAR~L~, to enabl visual discrimination ~etween the two.

The output of the OR gate 1617 is supplied to one input of a NOR gate 1621. The other input to the NOR gate 1621 is the output of an OR gate which receives the color emulator signals BGDARK
and RWID. ~he OR gate 1613 enables the value of hit 0 to be changed to emulate color display through the selection of the ~ackground color, i.e., black or white.

Figure 12 illustrates the circuitLy for implementing the high resolution mode of the LCD 209 and also the embodiments of the latches 525-~31. In low resolution mode each character includes twice as many character cells as in low resolution mode.
This is accomplished by generating data words wherein each data word includes values for controlling Eour pairs of pixels with the pixels in a pair being identical.

'~he output of the attribute processing circuitry 521, i.e., the font data signals ~RDO-7 are supplied to the data latches 527, 525 (Figure 17) and outputted as the signals MEMB8-15 and MEMB0-7, respectively, in high resoIutior~ mode. ~n normal (low) ~esolution mode, bits FWRD~-7 of the ~ont data word are supplied to the latch S29 and ~its FWRD0-3 of the ~ont data word are supplied to the latch 531. The data bit ~WRD7 is supplied ~o ~L r~ 3 5;

inputs 6 and 7 of the latch 529 so that bits MEMB14 and MEM~15 will have equal values. Similarly, inputs 4 and 5 o~ the latch 52g are set to the value o~ ~W~D6 so that bits MEMB12 and MGMB13 will have equal values. Each of the bits ~WRD 0-5 is similarly duplicated in the output bits ~EMB0-11 oE the latches 529, 531.
Selection oE the high resolution or the low resolution mode is accomplished by the attribute bit HI~ES. Graphic mode font data inputs, FD0-15, are transmitted to the rnemory bus MEMB 0-15 through the latches 1701, 1703.

Figu~e 18 illustratec the circuitr~ Eor generating addresses in the ASCII code RAM 221 to enable access of ASCII code ~ords stored therein so that conversion to display image data may be accomplished by reference to the font data. The ASCII code RAM
start address is supplie~ by the registers R12, R13 as inputs to code buffer address counters 1801, 1803, 1805, and 1807. The value stored in the counters 1801, 1803, 1805, and 1807 is incremented to output in sequence the addresses oE ASCII code words stored in the ASCII code RAM 221.

l`he cornparators 1809, 181L compare the output of ~he ASCII
code bu~er address to the present cursor address and sets the ~i~3nals CURSOR and UCURSOR accordin~ly. As previously clescri~ed, the CURSO~ 5i9n~1 iS usecl to control blinking o~ selected pixels to identi~y the location o the cursor.

3'`~ -Figure 19 illustrates circuitry embodying the image data address generator for generating addresses within the display imaye RAM 223 for storing image data produced by converting ASCII
coded data through accesses to the font data stored in the font data RAM 225. The next Line address latch 553, 555 receives the memory address MEMBO-15 from the memory bus and transfers the address to the latches 549, 551 as loop back data LBD0-15 for test purposes. The outputs of the latches are also supplied to incrementers 1901-1907 where the value of MEMB0-15 is incremented by ~ he incremented address is supplied to transceivers 1909 19~.1 .

A second pair of transceivers 1913, 1915 receives the image start address from the registers R24, R25. The contents of the transceivers 1909, 1911 or of the transceivers 1913, 1915 are selectiv21y supplied to an image plane base address counter comprising the counters 1917 - 1923. The counters 1917 - 1923 are lncremented by +l every time all of the pixels within a character cell have ~een converted from ASCII code data to screen image datan Thus, the counters 1917 - 1923 store an address corresponding to the top row o pixèls in a character cell. The counters 1917 - 1923 ~re set to the value stored in t~e transceiver 1913, l9L5 whenever the las~ charac~er in the last row o~ the ASCXX code ~AM 22L has been processed.

1i , r-^

~ igure 20 illustrates the circuitry for generating addresses within the screen image RAM 223 which correspond to the beginning of a line of characters to be displayed on the LCD 209.
Transceivers 2001, 2003 store values which correspond to the number o~ characters in a display line of the LCD 209 in high and low resol~tion modes. This value is preset by ~he register Rl.

If high resolution mode is indicated by ~IRES, then the value HDISPO-7, which is stored in the transceiver 2001, is transferred to the row offset latch 2005~ If low resolution mode is indicated by the s~gnal U~IRES, tl~en HDIS~ DISP7, i. e., a value equal to one half of the vaLue OL E~DISPO-7, which is stored in the transceiver 2003, is supplied to t~e row of ~set latch 2005.

~ he row ofset latch comprises adders 2007 - 2011 and latches 2013 - 2017 which generate the image offset signals IMOFF0-11 corresponding to N times the value initially received as inputs by the adders 2007, 2009. The value N is equal to the line number currently being stored in the screen image RAM 223. Thus, IMOFF0-11 is a value which always corresponds to the beginning of a line to be displayed on the LCD 209~

The e~fective address, i.e., t~e physical a~dress IM~A0-15, within the s~reen image RAM 223 for storing the sc~een image data currently being processed is yenerated by adders 2019 - 2~25.

- 56 - ' 1I

~ D ~

The adders 20L9 -2025 add the line address represen~ed by the signals IMO~F~-ll to the character address IMA~-15.

Figure 21 illustrates circuitry 2101 embodying a scan address control signal generator which generates a signal, U~BRENB, which controls whether an address in the ASCII code RAM
221 or in the screen image RAM 223 i5 being processed. A font selector circuit 2103 is provided to generate bits MEMB10 and ME~ll o~ a rnemory address MEMnO-15 outputted by a pair of transceivers 2105, 2107. In this manner, one of two sets of font data stored in the Eont data RAM 225 call be select~ely addressed.

; Figure 22 illustrates a scan interval selector circuit 2201 ~hich includes a comparator 2203 having a first set of inputs receiving the signals SCNIV0-7 sto~ed in the scan interval register R19 and a second set of inputs receiving the outputs o~
a pair of counters 2205, 2207. The signal UCHIST is generated from the output of the comparator 203 to initiate a scan of the ~emory 213 and the conversion o~ ASCII code data to screen image data. The scan interval is selectable through the counters of the register Xl9. An advantage can be ootained in reduction of power consumption by initiating a re~resh o~ the memory at the lorlgest acceptable intervals~

~ S7 -I

.3~
A clock divider circuit 2209 generates the clock signals ~ATE0-7 having different frequencies. q`his enables a ~link interval selector circuit 2211 to generate the previously-discussed blink control siqnals CHARBLK, CSRBLK, and DIMsLK with diferent frequencies.

Figure 23 and 24 illustrate an embodiment of the memory 213 and circui~ry for memory and input-output decoding. The manner of operation of the memory 213 and the various circuitry shown in Figures Z3 and 24 will ~e apparent to onè of ordinary skill in the art from the description of the LCD-control-2 217 set for~h herein and, therefore, additional description of E'igures 23 and 24 is not necessary.

While the salient features of the invention have been described wi~h re~erence to the drawings, it should be understood that the described embodiment is susceptible of modiication and substitution without departing from the spirit and scope of the following claims.

Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A system for controlling a liquid crystal display capable of displaying data with a first visual tone and a second visual tone to display data with a third visual tone between the first and second visual tones, the system comprising means for receiving data to be displayed on the display, said data having either a first value for causing the display to display the first visual tone or a second value for causing the display to display the second visual tone;

means for supplying said display data to the display; and switch means, connected between said receiving means and said supplying means, for alternately supplying the display with said data to be displayed and said second value at a switching rate sufficient to cause said display to visually appear to be constantly displaying data with said third visual tone when said data to be displayed has said first value.

2. A system according to claim 1 wherein the display comprises a matrix of display pixels being turned on to display the first visual tone in response to said data having said first value and being turned off to display the second visual tone in response to said data having said second value and wherein said switch means comprises:

a source of clock pulses having a frequency equal to said switching rate;

a first AND gate circuit having a first input terminal for receiving said data from said receiving means, a second input terminal, and an output terminal connected to said supplying means; and a gating circuit for selectively supplying said clock pulses to said second input terminal to cause data having said first value received by said receiving means to be outputted by said said output terminal alternately with data having said second value at a repetition rate established by said frequency of said clock pulses.

3. A system according to claim 2 wherein said gating circuit comprises a second AND gate having a first input receiving said clock pulses, a second input for receiving a dim enable signal for enabling the display of the third visual tone, and an output terminal connected to said second input of said first AND gate circuit.