JPS61123883A - Control system for liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a small portable combinator, and particularly to a display device and a display control device used in such a combinator.

[Technical background of the invention]

In recent years, the spread of small combiators and personal combiators has been remarkable. Compared to the combiators of just 10 years ago, the Nonosonal compiators are a fraction of the size and have much greater processing power! Next.

Many of today's delta internal computers offered by various manufacturers are fabricated as one or more integrated circuit chips using LSI or FiVL chips or similar central processing units (CPTRs). i) Adopted. This makes the CPU, in some respects, the current standard for this industry. Accordingly, one or more sophisticated operating systems for each CPU have been developed and are commercially available to users of delta combi crystals. Therefore, when used with a standard CPU and operating system, it provides sufficient processing speed and flexibility for most personal computer users.

With the standardization of CPUs and operating systems, manufacturers of Δ-sonal computers have focused on other features of combi-series computers that are available; making them different among computers and increasing their market share. It is becoming possible to do this. The company has developed specialized data entry/editing peripherals, color graphics function buttons, and advanced application software programs.

However, with a few exceptions, all personal combiators use CRT displays, whether specialized CRT displays or connected to standard television sets.

CRTs have good screen resolution, can display color, and can display even more characters on the screen.

However, when using a CRT display device, the downward size of the delta compirator is limited, and most CRT IIi are very large, so the size of the combiator and display device is limited. - This prevents tupleization. Some manufacturers offer displays with liquid crystal display (f, CD) devices. LCDs are much smaller than CRTs, and therefore contribute to the I-tuple nature of the internal computer.

[Problems with background technology]

However, there are several drawbacks to using LCD displays. First, the number of characters that can be displayed on an LCD screen is very small compared to a CRT display. Also, LCD
Whereas character cells in devices are generally square,
A character cell of a CRT is a square or a rectangle long in the width direction or height direction. Also, it cannot display color like LCD FiCRT. The differences in the operating characteristics of CRT and LCD devices pose important problems. For example, if a computer with a CRT is connected to an LCD
Even if the Δ-sonal computer with the LCD is configured identically to the two, i.e. the same cpv, the same operating system and the same peripherals, the nine-mother computer with LCD - Even if the program uses a display device, CRTt- has Δ
-Sonarcon ♂ - Written for Ta! - Cannot run gram, this is a serious problem. Because.

App cage knot wear! This is because the log system must be modified or a program must be created for a comviator with a separate LCD device. Therefore, a combination with LCD and CRT 1! - Since there is no compatibility between LCD's and other computers, it is disadvantageous in terms of market strategy for manufacturers of LCD's.

Therefore, until now, there has been no portable combiator that is small and easy to operate and has an LCD that can be used without changing the application program written for the combiator with a CRT. .

[Purpose of the invention]

The object of the invention is to provide an 11-tuple processor that is compact and easy to operate.

Another object of the invention is to provide a compact display device for a portable combinator.

Another object of the invention is to have a liquid crystal display device compatible with a software program made for comviators having a CRT 7'? /- to provide a method for tuple combinations.

Another object of this invention is to provide an I-tag combinator having a liquid crystal display that displays the same number of characters as a standard CRT display.

Another object of the invention is to provide a control device ft for controlling data display on a segmented screen of a liquid crystal display device.
The goal is to provide the following.

[Summary of the invention]

In this invention, a first control circuit transfers display data from a screen image RAM to a multi-digit liquid crystal display such that the display data is simultaneously transferred to each segment of the display. The second control circuit FiASCII food data is converted into screen image data using the font pattern RAM t-. This system operates under the control of a software program written for CRT.
It is possible to emulate the color display.

[Embodiments of the invention]

The first (a) FIA is a perspective view of a converter using the present invention. This converter has a main body part 11 and a display part 13. This display section 13 is hingedly attached to the main body section 11, and displays a closed state, that is, a folded state. Portability is being achieved by downsizing the combination display and display device.

The ambiator is the first with the display 13 in the operating position.
(b) As shown in the figure. The CD device 15 is included within the display section 13. This LCD device 15 is a general CR
Although it displays the same number of characters as T, for example 25 lines, it is much smaller than the conventional CRT display device.

A key door 11 is provided on the lower front side of the LCD display device 15. When this display section 13 is closed, it becomes a protective cover that covers the key M-code 17.

FIG. 1(c) is a side view of the nine computer with the display 13 in the operating position. The support member 19 is attached to the main body 1 so that the key M-door 17 is positioned for optimum operation.
I support No. Two 7w discs 2fil
are located within the main body 11 and provide compatible storage capabilities for the converter.

FIG. 2(a) is a block diagram showing a combinator system embodying the present invention. This computer system has a processor 201, which has a processor 2o.
1 is connected to the internal path 2Q3 for bidirectional transfer of r-channel and control signals. This processor 201 is, for example, a model 80088 microprocessor manufactured by Intel Corporation in the United States. This microprocessor has random access memory (RAM),! : Read-only memory (ROM), these memories are used during microprocessor operation, and MSDO8
and cp/M-66 operating system.

The periphery of the Combiator system includes a keypad and a disk storage subsystem, each of which is connected to a separate internal path. A suitable disk subsystem includes one or more small floppy disk drives 21 as shown in FIG. 1(c).

A liquid crystal display (LCD) 209 is a display control circuit 21
Connected to 1. This display control circuit 211 transfers data to be displayed and control signals to LCD j 09. Next, the LCD j 09 sends a status signal to the display control circuit 211 along with a signal for identifying the display 7t-mat.

The display control circuit 211 is connected to the internal path 203, and the 6-display memory 213 in which bidirectional signal exchange is performed is also connected to the internal path 203 and the display control circuit 211. As will be clear from the description below, data displayed on the LCD 209 can be stored in and read from the display memory 213 by the display control circuit 21.

fvx set 201 can also transfer data directly to display memory 213 via internal path 203.

2(b) shows the display control circuit 211 and the display device 2.
13 is a more detailed block diagram of FIG. As embodied here, the display control circuit 211 has a first LCD control circuit 219.This first LCD control circuit 2
19 displays display data from the display memory 213 on the LCD 2
Transfer to os. The status signal generated by the LCD 209 is transmitted from L 209 to the first LCD control circuit 2.
Transferred to 19.

The second LCD control circuit 217 is connected between the internal path 203 and the display memory 213, and the second LCD control circuit 217 is connected between the internal path 203 and the display memory 213.
K Controls the storage of ASCII code display data and the conversion of M8 CII code display data into screen image data suitable for display on the CD 209.

The display memory 213 is divided into three sections.
Consists of M. That is, the ASCII code RAM 221 that stores the data displayed on the CD, and the AS
CII=r l' Also stored in RAM 221.

Screen image RAM that stores all or part of the data to be displayed in a 7-mat format suitable for display on the LCD J09! 21, and a 7t pattern RAM that stores conversion data used when converting ASCII:f-code data to screen image data.
It is J25.

As will be described later, the second LCD control circuit 217 has many internal registers, and these registers can be accessed by the processor 201.
used to define and control One of these registers is an index register (not shown) that is used as a pointer to a memory location that stores the location keys of other registers. This index register is a register loaded by processor 201 by executing the otrr instruction. The 1 index register is first loaded with the appropriate register address to load the other registers, the data register (not shown) is loaded with the information to be stored in the selected control register, and the OUT The instruction is processor 2
Executed by 01.

The table below shows the control registers and the values stored in these control registers for implementing and controlling the different modes of operation of LCD 209.

Register νW Description RO* RI W Horizontal display (character) R2* R3* R4* R5* R6W Vertical display (character) R7* R8* R1211L/W Start address (upper) R1
3R/W Start address (lower) R14R/W
Cursor address (upper) R15FVW Cursor address (lower) R16ゝR17* H2o W 4M interval select R21W Underline position (scan line) R22W Select 7 R23W Background (BG) force 2-table R26W Video RAM address mask R27W
Test mode R28W Test status l R29W Test status 2 R30W Data loopback (higher order) R31W
Data loopback (low order) * in the above table indicates that it is currently not used.

The functions and meanings of the signal values stored in the control register will now be explained.

R1 = horizontal display range is stored from 2 to 0FFH* and the ratio value is the actual screen size (40° in low resolution mode and 80 in high resolution mode)
If does not match, error.

R6: Vertical display Bits 7-0: Total number of characters displayed vertically.

The range is 2 to 0FFH, and if the stored ± value does not match the appropriate screen size (25 lines), the operation 2-・R9: Maximum scan line address bits 7-4: Ignore j'
Bits 3-0: Store a value corresponding to the number of lines that is smaller than the number of scan lines for one character.

Range is O to OFH6 RIO: Cursor start scan line pit 6-5
= Controls enabling or disabling of the display cursor.

Bit Bit Q Cursor display foot 0 1 No cursor display 1 0
Cursor display foot 1 1
No cursor display bit 4: Ignore bit 3-O: Cursor start scan line.

The range is 0 to OFF'H.

When the stored value is larger than bits 3-0 of R9 (character scan line size), this cursor will not be displayed.

R11: Cursor end scan line (with iF only) Bits 7-4 = not ignored.

Bits 3-0: The end scan address of the cursor.

Range is 0 to 0FFH.

When the stored 9-value is smaller than bits 3-0 of RIO (cursor start scan address), the cursor cannot be displayed - R12: Character/image buffer start address is upper (read/write) bits 7-6: When writing , is ignored and returns to zero on read.

Bit 5-O: Upper 6 pits of the matching start address of the character/image buffer.

R13: The start address of the character/image buffer is the lower (read/write) bits 7-0: The lower 8 pits of the relative start address of the character/image buffer. Since the relative 2-tard address of the character/image buffer register is 14 bits wide, a 16-byte character/image buffer area can be accessed.

R14: Upper cursor address (read/write) Bits 7-6: Ignored when writing, returns to zero when reading.

Bits 5-6: Upper 6 bits of the relative address of the cursor.

R15: Cursor address lower (read/write) Bit 7-O: The lower 8 pits of the relative address of the cursor.

The relative address of the cursor register is 14 pits wide. Therefore, a 16 byte character/image buffer area is accessible. When this cursor address is off-screen, the cursor will not be displayed.

R18: Operation mode (write mode) bit 7
: Controls recognition of character attributes in character code. When it is 0, black and white modes are selected. When 1, the color mode is selected.

Bit 6: Enable or fully control the color/image buffer scan function.

When set to 0, the scan function is disabled; when set to 1, the scan function is enabled. When the main processor is changing the mode register of the second LCD controller, the scan function becomes display
Destruction of data stored in the screen image RAM 2 J J, ie, the video buffer, is prohibited.

ゞyl'5m,
(When this bit is O, the maximum scan line address of R9 is programmable.

When this bit is 1, the maximum scan line address is not programmable and is set to 7 (RID "OUT" instructions are ignored).

This bit is set when monochrome display mode is selected.

Bits 4-3: Ignored.

Bits 2-0: Code/image buffer scan address mask bits. The code/image buffer address is the AN of this mask value and the scan address register (14 pits).
Dt - equal to the value taken.

This feature allows changing the code/image buffer address structure.

R19 Niscan interval select bit 7-4:
It will be ignored.

Bits 3-0: If the time waiting between each plane of the display section 209 is 0, the first
LCD controller 219 does not wait between scans of each plane.

R20: T'Fnv interval select bit 7: Selects the basic clock for pixel blinking. When it is 0, the character plink timing is the 2nd L■control y;t
1y scan frame clock (not shown). When l, the character plink timing is synchronized to the character/image buffer scan clock.

Bits 6-4: Ignored.

Bits 3-2: Control fast plink cycles. The plink cycle is defined as follows.

Bit 3 Bit 2 Divisor bits 1-0 = Control slow plink cycles. The plink cycle is defined as follows.

Bit 1 Bit O Approximate number 0 1 1 V64 R21: Angline position and overscan writing prevention Bit 7: Ignored.

Bits 6-4 = Image memory scan limit address - This function changes the mode register in the screen image tone 209 to prevent overwriting.

Bit 3: Underlined rask address. The range is 0 to 0FH0. If the stored value is greater than the maximum current line address of R9, the underline disappears.

R22: Font selection Bits 7-4= 7 is the address of pattern RAM 225.

This bit string is used for addresses bits 12-15 of the font RAM 225.

Bit 3: Selects highlight mode function. The stored value is 00
Then, bit 11 of the ninth address of font addressing is pit 1 of R22 (see below).

When the stored value is 1, bit 11 of the bright addressing address is the character attribute 1 (brightness).

Bit 2: Selects highlight function. When the stored value is O, the high speed plink becomes disneedel.
, 11 is stored and the psychic value is 1,
High-speed printer is enabled.

Bit 1: When bit 3 of R22 is 0, bit 11 of the address for index addressing is set to the same value.

When bit 3 of R22 is 1, it is ignored.

Bit O: When the value of the scan line 123 is less than or equal to 7, 7 is used as bit 10 of the address for client addressing.

R23: Background Color Table Bit 7-O: When Power 2-mode is selected (when bit 7 of R18 is 1), the background color part of the character attribute is decoded by this bit array.

Background attribute Background color reference bit BG 0 0 0 Bit 0 001 Bit 1 010 Bit 2 0 1 1 Bit 3 100 Bit 4 101 Bit 5 110 Bit 6 111 Hi;t 7 Note: Reference bit = O White background = 1 Black Background (reverse video) R24: Image buffer start address upper (write) Bit 7: Ignored.

Bit 6-0 The most significant bit of the image buffer's start address.

R25: Lower start address of image buffer (write) Bit 7-0 Lowermost bit of start address of image buffer R26: Display memory 213 address mask (write) Bit 7: Enable or disable read/write access to display memory 213 Disable.

Bit 6: Ignored.

Bit 55-3 = Bit 15-1 of the display memory address supplied from the processor 201 to the display memory by RA select ◆1
3 is masked by this bit array.

Bit 2-O: Bit 15-1 of the display memory address supplied from the processor 201 to the display memory by the RAM selector 2
3 is massed by this pit array. As a result,
Memory address configuration increases.

R27: Test mode (write) Bit 7: Displays test mode. When the stored value is 00, normal mode is selected. When the stored ratio value is 1, the test mode is selected. When in test mode, memory addressing is enabled only by the suffix 1 on scan control, and memory addressing from other suffixes is ignored.

Bits 6-3: Ignored.

Bit 2: Controls the video RAM read cycle time. When O, the read memory cycle time is 4 machine clock cycles.

Bit O: Controls the write cycle time of display memory 213.

When 1, the write memory cycle time is 5 machine clock cycles. When 1, the write memory cycle time is 4 machine clock cycles.

R28: Test Status 1 (Read) Bit 7-O: Test pit is used for diagnostic purposes ((
It will be done.

R29: Test status 2 (read) bits 7-0: These bits are used for diagnosis. R30: Data route back upper (read) bits 7-0: These bits are used for diagnosis.

R31 Near'-Tarou! Back lower (lead) pict 7
-O= These bits are used for diagnostics.

Mode Control Register This is a 6-pit register with I10 address 308H. This register is stored in the display control circuit 21 as shown below.
Controls the status of 1.

Bits 7-6: Ignored.

Bit 5: When the stored value is 1, this bit turns the character background brightness into a plink attribute function for alpha-animetic mode.

If no superior attribute pit is selected, 16 background colors (
or brightness color) are available. In normal operation, this bit is set to 1! Enable link functionality.

Ct4: When the stored value is 1, high resolution mode (640X200) is selected for black and white graphics mode.

One of eight colors can be selected with the Direct Drive Set in this mode using the mono mode register or the bald 2-fix mode register (for engineering).
can.

Bit 3: 1 when stored and ratio value is 1. Video signal is enabled upon mode change.

Pit 2: When the stored ratio value is 00, the color mode is selected.

When the stored value is 1, black and white mode is selected.

Bit 1: When the stored value is 0, 320X200 graphics are selected. When the stored value is 1, Alphaniemeric mode is selected.

Bit 0: When the stored value is O, the 40 character x 25 line alpha animatic mode (low resolution) is selected. When the stored value is 1, 8o characters x 252
The alphanumeric spider 1' ([resolution)] is selected.

The list below is a list of modes that can be selected for this register.

Bit 543210 Selected function 10
1 100 40X25 black and white alpha 2-Merrick 10 1000 40X25 color alpha 2-
10 1 101 80X25 black and white alpha 2-Merrick 100001 80X25 color alpha 250001 80X25 color alpha 320X200 black graph 4yri X O
1010320X20o ColorIf"7Fy/(EMIERESHIN)
A schematic diagram of D 209. In the preferred embodiment, LCD 2
09 has a resolution of 640 pixels horizontally and 2 pixels vertically.
It has a resolution of 56 pixels. LCD 209 is 25
It has a display capacity of 80 rows x 80 characters. This is C
This is a common configuration for RT displays.

Pixels 301 are grouped into each character cell 301, which in the preferred embodiment is 3018(@)XlO
It has a pixel array of (height). A typical character cell for an LCD device is a square pixel array, such as 8x8 7-ray, as shown in cell 3o5. Using character cells that are larger in height than width increases the reliability of the LCD device. The preferred embodiment therefore includes square cells. However, as will be explained below, the size of the character cell is a glogrammaple to provide flexibility in the A7" cage design. In the preferred embodiment, the intercharacter and interline spacings are each one pixel. .

In the preferred embodiment, display memory 213 has a capacity of 48 bytes and 16 bytes of ASCII code RAM 2J1.
24 bytes are allocated to the screen image RAM 223, and 8 bytes are allocated to the human pattern RAM 225. Display control circuit 211 has four main control modes. In other words, black and white character mode.

Character mode of color georage seal.

This is a graphical and direct pit map mode for the second generation model.

In either control mode, read or write operations of display data by the processor 201 are performed via the cD controller 217 f12r.

When the character display mode is selected, the second LCD controller 217 displays the ASCII
Scans the code RAM and converts the ASCII code character data according to the correlated attribute pits into the font data t-
Convert to screen image data using The converted display data is stored in the screen image driver 323. If graphic mode is selected, the second L
CD controller 211 is ASC'II code RAM
The ASCII code and 7-fick data stored in the screen image RAM 221 are converted into appropriate pixel image data and written into the screen image RAM 223.

glLcD controller 219 uses screen image R
The next pixel image data stored in the AM 223 is scanned, and the image data is transferred to the IC LCD 209 for display according to the LCD scan timing. Fnant pattern RAM 22B is accessible to processor 201 during idle time.

! The processor 201 sends the ASCII code display data to the second LCD fund 2217 in the form of two bytes, a (or data) byte and an attribute byte. In direct pit map mode, processor 201 sends display data directly to screen image RAM 2231c.

1) when any false shift control mode except direct bitmap mode is selected! and the mode register indicates monochrome mode, the second LCD controller 217 accesses the Fnandt pattern RAM 225 to convert the ASCII code data to pixel data and performs a logic operation according to the value of the attribute byte. When the mode register is set to 2 - 1, the operations performed are almost the same as for black and white, except that the color register is used to convert data that correlates to color attributes into a black and white pattern of selected pixels. The process of accessing table registers and attribute items is different. If a color sheet is selected, the ASCII
The data stored in the code RAM 221 is transferred to the appropriate memory in the screen image RAM 22J without accessing the basic pattern 7 RAM 2j5f.

Reverse video character is screen image RAM
2231c, the second LCD controller 217 changes the background color to black and makes the characters white.

When a character that has an attribute that instructs a link is stored in the screen image RAM 223, the second L controller 217 displays character data with all white character cells in the designated area of the display device 209, and some characters When displaying in reverse video, the character data of all black character cells are displayed alternately.

The second LCD controller 217 displays highlighted characters and half-gradation images. In the case of emphasized characters, the second
LCD: The ff controller 217 displays the second font data group stored in the font pattern RAM 2J5, such as ♂- (bold font) 1, ASCII
While converting code data to screen image data,
to access. Half-gradation is performed by changing the display of the selected character to all white pixels and visually providing a half-gradation image.
In the one-character display mode, the character data has two characters: a character code byte and an attribute byte.

Next, the definition of 2 bytes during operation in monochrome control mode is shown.

BLRGBIRGB Character Code Background (Background) (Foreground) Character Attribute BL: Character cells and all white pixel cells defined by background, for example, are alternately displayed and the attribute is blinked.

(2)=With this brightness, characters are displayed that are emphasized by selecting alternating characters or characters that are dimmed by blinking at a rate higher than the response time of the LCD 209.

The attributes of packground and frameground are coded as follows.

Pac Ground 7t-Ground RGB
RGB ooo ooo No display, filled with white pixels 0
00 001 Underline Goo 111 Black text/White background 111 000 White text/Black background 1
11 111 No display, filled with black pixels Next, the definition of 2-byte character data in the Karashi Island Milesin mode is shown. Since the LCD 209 naturally cannot display multiple colors, the color attributes have threshold values that can be used to display images in a specific black and white combination.

BLRGBIRGB character;-de packground character attribute BL: To alternate between a normal display character cell and a cell filled with specific data (e.g., all white pixels) defined by the packground. Flashing KM nature.

I: Highlight attributes to display characters either by selecting alternating characters or by blinking at a rate higher than the response time of LCD 209.

Pack ground: Access the color table register using the color attributes of the 3 pits as pit addresses.

RGB color table register pit address ooo.

If the accessed bit of the Zoo 4 color table register is O, this character cell is displayed as black text on a white background. Conversely, if it is 1, 0 is displayed as white text on a black background.
The correspondence between color characteristics and cell display combinations is programmable (by loading the appropriate values into the color table register). 7 oh ground bit has no meaning. 7 stored in turn RAM 2 j 5
Zuntoters are always treated as cells, and the display cell size is programmable. However, the width of the 7 pixels is fixed at 8 pixels, but using hardware with 8 pixel resolution,
The height of the 0 character cell, which can be extended to 66 pixels (low resolution mode), is programmable from 1 to 5 pixels.

A character cell is defined as the total space including the character body, intercharacter space, and interline space. 7zunto/4turn RAM j j 6
In this case, eight pixels i'' row in one cell are treated as one byte of display data, M2R of one byte display data displays the leftmost pixel on the screen, and IJB represents the rightmost pixel.

The 8 to 7 byte 7 st/-turn RAM 225 has 4 204 bytes corresponding to 256 character patterns of @88 pixels and 8 pixels high to realize multiple fund selection.
It can be managed as an 8-byte segment. 8
By using a character cell with a height greater than the pixel, it can be divided into two different characters and stored in two 4096 byte segments.

The actual byte address in hexadecimal for a particular row within a display cell is generated as follows.

Address-C6000H+(FS1*1000H)+(
P8G*800H)+(ROWZ*400H)+(RO
W1*200H)+(CDI2)+ROWOFSI:
7 High-order bit of the pattern RAM segment selection pit. If emphasis is enabled, this bit turns into a luminance pit.

FSO: Lower bit of Fundamental pattern RAM segment selection bit. If a character height larger than 8 pixels is selected, this bit changes.

R□-RO punishment: These 4 pits are in the character cell. Represents a special row. Character height is 8 strokes If the sum is equal to or equal to the sum, ROW3 has no meaning.

CD red herring? An 8-pit character code that allows the identification of 256 different characters, including letters.

In the graphics display mode, graphic data to be displayed is handled as bytes corresponding to eight pixels and is transferred directly to storage locations in bytes 16 of screen image RAM 225. Screen image R
The AM 225 is divided into two segments of 8 bytes, each segment corresponding to an odd row image memory and an even row image memory. Even row image memory is 80
By)
), and the image memory of odd rows is 80 bytes x 1oo rows (load 2 rows 2... rows 99
) image data is stored.

16 for a specific group of 8 horizontal pixels on the screen
A decimal byte address is generated as follows.

7 do v, ;<-MOD(ROW/2)*BAOOOH+
MOD((ROW+1)/2)*B8000+INT
(ROW/2)*50H+COLMOD: IMT representing the modifier function: ROW representing the integer function Vertical logarithm count of the row on the screen with the topmost property on the screen as row 0 COL: Leftmost edge of 8 pixels 3(b) to 3(d) schematically show another feature of the present invention. LCD 209 is 1, 2. Or it can be composed of 4 segments or planes. When the LCD 209 is configured with a single plane, the data is displayed on the LCD 209 as characters ≧
Each input is transferred and one = pts is transferred. However, if the %LCD x o y is divided into multiple planes, there will be as many characters as the number of planes in the screen image? It can be transferred from RAM 223 to LCD 209 in parallel.

As shown in Figure 3(b), a single plane LCD is
lines (eg 25), each line having N words (eg 80). Each word corresponds to one character displayed. Assuming that one character to be displayed is stored at a memory address in the screen image RAM J j J, A+N-1 is the address of the last character in the first line, and j5, A+( L-1
)N is the address of the first character of the last line, and the last character of the last line is stored in address +LN-1. Therefore, the value is the line number (64), and the value N is a 2-in value, meaning the position of the character within the line.

FIG. 3(c) shows an embodiment in which the LCD 20G is divided into planes and planes B. FIG. Line 1-L is included in plane A, and line L+1-2L is included in plane B. Data word l of line l is stored at plane offset address A, eg t0, and data word 1 of line L+1 is stored at plane offset address B, eg B=A+LN.

The third (Xu figure) shows an embodiment in which the LCD 209 consists of four planes, namely plane A, plane B, plane C and plane D. In this embodiment, the maximum line off cell) N is the third (b) It becomes the value A in the case of the embodiment shown in the figure and FIG. 3(C).

Plane A, Plane B, Plane C Oyohi Plane D
The address of the first data word of the first line of is A # n = (L +1 ) 2 N tC = N, respectively.
, D=(L+1)2N+N.

FIG. 3(e) shows the address of the screen image RAM 223 and the LCD in an embodiment in which the LCD 209 has two planes, plane A and plane B.
209 address correspondence, plain offset address person is screen image RAM I J
Assuming that the addresses in J are equal, the words are from the screen image RAM
i sent to plain person in j 09. ! In lane B, the data words stored at addresses I, N-2NL-IK are displayed.

If the LCD 209 is composed of four planes,! The plane offset addresses of lanes A, II, C and D are O and N, respectively.

(L+1)N- and (L+1)N+N.

Figure 4 shows that the display data is stored in the screen image RAM s.
x sp~3 1st LC transferred to LCD 209
3 is a block diagram of a D controller 219. FIG.

This block diagram shows the circuitry that generates display locations on LCD 209 for displaying data and transferring display data from screen image RAM 223 to LCD 209.

For example, at the start of the computer system, the processor 20
At the time of I4 war add of 1, the control value of a certain food is registered in register 40.
3 through 411. This control value relates to the number of planes within LCD 209 and the number of words within each plane. For example, Figure 4 shows the LCD
209 is an embodiment of the first LCD controller 219 having a plain display. Therefore rag person 403
stores the plane offset person mentioned above. This person's value is O if the first storage word in screen image RAM 32j stores the character I, which appears in location O in row 0 of CD 209.

Similarly, rag B 405, r@g C 407 and r@g D 409 store the values of grain offset, top B, 7" lane offset C and plain offset) D, respectively. These values are , L when displaying the first character of plane B and plane D
This corresponds to location 7 on CD 209.

A value equal to the number of characters in each line of the plane is loaded into ragΣ411. Assuming that LCD 209 displays 80 characters per line, for the embodiment of LCD 209 shown in Figures 3(b) and g3(c), rag E 41
The value stored in 1K is 80, and in the case of FIG. 3(d), the value stored in rsg'Fa 411 is 4G.

The outputs of registers 403 to 409 are sent to multiplexer 41
3 input. Signals PLNS'HLo and PL,N5EIJ control multiplexer 413 to selectively output the 1 values stored in registers 403-409 to one input of adder 415. The value output to multiplexer 413 constitutes a 16-bit base offset address for one of the planes.

The output of adder 415 constitutes a 16-bit address of a character position on LCD 209 for one of the planes. The first value output by the adder 415 for each grain A to LC in each grain A to
D 209 and is equal to the offset value stored in registers 403-409.

For each other character on a line, the pace offset value must be incremented. This increment is performed by adder 417. Register 419 and counter 421
This is done by

The value stored in rag '1rI 411 is added to adder 417
is supplied to one input of the . The other input of adder 417 receives the output of register 419, LINSAO-25. The output of the register 419 is also a line load signal L.
The counter 421 is loaded under the control of INELD. Register 419 stores the output of adder 417 and loads its value under control of line end signal LINEEND. In this embodiment, the values stored in the various registers and adders are represented in two's complement. First, the values of register 419 and counter 421 are set to zero. The value of the counter 421 is the data ready signal DATARD
It is incremented by 1 by Y. DATAARDY below
We will discuss the occurrence of

Initially, the twin word register 423 is loaded with a value equal to the number of bars displayed in each plane line. Therefore, in the embodiments of FIGS. 3(b) and 3(c),
Assuming that the LCD 209 displays 80 characters per line,
The stored value will be 40. In the embodiment of FIG. 3(d),
Each row has two planes, so the value stored in line word register 423 is equal to 20. This stored value is determined considering that two 8-bit words or characters are transferred from screen image RAM 223 as signal VRAMDO-Js at a time.

The two's complement of the value stored in line word register 423 is loaded into timing counter 425 upon the occurrence of LINELD, which is generated when counter 425 overflows. The timing counter 425 is DATA
OR? that receives the RDY signal and the local clock signal LOCLK as inputs. - is incremented by controlling the output of 429. The value stored in the timing counter is transferred from the screen image RAM 223 to the LCD 20.
This corresponds to the number of 2-word data transferred to 9.

Line number register 429 is initially loaded with the number of lines to be displayed within the plane. In the embodiment of FIG. 3(b), this number is equal to the maximum number of lines that can be displayed on LCD 209. In the embodiment of FIGS. 3(c) and 3(d), the value stored in register 429 is
This is the maximum number of lines W that can be displayed on the LCD 209.

This is because the LCD 209 is vertically divided into two planes. The value stored in register 429 is expressed as a two's complement number, and is incremented when all data in the display line of LCD 209 is transferred. When an overflow occurs, the timing counter 431 is reloaded with the ratio value stored in the line number register.

As will be apparent to those skilled in the art, the display parameters, ie, the number of lines on the LCD 209 and the number of characters on the 12-inch screen, can be programmed. This allows for flexibility in the computer, and as a result, flexibility in the ESO.

Screen image RAM J 23 to LCD 20
In the actual transfer of display data to 9, register 441゜4
43.445 and 447 are used. Each of these registers is correlated to a different plane of LCD J09. Therefore, if the displayed data is for a plain person, register λ441. For plane B, register a
In the case of 44s and f lane C, the register C445 and in the case of plane (D) are stored in the register D442.

In the embodiment of FIG. 3(C), there are only two planes of the LCD.
209, register A441 and register B443 are required. Similarly, in the single plane embodiment of FIG. 3(b), only register A 441 is utilized.

All four data transfer paths shown in the fourth diagram are the same,
Since they operate in parallel, only one data transfer path will be described in detail.

2 words y' from screen image RAM 223
-I VRAMDO-1s is loaded into register 441 and parallel to serial converter 448 by signal PLANASTB.
Shift input is performed for . By shifting the data from register A441 to parallel/serial converter 448, signal DATA
RDY is generated and applied to the input of AND gate 430.

Parallel-to-serial converter 448 is comprised of shift register 449A and multiplexer 451.

The 16 bit data ADO-25 input to the 449 shift registers is the selection signal NBLSEL□ and NBLS.
4 bits by EIJ, i.e. NAO□-3°NA
O4-7, NAO&-1f, and NAO12-1
Output as 5.

The output of multiplexer 451 is data PLANAD.
Supplied to LCD 209 Gray 7 as O-3,
Furthermore, a buffer 7453Vc is supplied.

As is clear from FIG. 4, registers 443, 445 and 447 receive ready signals DATARDYB and
, DA'rARDYC and J) A'rARDYD, these signals are further connected to the piece gate 43011C.
After the input and resulting display data shifted from each of registers 441-447 is shifted, a single signal DATARDY2>E is generated that can increment timing counter 425.

LCD 209 (7) When there is one or two planes, an appropriate value is applied to the Φ dart 4300 Å force.

During operation, the initial values corresponding to the embodiment of the LCD 209 are:
As mentioned above, registers 403, 405, 407/, 40
9,411.423 and 429. This value includes not only the number of planes included in the LCD 209 but also 1
This is reflected in the number of characters in a line and the number of lines on the LCD 20G. Adder 415 outputs display addresses in each plane of LCD 209, and multiplexer 451 A-4
5JD displays screen image data on LCD j 09
Transfer to.

Assuming that the LCD 209 is composed of four planes, as shown in FIG. 3(d), the data word is
two multiplexers 451A, 451B.

451C and 451D to LCD 209K. Two data words, or 16 bits, are shifted from registers 441, 443, 445 and 447 to register 4491.449B.

When transferred to 449C and 449D, the signal DATA
RDY goes high and increments timing cucunters 425 and 421.

When 20 2-word data transfers are made to each shift register, timing counters 421 and 425
causes an overflow.

As a result, signals I, INEI, and D are generated, and the counter 4
25 is reset to the value stored in the line word register 423, the timing counter 431: is incremented, the counter 421 is set to the value stored in the register 419, and the current output value of the adder 412 is loaded into the register 419. .

As a result, counter 421 outputs an incrementing address that is added to the plane base address stored in registers 40'3-409 to generate the screen address for the second row of each display plane. The data word displayed on the second line of each plane is then transferred to the screen location output by adder 415. Once the second line of data for each plane of LCD 209 is displayed, the third and subsequent lines are displayed. When the last fin of each plane is displayed,
The timing counter 431 is reset to the value stored in the overflow and line number register 429.
1' The result register 419 is reset to zero.

The data in the screen image RAM 223 is transferred to the LC again.
D 209 to refresh the display gray and change the displayed data to reflect the changes in the data stored in the screen image RAM 2;t3.

FIG. 5 shows details of the second LCD controller 211.
This is a diagram. The second LCD controller 217 includes the above-mentioned status register and control register, and the CPU
Address and data transfer path for 201 and ASCII
I code RAM 22 J and screen image 7 R
AM 223, a 7-ont/4-bit RAM 225, and circuitry for modifying data according to correlated attributes.

Status and control section 501 register R1
, R6, It9-R15, and Big-R21. The functions of these registers have been described above.

This embodiment will be described below.

The 8-bit data bus from CPU j 01 is signal DB.
Supply O-7. 3 RAM-2 in memory 213
The data bus for 21, 223 and 225 is connected to the signal M
Displayed by BO-15.

CPtr 201, memory 213. and 2nd LC
The memory path shared by D controller 217 is indicated by signalman Q-15.

When initialized, select register logic 5
DBO-03 is controlled by the five bits of address signal AO-7 and loads initial values for status and control values from CPU data bus DBO-7 into the appropriate control and status registers. After initialization, if the value of any of the status and control registers needs to be changed, select register processor 503 is enabled to reload the appropriate register or registers.

Data provided by CPU 201 can be transferred directly to memory 213 via two write data latches 503 and 505. The data register and chip transfer the two 8-bit data transferred from the CPU in parallel onto the 16-bit memory path as memory data save MBO-15.

Similarly, the 16-bit data words transferred from memory 213, MEMI O-15, are output to CPU 201 as two 8-bit data words CPUDI O-7 through a pair of linear data latches 507 and 509. obtain. The memory data Xl0-15 is further input to the upper 8 bits, the ASCII code latch 511 which inputs the M1B-f5, and the lower 81:'y) MEM
IO-7 may be provided to input ASCII attribute latch 513. ASCII-), 511°513 is ASC
Used to input data from II code RAM 221.

The contents of the ASCII cord register 511 are transferred to the memory path as the lower 8 bits of the address of the font pattern RAM 225, bits A0-7. The upper eight bits are provided by seven font select logic 515 which receives input from font select register E22. 16 pins, address is font turn RAM 2 which stores screen image data corresponding to ASCII code data.
25 is used to access specific memory data words within 25. The actual pit representation of the ASCII code data is used as part of the address in the 7-ont pattern RAM 225.

The 2-word data returned from the 7-on-4 tandem RAM 225 is latched into the font data latches 517 and 519. The lower 8 bits are input to attribute processing circuit 521 and latch 519 which provides the lower 8 bit word AO-7 to the memory path. The font data line 517 supplies the upper 8 pits to the attribute processing circuit 521 and the memory path as the upper 8 pit words 1B-15. The data bits directly transferred from the 7 ont data 2d 517 and 519 are transferred to the screen image RAM 22 j Vc by a meso path.

The attribute processing circuit 521 receives 8 pits of data at a time from the data latches 517 and 519, and modifies the data using the association attribute control circuit 523. The modified version outputs dfP Niller Mode 7 Ontorer 2 and 5
25.527 or build (emphasis) mode data latches 529 and 531 to the memory path.

? - In low resolution mode, each displayed character is twice the size of the character cell.

The addresses in screen image RAM 223 for storing screen image data are generated by counter 541, which receives image start address ISA O-15 from image start address registers R24, R25-1)h. An adder circuit 543 adds the offset value to the output of the counter 541. This offset is generated by adder 545 and stored in latch 547 connected to adder 545. The output of the adder 543 is a 16-pit image plane address IMPAO-1.
5 and is supplied to the memory path. A pair of data latches 549 and 551 are provided to transfer the data from the memory path to the CPU 20 as the data pack LBD O-J5.
Transfer the image plane address to 1. The next line address 2, channels 553 and 555, receives the address from the memory path and supplies it to the counter 541 via the adder 557 or to the CPU 201 as routine data.

FIG. 6 shows the second LCD controller 21 shown in FIG.
FIG. 7 is a logic diagram of the preferred embodiment of FIG. As shown in FIG. 6, the memory path includes a pair of 8-bit controllers, 01.603, which receive memory path signals AO-15 from CPU 201 and memory 213. This signal AO-7 is transferred to latch 665 and becomes the MEMB O-7 signal.

Bit AB-11 is transferred to Ciro 07.)
It becomes MEMB & -11. The upper four pins from latch 607, l) ME pins 12-15, are supplied by display memory address mask register 826.

8-bit data bus DO connected to CPU j Of
-.7 is input by the input character, Chiro 09, which outputs CPUDoo -07. The data is transferred to the CPU 201 via the output terminal 11.

The clock signal used within the g2LcD controller is generated by oscillator 613 and output by latch 615).

Select resostarono, ri 503 (Fig. 5) is f-z-
da621.623 and NAND)Ia-)625-
645. Inputs to decoders 617-623 include signals REGSEL O-REGSEL 4. This signal is CP output by latch 647.
U data bit CPU D 10- CPU D J
Consists of 4. Latches 621 and 623 output enable signals UR18WR-UR27WR that control writing to the corresponding status and control registers. Decoder 6
23 is a read enable signal UR28RD
- Output UR31RD.

NAND controllers 625-629 and 639-645 output I and CD control register write enable signals UR9WR-UR25WRt-, respectively.

NAND gates 631-637 are LCD control register read control signals UR12RD-UR1
Output 5RD.

FIG. 7 shows a circuit 701 for generating a CPU access request signal. This circuit is the second LCD controller 22
Although it plays a certain role in the operation of No. 17, a detailed explanation thereof will be omitted as it is not necessary for understanding this invention.

Furthermore, FIG. 7 shows CPU data CPUD00 as input.
-Receive Or and each memory path MIMB g -1
An example of a write data latch 503,505 outputting to s and MEMB O-7 is shown.

Similarly, MEMB 8-15 and MKMB as input
Read data latch 5 receives CPUDI O-7 and outputs CPUDI O-7, which is transferred to CPU 201 as an output.
07,509 is shown.

FIGS. 8-10 illustrate embodiments of the status and control registers described above. Mode: The control register outputs the link enable signal (BLK]ila) and video enable signal (VIDKNB) according to the CPU data CPUDoo-or.

Selectively outputs graphic mode signal (GRAPiIC) and high resolution signal (HIRES) =・
The trigger is realized by the trigger f801.

Horizontal display register R1 and vertical display register R6 are similarly implemented with edge triggered flip-flops 803.805 receiving CPU D00-07.

Character/image buffer start address (upper)
The register n12 that stores the input signal CPU D 00
Edge trigger flip-flop 807 receives input signal CPUDIO-07 and trunk cooperation 8 receives input signal CPUDIO-7.
This is realized by 09.

The data to be written to register R12 is provided by flip-flop 807, and similarly the data in register R12 is transferred via transceiver 809.

Character/image buffer start address (lower)
The register R13 storing the data is realized by an edge trigger flip-flop f811 and a transceiver 813. Data written to register R13 is provided via edge trigger flip-flop 811, and data read from register R13 is transferred via transceiver 813.

The cursor address (upper) register, which is the register R14, is supplied by the edge register 815. Trunk Cooper 817 transfers the value stored in register RI4 to CPo 201. Similarly, register RJ5, which stores the cursor address (lower), is connected to the
This is realized by 21.

Register R9, which stores the maximum scan line address, is implemented by an edge-triggered flip-flop 901. Register R10 that controls the cursor start scan line is implemented by an edge trigger flip-flop 903.

ANDI'-to 905 connected to flip-flop 903 via inverter 906 outputs cursor inhibit signal C3.
Generates RI■. The register R11 that controls the cursor end scan line is
This is realized using a 907IC. flip f70 tube 901
．． 903゜907 are all input CPU data CPU
Receive DOO-07.

The operation mode register R181, scan interval select register R19, and high link interval select register R20 are realized by edge trip flipflops fyo99911 and 913, respectively.

Underlined part and O, 4-scandelotecsi.

registers R21 and 7, select register R22 and background color register -R23 are respectively)'j! 7! j y def 0゜f9z
s, 91y and 919.

FIG. 10 shows the image pack realized by the Eno Trigger Furi, GoFex, GoFex 1001.1003.1005 and 1007, the front start address (upper) register R24, the image pack astart address (lower) register 8252, and the display memory mask register R26.
and test mode register 827t. Multiplexer 10o9 is free, f70. f1005 (receives D output), AMDI'-to 1011°1013.101
5 and generates 3 upper address mask pits. 1st test status register 'H, 28,
1 to 2 test status register TL29*5″-Tarude hack (upper) register R30, data loopback (lower) register R31 is transceiver 1017°1
019.1021 and 1o23, selective Kf
-CPUDI o -y Output.

11 and 12 show a second LCD controller (a-5217) containing timing signals for accessing memory 213.
Generates timing and control signals used within the system.

Furthermore, in Figure 11, LCD 209, CPTJ
A priority encoder 1101 is shown that includes a D tag 1103 that outputs signals LCD5EL, CPUIL, and 5CN8EL that control access to 201 and memory 213. Since the function of the timing circuit is not necessary for understanding the present invention, a detailed description thereof will be omitted.

The l/c13 diagram also shows circuitry for generating timing and control signals. S+Yancon) 0-ni'/
−)77-9” Z J O1 is A8CII = r −
)” Read RAM 221, font A! Turn RAM
225 and generate timing and control signals for writing screen image data to screen image RAM 223.

FIG. 14 shows an embodiment of the counter and controller (FIG. 5) connected to horizontal display renoster R1, vertical display register R6 and maximum scan line address register R9. The horizontal character counter 1401 corresponds to the contents of the register R1 and the second character generated by the first manual group MDISPO-7 and counters 1405 and 1407.
It has a controller 1403 with a human power group.

Counters 1405 and 1407 are incremented each time an ASCII code character is converted to a screen image character by the second LCD controller 217. The count value stored in counters 1405, 1407 is equal to the current value stored in register R1, and a twin-ended signal LINEND is generated by D7 rig 70fz4os.

Vertical 2-in counter 1411 is vertical display register R5
It has a comparator 1413 having a first power group 15PO-1 supplied by a counter 1415.141'l and a second power group supplied by a counter 1415.141'l. Counters 1415 to 1417 are incremented by the LINEEND signal and store the twin number stored in screen image RAM 223. Counter 1415°1
The line number stored in 417 is the vertical display register R6.
is equal to the current value of D-flip 70, D-flip 1419 generates an end-of-frame signal UFRAME.

Character line address counter 142 consists of a comparator 1423 having a first group receiving the contents of maximum scan line address register R9 and a second group receiving the value stored in counter 1425. counter 1423
f) The output is the maximality control signal MAXROW.

Figure 15 shows font data latches 517°519,
ASCII code latch 51 and attribute latch 513
An example is shown below. ASCII: The value of the attribute associated with the ff-1' word is output by the attribute latch, and the value of the attribute associated with the ff-1' word is output by the attribute latch,
BGRED ), Pac Ground Green (BGGR
N), Pack Ground Blue (BGBLU),
Brightness bit (IBIT), foreground red (
FGRED), Forground Green (F'G
GR1:N), and 7 Org 2 Kund Blue (FGB
LU) control signals.

Signals BGRED, BGGRN, and BGBLU are used as selection signals for power2-voltage generator multiplexer 151o. The input to the multi-prefner 15101C is:
This is an example of the Nogutsu ground table Renostar R23, consisting of edge, trif flip 7o, and g919 (D outputs.I, CD 209 cannot display red, green, and blue colors, so the color encoder multiplexer 15o1
selects whether to make the background on the display 209 brighter or darker depending on the values of BQRIDBGGRN and BGBLU.

FIG. 15 shows -)y7ta 1425 (D output ROWO-
3. Compare the count value of the cursor start scan line register R10 and the count value of the cursor end scan line register R11, respectively.
An example of a cursor timing circuit 15o3 with IR1505 and xsoy is shown. AND gate 1509
The inputs of are connected to the outputs of converter delta 1505.1507. ANDART 1509 (D output C3RPO
5 controls the display of the cursor on the LCD 209.

The monochrome mode attribute decoder 1511 outputs a no-display white control signal ND that displays all pixels of a character as white and a no-display point control signal ND that displays all pixels of a character as black.
Generate BLK. Decoder 1511 further generates an inverted video signal RVVID that displays all pixels of the correlated character cells with inverted values.
- The underline timing generator 1513 has a counter 1515, one input group of which receives the output value of the counter 1425, and the other input group of which receives the value stored in the underline position register R21. Counter 1513 and decoder 1511 (AND e connected to D output
-) 1517 generates the underline control signal LNUNDER.

FIG. 16 is an embodiment of the attribute circuit 521 shown in FIG. 1
Paired trunk cooperators 16o and 1603 receive two data words (16 pits) in parallel from font data lines 511 and 519 and convert them into two serial data words of 8 bits each. Each 8-bit data word is then processed in parallel according to the attribute bits to produce an 8-bit, 7-onto data word FWRD O-7. Since each bit is treated in the same way, only bit O will be described in detail.

Bit O requires two people o Rr -) J t; o so
Applied as one input. The output of the 0R''-to 1607 which receives the signals LNUNDER and NDBLK is input to the other input of the 0Rr''-to 1605.
UE), the output of the OR gate 1605 becomes 1, and the pixel of the display section 209 corresponding to bit O is displayed in black.

0Rf-to 1605 (D output is AND? -) 160
9 is applied to one input. ANDr 1609 performs several functions based on blinking control of pixels at selected locations on LCD 209. One such feature is half-gradation, which flashes very rapidly so that it appears as a gradation halfway between black and white. This function receives a high frequency dimming enable signal DI■■ and a high frequency dimming blinking click signal DIMBLK.
1 is realized. AN'Dr-to 1611 is Sui,
The pixel corresponding to pixel 17 is turned on and off at high speed. This switching is performed via the second human power of the piece gate.

Pixels can flash at a rate that is visually perceptible. This is AND Dart 1613 and NAXDI"-)
1615. Blinking of pixels is caused by a blinking pixel which is one input of the NAND gate 1615) BLBI
Controlled by T. NAND? The other input of the M-dart 1615 is the output of the M-dart 1613. AND gate 1613 blinking black.

A blinking frequency signal is output according to the signal CHARBLK.

ANDr-) 1609 (D output is 0Re-) 1617
is applied to one input of The output of the cursor blinking )y'-to xg19 is applied to the other input of the 0Rf-to 1617. If the cursor position has a pixel correlated to bit 0, then the pixel is connected to the cursor blinking clock signal C
It blinks at a rate determined by 3RBLK. The frequency of the cursor blinking clock signal C3RBLK is different from the frequency of the character blinking clock signal CHARBLK, for example, 2
It is desirable to double the amount. As a result, the two signals can be visually distinguished.

0Rr-to 1617 (7) output is N0Rf-to 1621
is fed to one input of The other input of NOR dart 1621 is the output of 0Rr-to which receives the color emulator signals BGDARK and RVVID. OI
I''-t 1613 changes the value of bit 0 to change the color display by selecting the background color, black or white.

FIG. 12 shows an embodiment of the circuits and latch circuits 525-531 that implement the high resolution mode of the LCD 209.

In high-resolution mode, each character is
It has twice as many character cells. This is done by generating data words having values that control four pairs of pixels, one pair of pixels being identical.

The output of the attribute processing circuit 521, that is, the 7-onto data signal FWRD O-7 is sent to the data latch circuit sxy, 52s.
(Figure 71117) and output as signals WHIR&-15 and MEMB 0-7, respectively, in high resolution mode. In normal resolution (low resolution) mode, the font data word's pitch () FWRD 4-7 is supplied to the latch circuit 529, and the font data word's pitch (OS) is supplied to the latch circuit 531. Databi, ) FWRD 7
Since it is supplied to inputs 6 and 7 of child circuit 529, MEMB 14 and MEMB 15 have equal values. Similarly, inputs 4 and 5 of latch circuit 529 are F
WRD is set to the value of 6, so the bit MEMB
12 and MGMB13 have equal values. Beep)
Similarly, each bit of FWRD O-5 is connected to a latch circuit 529.
and 531, ) copied to MEMB O-11. The selection of high resolution mode or low resolution mode is made by the attribute bit, ) HIRES. Graphic mode font data input FDO-15 is transferred to memory path 0-15 via child circuits 1701 and 1703.

FIG. 18 shows the ASCII code RAM 221 which enables access to the ASCII code words stored in the ASCII code RAM 221 and converts them into display image data by referring to font data.
The circuit that generates the address of is shown. ASCII code R
The AM start address is provided by registers RJ 2 , R13 as inputs to code buffer address counters 1801, 1803, 1805 and 1807. Counters 1801.1803.1805 and 18
The value stored in 07 is incremented and the ASCII
The addresses of the ASCII code words stored in the code RAM 221 are sequentially output.

The controllers 11109 and 1811 compare the output of the ASCII code buffer address with the current cursor address, and depending on the result, output signals CUR8OR and UCU.
Set R8OR. As mentioned above, the CUR8OR signal is used to control the blinking of selected pixels to determine the location of the cursor.

FIG. 19 shows the ASC by accessing the font data stored in the font data RAM 225.
A circuit is shown that uses an image data address generator to convert II code data and generate an address in display image RAM 223 to store the resulting image data. The next line address latch circuits 553 and 555 receive the memory address MEMB O-15 from the memory path, and convert the address to loopback data LBDσ-15 for testing.
The data is transferred to the latch circuits 549 and 551 as data. The output of the latch circuit is further incremented by circuits 1901-190.
7, and the value of the shelter 0-15 is incremented by +1.

The incremented address is the transceiver 1909
．． Supplied in 1911.

A pair of Tiger/Sheepa 1913, 1915 Hashi, Zosta R
24, receives the image start address from R25. The contents of the trunk coopers 1909 and 1911 or the contents of the transceivers 1913 and 1915 are stored in the counter 1917-1.
923. Counters 1917-1923 are incremented by 1 each time all pixels in a character cell are converted from ASCII code data to screen image data. Therefore counters 1917-1923
stores the address corresponding to the top row pixel in the character cell. Counters 1917-1923 are AS
When the last character of the last row of CII code RAM 221 is processed, it is set to the value stored in transceiver 1913.1915.

FIG. 20 shows the screen image RAM 2j corresponding to the beginning of one line of characters displayed on the LCD 209.
3 shows a circuit that generates addresses within 3.

Transceivers 2001.2003 store values corresponding to the number of characters in the display line of LCD 209 in high resolution and low resolution modes. This value is in register R
IK, it will be reset.

If high resolution mode is indicated by HIRES, the value stored in transceiver 2001 HD18P O-7
is transferred to the row offset latch circuit 2005. Low resolution mode is activated by signal WIRE8 (1m if indicated)
1SP 1- HDISP 7 or transceiver 2
A value equal to half the value of MDI8P O-7 stored in 003 is supplied to the latch circuit 2005 in row 003. The jar row offset Djibouti circuit is
an image offset signal IMO corresponding to N times the value originally received as input by adder 200712009;
It is composed of adders 2007-2011 that generate FFO-11 and latch circuits 2013-2017. The value N is equal to the line number currently stored in the screen image RAM 223.

Therefore, IMOFF" 0-11 is the value that always corresponds to the start of the line displayed on LCo 209.

Screen image RAM 2 that stores the execution address, that is, the screen image data currently being processed.
The physical address IMPA O-15 within 23 is the adder 20
19-2025.

Adders 2019-2025 convert the line address represented by signal IMOFFO-11 into character address IMPA.
Add to O-15.

FIG. 21 shows a circuit 2101 that uses a scan address control signal generator to generate a signal UCBREND to control whether addresses in ASCII code RAM 221 or screen image RAM 223 are being processed. shows.

The font selector circuit 2103 receives the memory address M output by the pair of transceivers 2105 and 2101.
KMB O-1! It is provided to generate a pit 10 and a corridor 1). In this manner, one of the two 7-ont data stored in the 7-ont data RAM 225 may be selectively accessed.

FIG. 22 includes a comparator 2203 having a first set of inputs receiving the signal 5CNIV O-7 stored in the scan interval register R19 and a second set of inputs receiving the outputs of a pair of counters 2205-2207. A b-scan interval selector circuit 2201 is shown. Signal U
CI (IST is scan of memory 213 and ASCII
Generated from the output of comparator 203 to initiate the conversion of code data to screen image data. The scan interval can be selected via the counter in register n19. It is also possible to save power by refreshing the memory at long intervals.

Clock divider circuit 2209 generates clock signals RATE O-7 having different frequencies. This allows the above-mentioned blinking control signal CTIARBLK to have a different frequency.
, C3RBLK and DIMBI,K enable the blink interval selector circuit 2211.

23 and 24 show the memory 213. and an embodiment of the same circuit for memory and input/output decoding. The dynamic aspects of the memory 213 and the various circuits shown in FIGS. 23 and 24 will be apparent to those skilled in the art from the description of the second LCD controller 217 provided herein. There is no need for a description.

[Brief explanation of drawings]

1(a) to 1(c) are diagrams of a portable computer using a display device and a display control circuit to which the present invention is applied; FIGS. 2(a) to 2(b) are diagrams of a portable computer according to the present invention. A block diagram of a computer and a display system to which this invention is applied; FIGS. 3(a) to 3(e) are diagrams schematically showing the relationship between a display device and a display memory in a system to which this invention is applied; Figure 4 is a detailed block diagram of a control circuit for transferring LCD Ic screen image data in a computer system to which this invention is applied; Figure 5 is a diagram showing a control circuit for converting ASCII code data to screen image data in a computer system to which this invention is applied. 6 to 24 are detailed circuit diagrams showing an embodiment of the control circuit shown in FIG. 5. 201... Processor, 203... Internal lotus, 20
9...LCD, 211...Display control circuit, 213.
...display memo'), 219...first LCD control circuit, 217...second LCD control circuit, 221...A
S, CII Co-)"RAM, 225-7O7)-2
#, -7RAM. !゛Applicant's Representative Patent Attorney Takehiko Suzue Commissioner of the Patent Office Michibu Uga 1. Indication of the case Japanese Patent Application No. 183155 No. 1988 2, Name of the invention Control system for liquid crystal display device 3, Person making the amendment Relationship to the case Patent Appearance Person Data General Coordination 4, Agent November 1988 June 26th, 6th, name of the representative of the appropriate application to be amended), power of attorney and its translation,
drawing

Claims (1)

Claims: 1. A display memory for addressably storing data displayed by a display device at correlated addresses; means for supplying addresses of the display memory and accessing the data according to the addresses; means for converting an address into a corresponding position signal of said display device; and transmitting said display position signal and correlated display data to said display device, so that said display data corresponds to a correlated display position signal. 1. A control system for a liquid crystal display device, comprising: means for displaying information at a display position. 2. The display device has a numbered sequence of display pixels arranged in a matrix of rows and columns for displaying the display data, and the converting means is arranged to display the display data, and the conversion means 2. The system of claim 1, further comprising an offset counter that generates a pixel offset value indicative of a display pixel in a sequence of display pixels. 3. Incremented in response to display data transfer,
generating a row overflow signal when the count value is equal to a maximum number of pixels in a row of the matrix; a pixel column counter that is reset in response to the row overflow signal; and a pixel column counter that is incremented in response to the generation of the row overflow signal; , further comprising a pixel row counter that generates a reset signal when the count value is equal to the maximum number of pixels in the row of the matrix, and is reset by the reset signal. system. 4. The offset counter includes: a pixel counter that is incremented in response to the transfer of display data to the display device; and an offset addition that is incremented by a value equal to the number of pixels in the row of the matrix in response to the row overflow signal. and a register for transferring the contents of the offset adder to a pixel counter in response to the row overflow signal, the pixel counter and offset adder being reset to zero in response to the reset signal. The system according to claim 3, characterized in that: 5. In a memory location with a correlated address,
storing display data displayed by the display device;
a display memory comprising a plurality of memory locations; providing addresses of memory locations of said memory;
means for accessing data to be displayed on each of said display segments in response to each provided address; means for converting said provided address to a corresponding display position within each segment of said display device; and Transferring in parallel accessed data and display position signals to be displayed on each segment of said display device, thereby providing a selected display of each segment of said display device in response to provision of a single address of said display memory. A control system for a liquid crystal display device having a plurality of display segments, characterized in that the control system comprises means for simultaneously displaying data at positions. 6. The display device has four display segments, the transfer means comprises four multiplexers, the output of each multiplexer is connected to a different display segment, and the input is connected to a display memory to receive the display data. 6. The system according to claim 5, wherein the system is connected to a computer. 7. The system of claim 6, wherein the memory locations of the display memory are divided into four memory segments, each memory segment being associated with a different multiplexer and display segment. 8. The display device has numbered columns of display pixels arranged in a matrix of rows and columns, each segment of the display device having a position of a starting display pixel within the numbered display pixels. a display pixel correlated to a segment offset indicated, wherein said converting means correlates each transfer of display data to indicate a display pixel in the sequence of display pixels in which said correlated and transferred display data is displayed; 8. The system according to claim 7, further comprising an offset counter that generates a pixel offset value. 9. a pixel counter which is incremented in response to each transfer of display data and which generates a row overflow signal when the count value is equal to the maximum number of pixels in a row of the matrix and which is reset by the row overflow signal; and said row; and a pixel row counter that generates a reset signal when the count value is equal to the maximum number of pixels in the row group of the matrix in response to the overflow signal, and is reset by the reset signal. The system according to scope item 8. 10. The offset counter includes: a pixel counter that is incremented in response to the transfer of display data to the display device; and an offset addition that is incremented by a value equal to the number of pixels in a row of the matrix in response to the row overflow signal. a register for transferring the contents of the offset adder to a pixel counter in response to the row overflow signal; and adding a segment offset correlated to the selected display segment with the contents of the pixel counter to transfer the contents of the offset adder to a pixel counter; a segment offset adder for generating a pixel position relative to display data transferred to a selected segment of the device, said pixel counter and said offset adder being reset to zero in response to said reset signal. The system according to claim 9, characterized in that: