JPH011027A - a video device that provides video data to a display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to the field of seven frame buffers for video display devices, and more particularly to addressing mechanisms for frame buffers.

[Conventional technology]

Video Random Access Memo for use with video display devices! j (VRAM) has come into commercial use in recent years. These video memories include a memory array for storing pixel data and a shift register formed on the same substrate on which the memory array is formed. The row address is used for rounding to transfer data to the shift register. The column address is then used to identify the starting location from which the data in the shift register is read. The operation of the shift register can be performed in synchronization with the array access. Typically, data is shifted out of the shift register at a much higher rate than the access speed of the dynamic RAM.

In many applications, an integer rate of scan lines per row line in memory is desired. That is, the shift register cannot be emptied in the middle of a scan line. Timing and other problems arise if this correlation is not maintained.

A non-integer number or integer rate of traversal f per line of video memory
The present invention provides a circuit for addressing VRAM while making it possible to display 11 images.

Among the features provided by the invention are a lookahead mechanism used to initiate memory cycles before the shift register is emptied;
There is. This lookahead mechanism allows the shift register to be emptied in the middle of a scan line and reloaded in a timely manner to continue the scan.

[Summary of the invention]

On this statement? If you are using VR on your computer display device.
A video device (hereinafter sometimes referred to as a video unit or video card) that provides video data from an array of AMs will be described. Interface means are used to interface between the video section and the computer's central processing unit II (CPU). Pixel data stored in the VRAM is readdressed by an address generator coupled between the interface means and the VRAM. The address generator includes a row address storage that stores row addresses and a column address storage that stores column addresses. A column counter is coupled to receive the column address. The column counter is clocked synchronously with the pixel clock rate (more specifically, the rate at which data is shifted out of the VRAM's shift register). A row address counter is coupled to the ninth receiving row address. The addressing means includes control means for increasing the count of the row counter when the column counter reaches a predetermined count (eg 256 if the shift register has 256 stages). The column count is then reset to zero, making it available for describing the next full row in the VRAM array.

Also, in the preferred embodiment, the signal is generated before the shift register is emptied. That signal is generated by keeping track of the amount of video data remaining in the shift register. The look-ahead feature is used to initiate the transfer of data from a VRAM memory location to a VRAM shift register.

Issues of the present invention, such as the compatibility of the video section with two different busses (NuBua and 68020 buses), are discussed in detail in the description below.

〔Example〕 Hereinafter, the present invention will be described in detail with reference to the drawings.

This specification describes a video device having an array of VRAMs for use in computers that include a central processing unit (CPU) and a main memory. In the following description, numerous details are set forth, such as specific numbers of bits, etc., in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without such specific details. In other instances, well-known circuitry and timing have not been described in order to avoid unnecessarily obscuring the present invention.

The video device of the present invention is realized as a video card inserted into a motherboard of a computer. The combinator shown in FIG. 1 includes a CPUIQ.

This CPU is a commercially available 68020 microprocessor. The CPU 10 connects to the main memory via a path 12.
Communicate with RAM11.

Path 12 is a standard path structure using protocols associated with the 68020 microprocessor.

For example, are the address and data signals separate? tllk
ie, their signals are not multiplexed on a common line. The computer includes multiple slots into which cards are inserted. Those slots are N
It is coupled to path 14 of uBua.

NuBum interface 13 is 68020 path 12
and NuBua. (For example, since data signals and address signals are multiplexed in NuBua, the interface circuit 13 is
It includes demultiplexing means. ) As mentioned above, the video card 15 is inserted into one slot of the computer and intersects with the NuBua 14.

The output from video card 15 includes standard red, green, and blue (KGB) signals. These signals are coupled to a video monitor to provide color narrowing.

Not shown are many circuits associated with the illustrated computer, such as ROM%, which stores system programs. Other aspects of the computer appear on dg
[Memory mapping unit (Escape MORY kite P)
Pending U.S. patent application entitled PING UNIT)
Slot (CARD FOR COMPUTERWITI)
(EXPANSIONSLOTS) Pending U.S. patent no.
Determining available memory size (ME
THOD AND APPARATUS FORDFJ
TERM-INING AVAILABLE MEyl
oRY 5IZE) J, pending U.S. patent application Ser. All such US patent applications are assigned to the assignee of the present application.

The computer shown in FIG.
ntosh) computer. Official K, 680
The processing power of the 20 microprocessor was superior to that of the early versions of this computer. The video card 15, unlike the black and white video of earlier versions of this computer,
Color video (gives No. 8).

The main elements of the video card shown in Figure 1 are Nu
A Bua interface circuit 20, a card timing circuit 21, a frame buffer and controller 22, and a video output circuit 23. Since most of the invention resides in the frame buffer and controller 22, this first
m will focus primarily on the frame buffer and controller. To outline the environment in which the present invention is used, the NuBua interface 2u, card timing circuit 21, and frame buffer and controller 22 will only be described in general terms.

N%tBus interface circuit 20 provides an interface between the computer's NuBua 14 and video card 15. Data and address signals are Nu
It is buffered within the Bua interface circuit 20.

NuBua K associated well-known timing and control signals Jd are coupled to the card via the NuBu-interface circuit 20. They are write output enabled (
WROE), Reset, TMO and TMI, Interrupt Request (IRQ), Acknowledgment (aACK), Start and Pass Clock I, CLK). Nu
Outputs from Bua interface circuit 20 include separate data and address buses.

The data bus is coupled to frame buffer and control i22 and video output circuit 23. The address bus is coupled through card timing circuit 21 to frame buffer and controller 22. NuBua interface circuit 20 is fabricated using well-known components. That NuBua
The structure of the interface circuit is not critical to the invention.

Card timing circuit 21 performs card level timing. The video timing used in the present invention is generated by frame buffer and controller 22, which will be described below. This card level timing is not unique to the present aA, and a well-known timing circuit can be used. The card timing circuit 21 is
Selection (slot used in the decoder to generate No. 8) receives a&another line. The card timing circuit 21 receives a start signal and a bus clock (Bus CLK) (ei
nto,! J set value number, ACK signal, TMO signal, TMI signal, IRQ signal, - direct synchronization (VSYNC)
) No. 4 and the WROE signal are also received. In the embodiment described herein, the card timing circuit is fabricated from three programmable play logic integrated circuits.

Also included as part of card circuitry 21 is a configuration ROM that provides configuration information to the video card.

Frame buffer and controller 21 will now be described in detail, beginning with FIG. VRAM
, memory control, RAM address generation and digital pixel data generation, the frame buffer and controller 21 generally provides video timing and RAM timing. The frame buffer and specific inputs to controller 21 will be described with reference to later figures.

Video output circuit 23 includes a color lookup table.

These color look-up tables (CLTs) are well known in the art and include, for example, a digital signal that receives a symbol (e.g., 8 bits of pixel data) and represents a predetermined color, e.g., 8 bits of red. 8 bits representing green and 8 bits representing blue are given. These signals are converted to analog signals and then used to drive the color monitor. Those color lookup tables are in some cases ROM. The particular CLT used in video output circuit 23 is a RAM that is written to the data bus.

Frame Buffer and Controller Overview As shown in FIG. 2, the seven frame buffer and controller includes a frame buffer controller 25 and two RAM punctures. The RAM banks are RAM play 2B (punk O) and RAM array 27 (punk 1). RAM array 26.2T stores pixel data for display, which is sent via bus 33 to the color lookup table at the pixel clock rate (up to 8 bits in parallel).

In the embodiment described herein, the display device is 64
It has 0 x 480 pixels and the pixel clock speed is 30.24 mHz. Pixel data is sequentially output from the array via bus 24 (3 from the selected array).
2 bits) and then clocked out on bus 33 with 1, 2, 4 or 8 bits per pixel.

Next, the seven frame buffer controller 25 will be explained in detail with reference to FIGS. 3 and 4. This 7 frame buffer controller uses a reset signal and a pixel clock (PIX CLK).
), a 20 mHz timing signal, a physical address strobe (PAS), a TMQ signal, a TMI signal, a control selection signal, and a RAM selection signal. data line D
24-D31 are coupled to the controller and are used to load the control registers. Data confirmation error signal (DT
ACK) is provided by the frame buffer controller as part of the data transfer protocol. NuBua'! by the frame buffer controller, as will be explained in more detail below with reference to FIG. or 68020 path. The signal on line 34 is 2
Indicates which of the two buses are coupled to the frame buffer controller. (Nubua is used in the present case.) Frame buffer controller 25 also receives a 19-bit address field (one for puncture selection).

In addition to the pixel data outputs and addresses, the controller provides control signals to arrays 26 and 27.

Standard row address strobe (RAS) and column address strobe (CA8) signals are provided to both arrays. RASO indicates the row address strobe for Punk O and RASI indicates the row address strobe for Punk 1. Similar l-OJ for other control signals
The modulus is used for the symbolism of ``1''. The DTOEO signal and the DTOE 1 signal are 4fA video RAM signals (data transfer output enable) that are loaded into the foot register in the video RAM.

The four wires of the WEN O to WEN 3 wires (WENO-3) are coupled to both plays for pie train translation when data is read into the array from bus 29.

SCO is a serial clock signal coupled to both arrays. 5OEO and 5OEI are serial output enables, one for each puncture.

The controller also uses standard timing signals, especially the pixel clock signal, horizontal synchronization signal I5YNCH), vertical synchronization (V5YNCH) No. 4, and composite synchronization (C5YNCH).
) signal, and composite blanking (CBL-ANK)
give a signal.

The Tani Array Q in the embodiment described herein is a commercially available video RAM, especially NEC No.

It has 8 pieces of 41264 RAM. Those valleys "chips"
has an array configuration of 256 rows (plK bits per row) and 25
It includes a 6-stage (94 bits per stage) shift register.

Therefore, each 16-bit address (row address signal 8
bit, column address signal (8 bits multiplexed on bus 28) selects one row in each video RAM, allowing 256 x 4 bits to be transferred to each RAM's shift register. Signals SOE_O and SOE_1 allow selection of arrays 26 or 27, so since there are eight 256.times.4 registers in the valley array, each array can combine 32 bits of data into 24.

Controller The main components of the frame buffer controller 25 are shown in FIG. 3 as an interface circuit 35, a RAM controller 36, an address generator 37, a video timing circuit 38, and a video multiplexer. Certain signals coupled to the frame buffer controller 25 shown in FIG. 2 are coupled to the interface circuit 35 of FIG. (Interface circuit 35 in FIG. 3 is different from interface circuit 20 shown in FIG. 2, and is not part of interface circuit 20. Interface circuit 25 provides an interface between the video card and NuBu@ conduct). Interface circuit 3
5 receives signals from the NuBua or directly from the 68020 path and provides control signals used by the controller and buffer. Interface circuit 35
This will be explained in detail later with reference to FIG.

RAM controller 36 receives inputs thereto, specifically a reset signal, a RAM select signal, a 20 mHz clock signal, as well as a size O signal, a size 1 signal and a read signal from interface circuit 35.

The RAM controller sends normal control signals to the RAM, mainly RAS.
.

Provides signals such as CAS, WEN, DTOE, etc., as well as data acknowledgment signals for NuBum or 68020 handshakes. size 0 signal ε size 1
Determine which byte lanes of the 32-bit data bus are in use. RAM controller 36 is VR
It also controls AM refresh. The RAM controller uses conventional circuitry that is not important to the invention.

The address generator 3T will be explained with reference to FIGS. 5 and 6.

The video timing circuit 3B receives a pixel clock,
A composite synchronization signal, a blanking signal, a horizontal synchronization signal, and a vertical synchronization signal are generated. Timing circuit 38 also provides timing signals to address generator 37 and multiplexers. Video timing circuit 38 is fabricated using known circuitry.

Multiplexer 39 receives 32 bits of data from the RAM on path 24 and couples the video data to pixel data bus 33. Data is combined with 1 bit, 2 bits, 4 bits or 8 bits per pixel depending on the mode selected.

Next, refer to Figure 4. The interface circuit connects latches 41 and 42. Those latches are one of the address buses.
Receive 8 lines. Hold operation is physical address strobe C
PAS).

The NuBua select signal or the 68020 select signal on line 39 controls the polarity of the output from the circuit shown in FIG. 4 (the NuBua and 68020 have opposite polarity references). In this way, the signal on pin 39 is transmitted to latch 41.42.
to control the output polarity on line 18; similarly, the signal on line 39 is coupled to multiplexer 4 for the same purpose.
8-51.

(The polarity of the g output signal is not changed.)

The latch 43 receives the AO flaw signal, the latch 44 receives the artificial flaw signal, the 2-pin 45 receives the size O signal, the latch 46 receives the size i@ signal, and the latch 4T reads out the ]l! receive the issue. The output terminal of the two-way 43 is coupled to a multiplexer 48, and as can be seen, when the multiplexer 480A terminal is selected, the AO signal appears at the output terminal of the launch 48. The QN output of the latch 43 and the Q output of the RAM 45 are applied to the input terminal of the Nant gate 52, and the B input is applied to the multiplexer 48. Since the Q output of latte 44 is applied to the multiplexer 490A input terminal, when the A input terminal of that multiplexer 49 is selected, the A1 signal appears at the output terminal of that multiplexer. The OR gate 53 receives the Q outputs of the latches 45 and 43, and provides one input terminal to the Nant gate 540. The QN output of latch 44 is applied to the other input terminal of Nant gate 54.

Multiplexer 5G receives the Q output of latch 45 at its A input terminal, so that when input terminal A is selected, the size O compensation is coupled to the output terminal of multiplexer 50. The input terminal of the multi-breather 500B is the QN of the latch 45.
Receive output. Multiplexer 51 receives the Q output (size 1 signal) of latch 46 at its A input terminal. Therefore, when the A terminal is selected, its Q output is coupled to the output terminal of multiplexer 51. B of multiplexer 51
input! 1 is coupled to the output terminal of the Nant gate 55.
L. The inputs to this Nant gate are the QN output of the RAM 45 and the Q output of the latch 43. The read signal is coupled directly through latch 4T.

To understand the operation of the circuit shown in factor 4,
Main control number 18 from 8020 bus reads, size 0
, size 1, AO, Aljr and PAS''c3). Data and address signals are not multiplexed. For NuBui+, the main control signals are TMO, TλII, AO, AI, set at start.Address and data are multiplexed and inverted.

The size Off signal and the size 1 signal are the size of data to be transferred, -j7i, 8, 1 on a 32-bit bus.
6,32.6AO indicating 24 or 32 bit wide transfer
The fH and A1 signals indicate where on the bus the transfer occurs.

That is, for example, an 8-bit transfer is performed on lines D7-015.
It can happen.

However, since NuBum does not support 3-byte transfers, size Q (input to RAM4S) is always at a high level when the signal applied to the circuit of FIG. 1 is the NuBua signal.

As shown in FIG. 4, signals AO, AI, size O.

Size 1 and Read are signals compatible with the 68020, and when used they are coupled directly through this circuit and appear at the output terminals of the multiplexer (
(excluding bladder ejection signal). The input to the circuit in Figure 4 is NuBu
When combined from a, the corresponding equation is realized by the circuit of FIG. 4 (the TM1 signal is understood as a read signal). "x" in the equation below indicates the output from the multiplexer.

XAO=AO@5ize 0 XAI=AOV 5ize O-AIX 5l
ze O= 5ize OX 5ize l
= AO·5ize O By implementing the above equation, the Nu[1us control signal is translated into the same signal. If the interface circuit were to be coupled directly to the 68020 path, those same signals would be detected at the output terminal of the interface circuit.

Before discussing address generators, it is helpful to examine VRAM and its addressing mechanism. 6th
A VRAM 62 is shown in the figure. This VRAM 62 has a memory array 63 and a shift register 64. This VRAM is RAM array 26. shown in FIG.
One RAM among the plurality of VRAMs constituting 27 is used. As mentioned above, the 8-bit row address coupled to the VRAM selects a row of data, such as row 66 of array 63. This data is shifted to shift register 64 as indicated by ll1I65. R
The column address given to AM@4 is the shift register 6.
4 is shifted from the shift register to output line 58 (four bits at a time).

For example, the column address may be selected to correspond to column 68 along row 66. The first data appearing at 1158 is then the data stored at location 68.

As the shift register shifts 9, the data represented by middle active arc 59 is shifted out of register 64.

Refer now to FIG. The address generator includes a length multiplexer 76. This multiplexer receives a signal indicating whether a particular frame has odd or even scan lines of the display that are interlaced. line 10
A second signal coupled to multiplex '9'' T6 via T6 is coupled to each pair of scan lines (even scan line and odd scan line) of the display.
The length of digital data required for kW is given as the digital number. As mentioned above, the length is not fixed since the embodiments described herein can use 1, 2, 4 or 8 bits per pixel. (The program allows you to select the length of each pixel by software.) If we use one bit per pixel, there is enough data, and therefore enough, to store the pixel data for each scan line. Small storage is used. ! The signal on 109 indicates when a new frame begins and is used to control the selection in offset at the output terminal (line 89) of multiplexer T6, as will be explained later.

Length multiplexer T6 makes the output at edge 89 zero;
It includes circuitry (the purpose of which will be explained later) that allows the number on line 108 to be halved or the number on line 108 to be halved.

Adder TI is a conventional digital adder, and line 8SI
Add the offset in K to the pace address on line 8a or the address on line 90.91. The control signal on line 92 for each new frame causes the signal on line 8 to be added to zero or one-half the number on line 10B, depending on whether an odd frame or a posted frame is displayed. The digital numbers on line 89 are then added to the digital numbers on [90 and 91] (for the remainder of the frame). The output of the adder, which is the address of the VRAM memory, contains a row field and a column field (8 bits each). The fields are coupled to registers 81 and 82. The row address is also coupled to a row address counter 80, and similarly the column address is coupled to a RAM (column) counter T9.

Row multiplexer 84 connects the output of row address counter 80 (line 86) and the output of row address register 82 (line 94).
Choose between. At the beginning of each frame, multiplexer 84 selects the output of row address register 82. VR
When the shift register associated with AM reaches its end, the address on line 96 is selected. counter 80
increases the address stored in register 82 (by 1) each time the shift register reaches its end.

Column multiplexer 85 combines the contents of register 81 with line 95.
Select between the zero address above. At the beginning of each scan line, the address of register 81 is selected. That address, which is also coupled to column counter 79, indicates that the data is in VRAM.
is incremented by the rate at which it is shifted in the shift register. (VRAM for each count in column counter 79)
Since there are 32 bits from , its speed is lower than the clock speed of Bixel. ) An output signal is provided on line 101 when column counter 13 exceeds a predetermined count (9, eg, 256). The output signal causes multiplexer 84 to select line 96 and multiplexer 85 to select the zero address.

Line 93 provides timing and control signals to implement counting operations and address transfer, which will be described later.

A comparator 83 compares the count in column counter 1g with the digital number stored in lookahead storage means 18. The contents of that count are transmitted to comparator 83 via line 9T.
The contents of storage means T8 are coupled to comparator 83 via msa.

When the contents of the column counter 79 match the number stored in the storage means T8, the comparator 83 produces a signal to the cutting edge 1100. In the embodiment described here, lookahead storage means 78 stores digital numbers. That digital number can be changed (typically by software)
.

Multiplexer BT selects the output of multiplexer 84, the output of multiplexer 85, and the input provided via line 112. The address on line 112 is the CPU
Available from NuBua.

They are used to load VRAM in the normal manner. The addresses from multiplexers 84 and 85 are the addresses used during scanning (Success Clean Φ Refrets 7).

A RAM bank selector 86 receives the side information and decodes the side information in the conventional manner to select bank 0 of the memory array.
and bank 10. For the following explanation,
It does not matter which bank is selected.

Address Generator Operation Now assume that the VRAM play contains pixel data for display. (As mentioned above, the pixel data is stored on data bus 29 at the address from line 112.)
The addresses are then coupled to the VRAM via path 28 in FIG. ) The CPU provides a base address corresponding to the location of the data, for example, to the top left corner TO of display 67 in FIG. This address does not need to match the beginning of a row line in memory. That is, there may be a column address such that the data for pixel TO begins in the middle within the shift register.

The pace address is coupled from line 88 to adder 77.

Since this is a new frame (assuming odd scan lines), the O on line 89 is coupled to the adder. Adder T7
The output of contains the pace address. This pace address is in register 81. ! :82 and is also o-loaded to counters 79 and 80. As data is clocked out of the shift register (eg, shift register 64 in FIG. 6), the count in counter T9 is incremented. For each shift register stack, a 32-bit data word is combined from the VRAM. 8 per pixel
If bits are used, the count in counter 79 is increased at one-fourth the pixel clock rate. Similarly, if 91 bits per pixel were used, the counter 790 count would be incremented at 1/32 of the pixel clock rate. (In fact, the shift register can operate synchronously from the pixel clock, as long as the data is accessed fast enough to meet the demands of the display mode. ) When the count of counter T9 reaches a predetermined value (for example 256), the last stage of the shift register is accessed. The signal on line 101 causes row multiplexer 84 to select the address on mss. For example, this is the base row address incremented by #il. That is, the next line in memory.

``Also, the signal on MA 101 causes multiplexer 85 to select line 95, which selects the first stage of the shift register.

Additionally, counter T8 is reset (O count).

For each subsequent scan line, the row address from row address register 82 and the column address from register 81 are set on line 8.
9 is added to the offset above. The new address is then coupled to registers 81.82 and selected by multiplexers 84.85.

When an odd number of scanlines is displayed, an offset on [189] is added to the paced address after the first scanline as described above (scanline 1 where the paced address is used).
except for). That is, for scan line 3, the addresses on lines 90 and 91 (which are pace addresses) are added to the offset to obtain the next line. For run a5, the offset is added to the addresses on lines 90 and 91 corresponding to scan 11ii13, thereby providing the starting address for scan line 5.

For even scan lines, the location in VRAM corresponding to scan line 2 must be addressed at the start of the frame. Here, running f? ! Half the length on line 10a is added to the pace address on 188 to obtain the address for ii2. This address from 90°91 is added to the total length (offset on line 89) to obtain the addresses for scanline 4 and the remaining υ scanlines in the frame.

Thus, to summarize for odd scan lines, the offset is initially zero, whereas for even scan lines, the offset is initially half the length. For non-interlaced displays, no odd-even signal is required and the length on line 108 corresponds to the length of the data between successive scan lines on the display.

Referring again to Figure 6, the importance of address generation in Figure 5 can be more easily understood. Assume that scan MA 75 of display 67 is scanning. Also assume that the addresses associated with registers 81 and 82 correspond to row 66 and column location 68 of array 63. This entire row is transferred to the shift register, with the first data from the shift register corresponding to column location 68. This provides pixel data for pixel 69 of scan line 75. As data is transferred from the 77 register 64, it is of course used via the color lookup table to obtain the video signal necessary to color line T5. The count of counter 79 is incremented. In this case, the number of counts required to reach 256 corresponds to the part enclosed by curly braces 59. When the end of the shift register is reached, data is loaded from the next row in the array, shown as row 660 (this address is derived from counter 80). For now, the column address is 0 υ,
from line 95 by multiplexer 85. The data at location 72 provides the pixel data for pixel 74 of i75.

Therefore, the data for pixel 73 is the IP! of row 66, as shown by line T1. Coming from 9.

The data for the next pixel 74 is in the next row (row 660).
from the beginning of the shift register (column 72). This means that even if data is stored in the array 63,
This is because a fixed number of scan lines does not necessarily map to a fixed number of rows. This allows data to be stored in array 63 more efficiently.

Memory cycle time is consumed to address a row and transfer data from that row to the shift register.

This time is relatively long compared to the pixel speed. The present invention provides a lookahead percentage indicator that alerts the device that it is nearing the end of the data in the shift register. Display 6 to indicate that the lookahead mechanism is activated in the plane that reaches the data for pixel T3.
70 wire 105 is used.

The lookahead mechanism is used in the lookahead storage means 781 of the Wks diagram. The number is stored and compared with the contents of counter 79 as described above. Before reaching the end of the shift register, a signal appears on line 10G. This signal is
Used as the RAM system # signal to start the time sequence of transferring data to the shift register. (In order to quickly transfer data from the next row to the shift register, the DTOE signal can be asserted while the data is being sent out from the shift register.) A smooth transition of data is made. Lookahead 105 in FIG. 6 is programmable. That is, a longer lookahead is used when more pixel data (e.g., 8 bits per pixel) is at stake, and a shorter lookahead is used when less pixel data (e.g., 1 bit per pixel) is required. is used.

In the embodiment described here, comparator 83 examines the six most significant bits of the count of counter T9, and memory 80 can be programmed from three to six bits.

The above provides a very efficient use of the video RAM, allowing pixel data to be stored in the video RAM without having an integer rate of scan lines per row of memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a video unit (video card) implementing the invention in a preferred embodiment of the invention and the connection of the card to a computer via a NuBua interface circuit; FIG. Figure 3 is a partial block diagram of the controller in Figure 2, Figure 4 is a partial circuit diagram of the bus interface circuit in Figure 3, and Figure 11g5 is a block diagram of the controller of the present invention. Detailed Block Diagram of the Address Generator Used in the Preferred Embodiment, FIG. 6 is a diagram used to explain the operation of the address generator shown in FIG. 10...CPU, 11...RAM, 13
. 20. NuBua interface circuit, 15.
. . . video card, 21 . . 9 output timing circuit, 22 . . . frame buffer and controller, 23
...Video output circuit, 25...φ frame buffer 1tilj control! , 26 , 27... video RAM
Array, 35...Interface circuit, 36φ.
・・RAM controller, 37・Fist・・Address generator, 38
...Timing circuit, 39...Video multiplexer, 41-4T...Latch, 48-51...
・Multiplexer, 76...Yuki length multiplexer,
77... Adder, 78-... Look ahead storage means, 79... RAM counter, 80... Training address counter, 81... Φ... Column address register, 8
2... Row address register, 83... Comparator,
84...Row multiplexer, 85...Column multiplexer, 86...RAM bank selector.

Claims (4)

[Claims] (1) A video device that provides video data to a display device when coupled to a computer including a central processing unit (CPU), comprising: interface means for interfacing to said CPU; and a plurality of video random access memories (VRAM). and addressing means for addressing the VRAM coupled between the interface means and the pixel data memory, the addressing means comprising: (a) a row address storage for storing row addresses; (b) a column address storage device for storing column addresses; (c) row counter means for incrementing said row address; (d) column counter means for receiving said column address;
) control means for selecting said row counter means when said column counter means reaches a predetermined count, whereby said pixel data memory is accessed to provide video data to a display device; Video equipment that provides data. (2) A video device that provides video data to a display device when coupled to a computer including a 68020 central processing unit (CPU), a main memory, and a NuBua in communication with the CPU and the main memory, wherein the NuBua or the interface means for selectively interfacing with one of the 68020 CPUs; a pixel data memory having a plurality of video random access memories (VRAM); and addressing the VRAM coupled between the interface means and the pixel data memory. addressing means, the addressing means comprising: (a) a row address storage for storing row addresses; (b) a column address storage for storing column addresses; and (c) for receiving said row addresses. (d) a column counter coupled to receive said column address; and (e) control means for incrementing said row counter when said column counter reaches a predetermined count. , whereby said pixel data memory is accessed to provide video data. (3) A video device for providing video data to a display device when coupled to a computer including a central processing unit (CPU) and a main memory, comprising: interface means for interfacing to said CPU; and a plurality of video random access memories (VRAMs); ); and addressing means for addressing the VRAM coupled between the interface means and the pixel data memory, the addressing means comprising: (a) an adder receiving a base address and an offset; (b) a row address storage device that stores the row address received from the adder; (c) a column address storage device that stores the column address received from the adder; (d) a column address storage device that stores the row address received from the adder; (e) a row counter coupled to receive said column address and said V
(f) control means for incrementing said row counter when said column counter reaches a predetermined count; A video device for providing video data to a display device, wherein the pixel data memory is accessed to provide video data. (4) In a video device that provides video data to a display device when coupled to a central processing unit (CPU) and main memory, a storage array addressed by row addresses and a shift register readdressed by column addresses are provided. Multiple video random access memories (VRA), each containing
M); addressing means for providing the row address and the column address; detection means for providing a first signal before the end of shifting of data from the shift register; and the first signal is received from the detection means. 2nd time when accepted
a control means for applying a signal to the VRAM, whereby the VRAM is addressed.