JPS61129194U - - Google Patents
Info
- Publication number
- JPS61129194U JPS61129194U JP19694984U JP19694984U JPS61129194U JP S61129194 U JPS61129194 U JP S61129194U JP 19694984 U JP19694984 U JP 19694984U JP 19694984 U JP19694984 U JP 19694984U JP S61129194 U JPS61129194 U JP S61129194U
- Authority
- JP
- Japan
- Prior art keywords
- state
- control signal
- gate control
- input signal
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Description
第１図はこの考案による時間間隔測定装置の一
例を示すブロツク図、第２図はその動作の説明に
供するためのタイムチヤート、第３図はこの考案
による時間間隔測定装置の他の例を示すブロツク
図、第４図はその動作の説明に供するためのタイ
ムチヤート、第５図は従来の時間間隔測定装置を
示すブロツク図、第６図はその動作の説明に供す
るためのタイムチヤート、第７図は複合パルス幅
、複合周期を説明するためのタイムチヤート、第
８図は二つの信号間の時間間隔を測定する場合の
ゲート制御信号発生回路１４の例の一部を示すブ
ロツク図、第９図はゲート制御信号発生回路１４
の他の例を示す論理回路図である。
１４：ゲート制御信号発生回路、１５：第１入
力端子、１７：第２入力端子、１８：ゲート、１
９：クロツク発生器、２５：リセツト端子、２１
：測定用計数器、２２：表示器、２６：設定手段
、２９：マスク用計数器。
Fig. 1 is a block diagram showing an example of the time interval measuring device according to this invention, Fig. 2 is a time chart for explaining its operation, and Fig. 3 shows another example of the time interval measuring device according to this invention. 4 is a time chart for explaining its operation; FIG. 5 is a block diagram showing a conventional time interval measuring device; FIG. 6 is a time chart for explaining its operation; FIG. The figure is a time chart for explaining the composite pulse width and the composite period, FIG. 8 is a block diagram showing part of an example of the gate control signal generation circuit 14 when measuring the time interval between two signals, and FIG. The figure shows gate control signal generation circuit 14
FIG. 3 is a logic circuit diagram showing another example of the above. 14: Gate control signal generation circuit, 15: First input terminal, 17: Second input terminal, 18: Gate, 1
9: Clock generator, 25: Reset terminal, 21
: Measurement counter, 22: Display, 26: Setting means, 29: Mask counter.
Claims (1)
状態とされ、第２入力端子に第２入力信号が与え
られて他の状態に反転され、その１の状態から他
の状態になるまでの間ゲート制御信号をゲート制
御信号発生回路から発生し、そのゲート制御信号
によりゲートを開き、そのゲートが開かれている
間これを通過したクロツクを測定用計数器により
計数し、その測定用計数器により計数された値を
上記第１入力信号から第２入力信号までの時間間
隔として測定する時間間隔測定装置において、 複合すべき入力信号の個数を設定する設定手段
と、上記第１入力信号を計数するマスク用計数器
と、そのマスク用計数器が上記設定手段の設定個
数と対応した値を計数するまで上記ゲート制御信
号発生回路からのゲート制御信号の停止を阻止す
る阻止手段とを設けたことを特徴とする時間間隔
測定装置。[Claims for Utility Model Registration] A first input signal is applied to the first input terminal to set the state to 1, a second input signal is applied to the second input terminal to invert the state to another state, and the 1 state is inverted by the application of the second input signal to the second input terminal. A gate control signal is generated from a gate control signal generation circuit until the state changes from one state to another, the gate is opened by the gate control signal, and a clock that passes through the gate is measured by a counter. in a time interval measuring device for counting by the measuring counter and measuring the value counted by the measuring counter as the time interval from the first input signal to the second input signal, setting means for setting the number of input signals to be combined. and a mask counter for counting the first input signal, and stopping the gate control signal from the gate control signal generation circuit until the mask counter counts a value corresponding to the number set by the setting means. A time interval measuring device characterized in that it is provided with a blocking means for blocking.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19694984U JPS61129194U (en) | 1984-12-28 | 1984-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19694984U JPS61129194U (en) | 1984-12-28 | 1984-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61129194U true JPS61129194U (en) | 1986-08-13 |
Family
ID=30754893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19694984U Pending JPS61129194U (en) | 1984-12-28 | 1984-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61129194U (en) |
-
1984
- 1984-12-28 JP JP19694984U patent/JPS61129194U/ja active Pending
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