JPS61128628A - Dynamic logical circuit - Google Patents

Abstract

PURPOSE:To set optionally the timing and time width or the like of an initial set signal by adding an initial setting signal holding circuit and an initializing detection circuit to a dynamic logical circuit. CONSTITUTION:When a signal at an initial setting input 4 goes to an L level, an output signal of the initial setting signal holding circuit 7 goes to an H level and the H level is kept even when the input 4 reaches the L level. An output of the circuit 7 is fetched into a reset terminal R of a counter 1 in the timing when an input signal 2, a clock T of the dynamic counter 1 goes to H and Q0 output 5 and Q1 output 6 of the counter 1 are initialized. The initializing detection circuit 8 detects the initialized signals 5, 6 and outputs an initializing end signal to the circuit 7. The circuit 7 receiving it releases the output to the counter 1 to complete a series of operation relating to the initial setting.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit that operates dynamically, and particularly to an initial setting circuit thereof.

[Conventional technology]

An example of a conventional dynamic logic circuit is shown in Figure 3 (
Examples of resetting a two-stage dynamic counter (hereinafter abbreviated as blade counter) are shown in a) and (b).

In Fig. 3(a), 1 is a counter, 2 is a
Input 3 is a Kukku T input whose phase is shifted from Kukuku T so that it does not overlap, and 4 is an initial setting input, which is II HH here, and is a reset input that becomes effective when T="H".几 is the reset terminal, 5 is the lower Q
0 output, 6 is upper Q8 output. Also, Fig. 3(b)
An example of the configuration of the counter 1 using transistors (KMOS) is shown, and the reference numerals in the figure are the same as in FIG. 3(a) above.

Next, the operation will be explained. FIG. 4 shows a timing diagram of the operation. w, Figure 4 (a) is the beam Pt clock T signal, (b) is the clock T signal, and (C) is the Q. (d) shows the Q1 signal, and (e) shows the reset signal. The period t shown in FIG.
In this case, the reset signal (e) is OFF, and the counter 1 repeats the counting operation. Next, the reset signal (e) is T
(b) The timing of turning on when = “H” is the period t
b11c shown. At this time, the reset signal (e
) is not inherited and does not affect the counting operation. In period 1c, when T(a)=“H”, the reset signal (e) is ON, and the Qo times signal C), Q, and signal (d) are set.

In this way, in a dynamic logic circuit, the input.

Since both outputs are performed in synchronization with the clock T signal (a) K, the period t1. As shown in , even if an initial setting signal is input, it may be ignored.

[Problem that the invention seeks to solve]

Since the conventional dynamic logic circuit is configured as described above, it is necessary to synchronize the initialization signal with the clock TK, and there are also constraints on the timing of the initialization input signal, such as the time width of the signal is limited. The problem was that it was large.

Another way to solve the above problem is to make the logic circuit static, so that the input condition of the initialization input signal is asynchronous with the clock, but this is because the elements The number increases;
There was a problem in that it was not suitable for miniaturization when it was integrated into an integrated circuit.

This invention was made to solve the above-mentioned problems, and the timing of the initial setting signal.

The purpose of this invention is to obtain a dynamic logic circuit whose time width etc. can be set arbitrarily.

[Failure to solve the problem]

The circuit according to the present invention is a dynamic logic circuit in which an initialization signal holding circuit and an initialization detection circuit are added.

[Effect]

In the initial setting circuit according to the present invention, the initial setting signal holding circuit outputs the initial setting signal to the dynamic logic circuit in response to the initial setting signal, and holds the initial setting signal until the initial setting signal is input from the initial setting detecting circuit.

When the initialization detection circuit detects that the output of the dynamic logic circuit has been initialized, it outputs an initialization completion signal to the initialization signal holding circuit.

Upon receiving this initialization completion signal, the upper mt21J period setting signal holding circuit releases the output of the initial setting signal.

〔Example〕

FIG. 1 is a book diagram showing an embodiment of the present invention.

In FIG. 1, numerals 1 to 6 indicate the same parts as in FIG. 3. γ is an initial setting signal holding circuit, 8 is an initialization detection circuit, and the initial setting signal holding circuit T receives an initial setting signal and an initialization completion signal from the initialization detection circuit 8, and outputs an initial setting signal to the counter 1. or cancel it. The initialization detection circuit 8 monitors the output of the counter 1 and sends an initialization completion signal to the initialization holding circuit 1 only when the initialization conditions are satisfied.
Output to. The initialization state detected by the initialization detection circuit 8 occurs even during normal operation and generates an initialization completion signal.
The signals other than the initialization completion signal after inputting the ω-period setting eccentricity at the initial setting holding port 'e & 7 are restricted and do not affect the operation of the counter 1.

Next, the operation will be explained. FIG. 2 is an operation timing chart in the above embodiment. (,) to (d) are the same as shown in FIG. 4, (f) is the initial setting input 40 signal, (g) is the output signal of the initial setting signal holding circuit 7,
(h) shows the output signal of the initialization detection circuit 8.

In the period t□ shown in FIG. 2, the initial setting human power 4 signal (f
) is OFF, and the Q0 signal (b) of counter 1, Q
The +multiplying signal C) changes in synchronization with the clock T signal (a). Even during this period, the output signal <h> of the initialization detection circuit 8 is Q. An initialization completion signal is output according to the values of the signal (c) and the Q1 signal (d), but since the initial setting signal (g) is not output, there is no effect on the counter 1. Next, the operation when the initial setting signal (f) is turned ON is shown in period tb. The timing at which this initial setting signal tfl turns ON is T
= "L" and was ignored in the next circuit. First, when the signal (f) of the initial setting human power 4 becomes ``L'', the output (g) of the initial setting signal holding circuit 7 becomes ``''Hn
K, which means that the initial setting human power 4 signal (f) is ++ H
It is retained even if it becomes n. Next, the output of the initial setting signal holding circuit 7 is taken into the counter 1 at the timing when the clock T signal (a) becomes H'', and its output is the Q signal (C).

Q, initialize signal (d). The initialization detection circuit 8 is Q.

It detects that the signal (C) and the Q+multiple signal d) have been initialized, and outputs an initialization completion signal to the initial setting signal holding circuit 7. Upon receiving the first half initialization completion signal, the initial setting signal holding circuit 7 scales the output to the counter 1 and completes a series of operations related to the 4JJM setting.

Note that although the above actual mlJ describes the counter 1 that operates with a two-phase clock, other dynamic logic circuits such as a dynamic shift register may also be used.
Further, the same effect can be obtained in a multi-phase clock such as a three-phase or four-phase clock, which is limited to two phases.

〔Effect of the invention〕

As described above, the present invention adds an initialization detection circuit and an initialization signal holding circuit to the dynamic logic circuit, so that the timing and duration of the initialization signal to the dynamic cooking circuit can be set arbitrarily. Therefore, when configuring a semiconductor integrated circuit, the number of logic elements can be reduced and the degree of integration can be improved.

[Brief explanation of drawings]

1 is a block diagram of a dynamic logic circuit according to an embodiment of the present invention, FIG. m2 is a timing diagram showing the operation of the embodiment of FIG. 1, and FIG. 3 is a clock diagram of a conventional dynamic logic circuit. FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 3. In the figure, %1 is a dynamic counter, 2 is a clock T
3 is a clock T input, 4 is an initial setting input, 5 is a lower Q0 output, 6 is an upper Q1 output, 7 is an initial setting signal holding circuit, and 8 is an initialization detection circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 1 Nidai Namitsuku type Kakuntahi 1+, OCl

Claims (1)

[Claims] In a dynamic logic circuit that has an initialization signal input and operates with non-overlapping multiphase clocks, an initialization detection circuit that detects the initialized output of the dynamic logic circuit and outputs an initialization completion signal. and an initialization signal holding circuit that holds the initialization signal and releases the initialization signal upon receiving an initialization completion signal from the initialization detection circuit.