JP2581463B2 - Differential XOR circuit and frequency multiplier using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for performing frequency multiplication using a voltage-controlled delay line, and more particularly to a configuration of an XOR circuit for reducing its jitter.

[0002]

2. Description of the Related Art Conventionally, for example, a circuit as shown in FIG. Input terminal 231
Is applied to the input terminal of the voltage control delay line 113, and a delay signal is output.
The delay signal and the input clock signal are compared in phase by the phase comparator 111 to output a phase comparison signal. After the high frequency component is removed by the loop filter, the phase of the input clock signal and the delay signal become equal. Thus, the delay time of the voltage control delay line is controlled such that one cycle of the input clock signal is equal to the delay time of the voltage control delay line.

This voltage control delay line is usually constructed by arranging voltage control delay elements in a chain as shown in FIG. 7, but if these voltage control delay elements are made of the same material, the output Ends 362, 363,
The relationship between the phases of the signals output from 364, 365 and the like is proportional to the number of delay elements that have passed.

Therefore, when the delay time of the voltage control delay line is equal to one cycle of the input clock, the two output terminals output from the two output terminals having different numbers of passing stages by exactly 1/4 of the total number of voltage control delay elements. The signal has a 90 degree phase.

[0005] By inputting these two signals to the XOR circuit, a signal obtained by multiplying the input clock signal can be output.

A conventional XOR circuit uses a circuit as shown in FIGS.

[0007]

The XOR circuit as shown in FIGS. 5 and 6 has a different signal propagation path depending on the state of the input signal. Therefore, the delay time greatly depends on the state of the signal input terminal and other signals. Was different.

For example, in the circuit shown in FIG. 5, the delay time differs greatly between a path passing through the inverter 43 and the transfer gate 51 and a path passing only through the transfer gate 52.

In the circuit shown in FIG.
And the path passing through OR-NAND gate 71 and OR
-The delay time differs greatly in the path passing only through the NAND gate 71.

If the delay time of the XOR circuit changes depending on the state, the cycle of the output clock of the PLL clock multiplying circuit changes depending on the state of the input terminal of the XOR, thereby causing large jitter.

An object of the present invention is to provide a configuration of an XOR circuit and a PLL clock multiplication circuit that minimizes a change in the period of the output clock caused by the XOR circuit.

[0012]

The use of a differential type XOR circuit as shown in FIG. 2 reduces the difference in the signal transmission path depending on the state, thereby reducing the difference in the delay time of the XOR circuit. The jitter of the output clock of the clock multiplication circuit is reduced.

[0013]

FIG. 1 shows an embodiment of a PLL clock multiplication circuit using a voltage control delay line according to the present invention. An input clock signal applied to the input terminal 201 is applied to an input terminal of the voltage control delay line 103, and a delay signal is output. The delay signal and the input clock signal are connected to the phase comparator 1
01, and outputs a phase comparison signal. After the high frequency component is removed by the loop filter, the phase comparison signal is adjusted so that the phases of the input clock signal and the delay signal become equal, that is, one cycle of the input clock signal. The delay time of the voltage control delay line is controlled so that the delay times of the voltage control delay line become equal.

This voltage control delay line is normally
As shown in FIG. 2, the voltage control delay elements are arranged in a chain, and if these voltage control delay elements are made of the same material, the output terminals 362, 363,
The relationship between the phases of the signals output from 364, 365 and the like is proportional to the number of delay elements that have passed.

Therefore, when the delay time of the voltage control delay line is equal to one cycle of the input clock, the two output terminals output from the two output terminals having different numbers of passing stages by exactly 1/4 of the total number of the voltage control delay elements. The signals have a phase difference of 90 degrees, and the two signals output from the output terminals having different numbers of stages by 1/2 have a phase difference of 180 degrees.

Therefore, the number of voltage control delay elements in the voltage control delay line is assumed to be 4n (n is a natural number), and m, m + n, m + 2n, m + 3n (m is a natural number satisfying 0 <m ≦ n) from the nearest input. The signals output from the output terminals of the four voltage-controlled delay elements are as follows, assuming that the phase of the signal output from the output terminal of the m-th voltage-controlled delay element is 0 degree.
The signals are delayed by 0, 90, 180, and 270 degrees.

By inputting these signals to the XOR circuit, a multiplied signal can be generated.

FIG. 2 shows a first embodiment of the differential XOR circuit according to the present invention.

For example, 0 degree is applied to the input terminal 211 and the input terminal 2
13 at 90 degrees, input terminal 212 at 180 degrees, input terminal 2
Assume that a signal having a phase delay of 270 degrees is given to 14.

FIG. 8 shows an example of a signal when such a signal is given to the differential XOR circuit of FIG.

If the input terminal 211 is High, the input terminal 212 is Low, the input terminal 213 is High, and the input terminal 214 is Low, nMOS1, nMOS4, pM
OS23, pMOS24 are on, nMOS2, nMOS
3. The pMOS 21 and the pMOS 22 are turned off, the input terminal of the inverter 41 becomes High, and the output terminal of the inverter 41 becomes Low.

If the input terminal 211 is Low, the input terminal 212 is High, the input terminal 213 is High, and the input terminal 214 is Low, nMOS3, nMOS4, pM
OS21, pMOS24 are on, nMOS1, nMOS
2. The pMOS 23 and the pMOS 22 are turned off, the input terminal of the inverter 41 becomes Low, and the output terminal of the inverter 41 becomes High.

If the input terminal 211 is High, the input terminal 212 is Low, the input terminal 213 is Low, and the input terminal 214 is High, nMOS1, nMOS2, pM
OS23, nMOS22 are on, nMOS3, nMOS
4. The pMOS 21 and the pMOS 24 are turned off, the input terminal of the inverter 41 becomes Low, and the output terminal of the inverter 41 becomes High.

If the input terminal 211 is Low, the input terminal 212 is High, the input terminal 213 is Low, and the input terminal 214 is High, nMOS3, nMOS2, pM
OS21, pMOS22 are on, nMOS1, nMOS
4. The pMOS 23 and the pMOS 24 are turned off, the input terminal of the inverter 41 becomes High, and the output terminal of the inverter 41 becomes Low.

As described above, the differential XOR circuit has a smaller difference in signal transmission path and a smaller difference in delay time depending on the state of a signal, as compared with a normal XOR circuit. pMOS and nMO
There is a difference between the rise time and the fall time due to the difference in S, but since the jitter is the fluctuation of the cycle from the rise to the rise or from the fall to the fall, the difference between the rise time and the fall time has little effect. .

FIG. 3 shows a second embodiment of the differential XOR circuit according to the present invention. The difference between the MOS transistors in the vertical stacking position, that is, whether the MOS transistor is a MOS transistor directly connected to the power supply or a MOS transistor having another MOS transistor sandwiched between the power supply and the power supply (for example, the pMOS in FIG. 2) (The difference in the positions of the transistors 21 and 22), the magnitude of the substrate effect differs, and the delay time slightly varies depending on the difference in the input terminals. The XOR circuit of FIG. 3 reduces the difference in delay time due to this basic effect by taking this position symmetry.

For example, in FIG. 2, the input terminal 211 is connected to the pMOS transistor 21 directly connected to the power supply and the nMOS transistor 1 directly connected to the power supply, but the input terminal 213 is not connected to the power supply.
Since the transistor is connected to the OS transistor 22 and the nMOS transistor 4 that is not directly connected to the power supply, the type of the transistor connected differs depending on the input terminal.

However, in FIG. 3, the input terminal 221 is the pMOS transistor 25 directly connected to the power supply, the pMOS transistor 28 not directly connected to the power supply, the nMOS transistor 5 directly connected to the power supply, and not directly connected to the power supply. The nMOS transistor 8 is connected, and the input terminal 223 is a pMOS transistor 27 directly connected to the power supply, a pMOS transistor 26 not directly connected to the power supply, the nMOS transistor 11 directly connected to the power supply, and an nMOS not directly connected to the power supply. The transistor 10 is connected, and the types of transistors connected by the input terminals are the same.

By doing so, the difference in delay time depending on the state of the input signal is smaller than in the XOR circuit of FIG.

[0030]

As described above, the jitter of the output clock in the PLL clock multiplication circuit using the voltage control delay line can be reduced by using the configuration of the present invention.

[Brief description of the drawings]

FIG. 1 shows a PL using a voltage-controlled delay line according to the present invention.
FIG. 3 is a diagram illustrating an embodiment of an L clock multiplication circuit.

FIG. 2 is a diagram illustrating a first embodiment of a differential XOR circuit according to the present invention;

FIG. 3 shows a second embodiment of the differential XOR circuit according to the present invention.

FIG. 4 shows a conventional PLL using a voltage-controlled delay line.
FIG. 3 is a diagram illustrating an example of a clock multiplication circuit.

FIG. 5 is a first embodiment showing a configuration of a conventional XOR circuit.

FIG. 6 is a second embodiment showing the configuration of a conventional XOR circuit.

FIG. 7 is an example of a voltage control delay line.

FIG. 8 is an example of an input signal and an output signal of a differential XOR circuit.

[Explanation of symbols]

 1-12 nMOS transistor 21-32 pMOS transistor 41-45 inverter circuit 51-52 transfer gate circuit 61 NAND circuit 71 OR-NAND circuit 81-88 voltage control delay element 101, 111 phase comparator 102, 112 loop filter 103, 113 Voltage control delay line 104 Differential XOR circuit of the present invention 114 Conventional XOR circuit 201 Input clock terminal 301 Output clock terminal 211 to 214 Input terminal 311 Output terminal 221 to 224 Input terminal 321 Output terminal 231 Input clock terminal 331 Output clock terminal 241, 242 input terminal 341 output terminal 251, 252 input terminal 351 output terminal 261 input clock terminal 262 delay control element 361 output clock terminal

Claims (3)

(57) [Claims] 1. A first nMOS transistor having a gate connected to a first input terminal and a source connected to a first power supply terminal, a gate connected to a second input terminal, and a source connected to the first input terminal. n
An nMOS transistor connected to the drain of the MOS transistor; a first pMOS transistor having a gate connected to the first input terminal and a source connected to the second power supply terminal; and a gate connected to the third input terminal. And the source is the first p
A second pM connected to the drain of the MOS transistor
An OS transistor; a third nMOS transistor having a gate connected to the fourth input terminal and a source connected to the first power supply terminal; a gate connected to the third input terminal;
Fourth nM connected to the drain of the MOS transistor
An OS transistor; a third pMOS transistor having a gate connected to the fourth input terminal and a source connected to the second power supply terminal; a gate connected to the second input terminal;
Fourth pM connected to the drain of the MOS transistor
An OS transistor; an input terminal of which is a drain of the second nMOS transistor; a drain of the fourth nMOS transistor;
An inverter connected to the drain of the S transistor and the drain of the fourth pMOS transistor and having an output terminal connected to the first output terminal, wherein a signal applied to the first input terminal and the fourth input terminal is 1
A differential XOR circuit having a phase shifted by 80 degrees and a signal applied to the second input terminal and the third input terminal shifted by 180 degrees. 2. A first nMOS transistor having a gate connected to the first input terminal and a source connected to the first power supply terminal, a gate connected to the second input terminal, and a source connected to the first input terminal. n
Second nM connected to the drain of the MOS transistor
An OS transistor, a third nMOS transistor having a gate connected to the second input terminal and a source connected to the first power supply terminal, a gate connected to the first input terminal, and a source connected to the third n terminal
Fourth nM connected to the drain of the MOS transistor
An OS transistor, a first pMOS transistor having a gate connected to the first input terminal and a source connected to the second power supply terminal, a gate connected to the third input terminal, and a source connected to the first p-type terminal.
A second pM connected to the drain of the MOS transistor
An OS transistor; a third pMOS transistor having a gate connected to the third input terminal and a source connected to the second power supply terminal; a gate connected to the first input terminal;
Fourth pM connected to the drain of the MOS transistor
An OS transistor; a fifth nMOS transistor having a gate connected to the fourth input terminal and a source connected to the first power supply terminal; a gate connected to the third input terminal;
Sixth nM connected to the drain of the MOS transistor
An OS transistor, a seventh nMOS transistor having a gate connected to the third input terminal and a source connected to the first power supply terminal, a gate connected to the fourth input terminal, and a source connected to the seventh n
Eighth nM connected to the drain of the MOS transistor
An OS transistor; a fifth pMOS transistor having a gate connected to the fourth input terminal and a source connected to the second power supply terminal; a gate connected to the second input terminal;
Sixth pM connected to the drain of the MOS transistor
An OS transistor, a seventh pMOS transistor having a gate connected to the second input terminal and a source connected to the second power supply terminal, a gate connected to the fourth input terminal, and a source connected to the seventh p-terminal.
Eighth pM connected to the drain of the MOS transistor
An OS transistor, an input terminal of which is a drain of the second nMOS transistor, a drain of the fourth nMOS transistor, and a sixth nMO
The drain of the S transistor, the drain of the eighth nMOS transistor, the drain of the second pMOS transistor, the drain of the fourth pMOS transistor, the drain of the sixth pMOS transistor, and the eighth pMO
An inverter connected to the drain of the S transistor and having an output terminal connected to the first output terminal, wherein a signal applied to the first input terminal and the fourth input terminal is 1
A differential XOR circuit having a phase shifted by 80 degrees and a signal applied to the second input terminal and the third input terminal shifted by 180 degrees. 3. A voltage controlled delay line having an input terminal connected to a first input terminal, a phase comparator having two input terminals connected to an output terminal of the voltage controlled delay line and a first input terminal. A loop filter having an input terminal connected to the output terminal of the phase comparator and an output terminal connected to the delay control element of the voltage control delay line; and four input terminals connected to the voltage control delay line. 3. The differential XOR circuit according to claim 1, wherein four output terminals of the output signals having different phases are connected, and the output terminal is connected to the first output terminal. Wherein a clock signal is input to the first output terminal and a multiplied clock signal is output to a first output terminal.