JPH0879061A - Differential xor circuit and frequency multiplier circuit using it - Google Patents

Abstract

PURPOSE: To obtain the differential XOR circuit with specified configuration in which a difference from the signal transfer path depending on the state of an input signal is decreased so as to reduce the difference from the delay time thereby minimizing a change in the period of an output clock resulting from the state of the input signal. CONSTITUTION: The differential XOR circuit is made up of NMOS transistors(TRs) 1-4, PMOS TRs 21-24 and an inverter 41. Signals whose phases are lagged by 0 deg., 90 deg., 180 deg. and 270 deg. from each other are given respectively to input terminals 211-214. For example, when the input terminals 211,213 are at a high level and the input terminals 212,214 are at a low level, TRs 1,4,23,24 are conductive and TRs 2,3,21,22 are switched off and the input terminal of the inverter 41 goes to a high level. The differential XOR circuit is used to reduce jitter of an output clock in a PLL clock multiplier circuit using a voltage controlled delay line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for frequency multiplication using a voltage control delay line, and more particularly to a structure of an XOR circuit for reducing its jitter.

[0002]

2. Description of the Related Art Conventionally, a circuit as shown in FIG. 4, for example, has been used for this type of frequency multiplication circuit. Input terminal 231
Is applied to the input end of the voltage control delay line 113, and a delay signal is output.
The delay signal and the input clock signal are phase-compared by the phase comparator 111 to output a phase comparison signal. After the high frequency component of the phase comparison signal is removed by the loop filter, the phases of the input clock signal and the delay signal become equal to each other. In this way, that is, the delay time of the voltage control delay line is controlled so that one cycle of the input clock signal and the delay time of the voltage control delay line become equal.

This voltage control delay line is usually constructed by arranging voltage control delay elements in a chain as shown in FIG. 7, but if these voltage control delay elements are made of the same one, the output Ends 362, 363,
The phase relationship of the signals output from 364, 365, etc. is proportional to the number of passed delay elements.

Therefore, when the delay time of the voltage control delay line is equal to one cycle of the input clock, the two output terminals having different passing stages by exactly ¼ of the total number of voltage control delay elements are output. The signal has a phase of 90 degrees.

By inputting these two signals into the XOR circuit, a signal obtained by multiplying the input clock signal can be output.

A conventional XOR circuit uses circuits as shown in FIGS. 5 and 6.

[0007]

In the XOR circuit as shown in FIGS. 5 and 6, the propagation path of the signal differs depending on the state of the input signal. Therefore, the delay time greatly depends on the state of the signal input terminal and other signals. It was different.

For example, in the circuit of FIG. 5, the delay time greatly differs between the path passing through the inverter 43 and the transfer gate 51 and the path passing through only the transfer gate 52.

In addition, in the circuit of FIG.
And a path passing through the OR-NAND gate 71 and OR
-The delay time greatly differs in the path that passes only the NAND gate 71.

When the delay time of the XOR circuit changes depending on the state, the cycle of the output clock of the PLL clock multiplying circuit changes depending on the state of the input terminal of the XOR, which causes a large jitter.

An object of the present invention is to provide a configuration of an XOR circuit and a PLL clock multiplication circuit that minimizes a change in the output clock cycle caused by the XOR circuit.

[0012]

By using a differential type XOR circuit as shown in FIG. 2, the difference in signal transmission path depending on the state is reduced, thereby reducing the difference in delay time of the XOR circuit, and eventually the PLL. The jitter of the output clock of the clock multiplication circuit is reduced.

[0013]

FIG. 1 shows an embodiment of a PLL clock multiplication circuit using the voltage control delay line of the present invention. The input clock signal applied to the input terminal 201 is applied to the input end of the voltage control delay line 103, and a delay signal is output. This delay signal and the input clock signal are the phase comparator 1
The phase comparison signal is output by 01 to output a phase comparison signal, and after the high frequency component is removed by the loop filter, the phase of the input clock signal is equal to that of the delay signal, that is, one cycle of the input clock signal. The delay time of the voltage control delay line is controlled so that the delay time of the voltage control delay line becomes equal.

This voltage control delay line is normally shown in FIG.
As shown in, the voltage-controlled delay elements are arranged in a chain, and if these voltage-controlled delay elements are made of the same material, the output terminals 362, 363,
The phase relationship of the signals output from 364, 365, etc. is proportional to the number of passed delay elements.

Therefore, when the delay time of the voltage control delay line is equal to one cycle of the input clock, the two output terminals having different passing stages by exactly ¼ of the total number of the voltage control delay elements are output. The signals have a phase difference of 90 degrees, and the two signals output from the output terminals having different numbers of passing stages by 1/2 have a phase difference of 180 degrees.

Therefore, assuming that the number of voltage control delay elements in the voltage control delay line is 4n (n is a natural number), m, m + n, m + 2n, m + 3n (m is a natural number of 0 <m≤n) from the side closer to the input. The signals output from the output terminals of the four voltage control delay elements are 0 degrees when the phase of the signals output from the output terminals of the m-th voltage control delay elements is 0 degrees.
The signals are 0, 90, 180, and 270 degrees delayed in phase.

A multiplied signal can be generated by inputting these signals into the XOR circuit.

FIG. 2 shows a first embodiment of the differential XOR circuit of the present invention.

For example, the input terminal 211 is 0 degrees, and the input terminal 2 is
13 to 90 degrees, input terminal 212 to 180 degrees, input terminal 2
Suppose that 14 is given a signal whose phase is delayed by 270 degrees.

FIG. 8 shows an example of a signal when such a signal is applied to the differential XOR circuit of FIG.

If the input terminal 211 is High, the input terminal 212 is Low, the input terminal 213 is High, and the input terminal 214 is Low, nMOS1, nMOS4, pM
OS23, pMOS24 on, nMOS2, nMOS
3, pMOS21, pMOS22 are turned off, the input end of the inverter 41 becomes High, and the output end of the inverter 41 becomes Low.

If the input terminal 211 is Low, the input terminal 212 is High, the input terminal 213 is High, and the input terminal 214 is Low, nMOS3, nMOS4, pM
OS21, pMOS24 on, nMOS1, nMOS
2, the pMOS 23 and the pMOS 22 are turned off, the input end of the inverter 41 becomes Low, and the output end of the inverter 41 becomes High.

If the input terminal 211 is High, the input terminal 212 is Low, the input terminal 213 is Low, and the input terminal 214 is High, then nMOS1, nMOS2, pM
OS23, nMOS22 turned on, nMOS3, nMOS
4, the pMOS 21 and the pMOS 24 are turned off, the input end of the inverter 41 becomes Low, and the output end of the inverter 41 becomes High.

If the input terminal 211 is Low, the input terminal 212 is High, the input terminal 213 is Low, and the input terminal 214 is High, then nMOS3, nMOS2, pM.
OS21 and pMOS22 are on, nMOS1 and nMOS
4, the pMOS 23, and the pMOS 24 are turned off, the input end of the inverter 41 becomes High, and the output end of the inverter 41 becomes Low.

As described above, this differential type XOR circuit has a smaller difference in signal transmission paths and a smaller difference in delay time depending on signal states, as compared with a normal XOR circuit. pMOS and nMO
Although there is a difference between the rise time and the fall time due to the difference in S, the jitter is the fluctuation of the cycle from the rise to the rise or from the fall to the fall, so the difference between the rise time and the fall time does not affect much. .

FIG. 3 shows a second embodiment of the differential XOR circuit of the present invention. The MOS transistors are different in vertical stacking position, that is, a MOS transistor directly connected to a power supply or a MOS transistor in which another MOS transistor is sandwiched between the power supply (for example, pMOS in FIG. 2). The magnitude of the substrate effect varies depending on the difference in the positions of the transistors 21 and 22, and the delay time slightly varies depending on the difference in the input terminals. The XOR circuit of FIG. 3 reduces the difference in delay time due to this substrate effect by taking the symmetry of this position.

For example, in FIG. 2, the input terminal 211 is connected to the pMOS transistor 21 directly connected to the power source and the nMOS transistor 1 directly connected to the power source, but the input terminal 213 is not directly connected to the power source.
Since it is connected to the OS transistor 22 and the nMOS transistor 4 that is not directly connected to the power supply, the type of transistor connected differs depending on the input terminal.

However, in FIG. 3, the input terminal 221 is not directly connected to the pMOS transistor 25 directly connected to the power source, the pMOS transistor 28 not directly connected to the power source, the nMOS transistor 5 directly connected to the power source, and the power source. The nMOS transistor 8 is connected, and the input terminal 223 is a pMOS transistor 27 directly connected to the power supply, a pMOS transistor 26 not directly connected to the power supply, an nMOS transistor 11 directly connected to the power supply, and an nMOS not directly connected to the power supply. The transistors 10 are connected, and the types of transistors connected by the input terminals are the same.

By doing so, the difference in delay time depending on the state of the input signal becomes smaller than that in the XOR circuit of FIG.

[0030]

As described above, the configuration of the present invention can be used to reduce the jitter of the output clock in the PLL clock multiplication circuit using the voltage control delay line.

[Brief description of drawings]

FIG. 1 is a PL using a voltage control delay line of the present invention.
It is a figure which shows the Example of an L clock multiplication circuit.

FIG. 2 is a first embodiment of the differential XOR circuit of the present invention.

FIG. 3 is a second embodiment of the differential XOR circuit of the present invention.

FIG. 4 is a PLL using a conventional voltage control delay line.
It is a figure which shows the example of a clock multiplication circuit.

FIG. 5 is a first embodiment showing a configuration of a conventional XOR circuit.

FIG. 6 is a second embodiment showing the configuration of a conventional XOR circuit.

FIG. 7 is an example of a voltage control delay line.

FIG. 8 is an example of an input signal and an output signal of a differential XOR circuit.

[Explanation of symbols]

 1-12 nMOS transistor 21-32 pMOS transistor 41-45 Inverter circuit 51-52 Transfer gate circuit 61 NAND circuit 71 OR-NAND circuit 81-88 Voltage control delay element 101,111 Phase comparator 102,112 Loop filter 103,113 Voltage control delay line 104 Differential XOR circuit of the present invention 114 Conventional XOR circuit 201 Input clock terminal 301 Output clock terminal 211-214 Input terminal 311 Output terminal 221-224 Input terminal 321 Output terminal 231 Input clock terminal 331 Output clock terminal 331 241, 242 Input terminal 341 Output terminal 251, 252 Input terminal 351 Output terminal 261 Input clock terminal 262 Delay control element 361 Output clock terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/21 9199-5K

Claims (3)

[Claims] 1. A first nMOS transistor having a gate connected to a first input terminal and a source connected to a first power supply terminal, a gate connected to a second input terminal, and a source connected to a first input terminal. n
An nMOS transistor connected to the drain of the MOS transistor, a first pMOS transistor having a gate connected to the first input terminal and a source connected to the second power supply terminal, and a gate connected to the third input terminal And the source is the first p
Second pM connected to the drain of the MOS transistor
An OS transistor, a third nMOS transistor having a gate connected to the fourth input terminal and a source connected to the first power supply terminal, a gate connected to the third input terminal, and a source connected to the third n
A fourth nM connected to the drain of the MOS transistor
An OS transistor, a third pMOS transistor having a gate connected to the fourth input terminal and a source connected to the second power supply terminal, a gate connected to the second input terminal, and a source connected to the third p
Fourth pM connected to drain of MOS transistor
The OS transistor, the input terminal has the drain of the second nMOS transistor, the drain of the fourth nMOS transistor, and the second pMO.
It is composed of an inverter connected to the drain of the S transistor and the drain of the fourth pMOS transistor and having an output terminal connected to the first output terminal. The signal applied to the first input terminal and the fourth input terminal is 1
A differential XOR circuit having a phase shifted by 80 degrees and a signal applied to the second input terminal and a third input terminal having a phase shifted by 180 degrees. 2. A first nMOS transistor having a gate connected to a first input terminal and a source connected to a first power supply terminal, a gate connected to a second input terminal and a source connected to a first input terminal. n
Second nM connected to the drain of the MOS transistor
An OS transistor, a third nMOS transistor having a gate connected to the second input terminal and a source connected to the first power supply terminal, a gate connected to the first input terminal, and a source connected to the third n
A fourth nM connected to the drain of the MOS transistor
An OS transistor, a first pMOS transistor having a gate connected to the first input terminal and a source connected to the second power supply terminal, a gate connected to the third input terminal, and a source connected to the first p-type
Second pM connected to the drain of the MOS transistor
An OS transistor, a third pMOS transistor having a gate connected to the third input terminal and a source connected to the second power supply terminal, a gate connected to the first input terminal, and a source connected to the third p terminal
Fourth pM connected to drain of MOS transistor
An OS transistor, a fifth nMOS transistor having a gate connected to the fourth input terminal and a source connected to the first power supply terminal, a gate connected to the third input terminal, and a source connected to the fifth n
Sixth nM connected to the drain of the MOS transistor
An OS transistor, a seventh nMOS transistor having a gate connected to the third input terminal and a source connected to the first power supply terminal, a gate connected to the fourth input terminal, and a source connected to the seventh n
Eighth nM connected to the drain of the MOS transistor
An OS transistor, a fifth pMOS transistor having a gate connected to the fourth input terminal and a source connected to the second power supply terminal, a gate connected to the second input terminal, and a source connected to the fifth p terminal.
Sixth pM connected to the drain of the MOS transistor
An OS transistor, a seventh pMOS transistor having a gate connected to the second input terminal and a source connected to the second power supply terminal, a gate connected to the fourth input terminal, and a source connected to the seventh p terminal.
Eighth pM connected to the drain of the MOS transistor
The OS transistor, the input terminal has the drain of the second nMOS transistor, the drain of the fourth nMOS transistor, and the sixth nMO
The drain of the S transistor, the drain of the eighth nMOS transistor, the drain of the second pMOS transistor, the drain of the fourth pMOS transistor, the drain of the sixth pMOS transistor, and the eighth pMO
An inverter connected to the drain of the S-transistor and having an output terminal connected to the first output terminal, and a signal applied to the first input terminal and the fourth input terminal is 1
A differential XOR circuit having a phase shifted by 80 degrees and a signal applied to the second input terminal and a third input terminal having a phase shifted by 180 degrees. 3. A voltage control delay line having an input terminal connected to a first input terminal, and a phase comparator having two input terminals connected to an output terminal of the voltage control delay line and a first input terminal. A loop filter in which the output end of this phase comparator is connected to the input end, and the output end is connected to the delay control element of the voltage control delay line; and four input ends of the voltage control delay line, The differential XOR circuit according to claim 1 or 2, wherein four output terminals each having an output signal having a different phase are connected to each other, and the output terminals are connected to the first output terminal. A PLL frequency multiplication circuit characterized in that, when a clock signal is input to, the multiplied clock signal is output to the first output terminal.