JPS61128360A - 分散型疎結合マルチプロセサシステム制御方式 - Google Patents

分散型疎結合マルチプロセサシステム制御方式

Info

Publication number
JPS61128360A
JPS61128360A JP25129884A JP25129884A JPS61128360A JP S61128360 A JPS61128360 A JP S61128360A JP 25129884 A JP25129884 A JP 25129884A JP 25129884 A JP25129884 A JP 25129884A JP S61128360 A JPS61128360 A JP S61128360A
Authority
JP
Japan
Prior art keywords
logical
processor
physical
information
name
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25129884A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0215093B2 (enrdf_load_stackoverflow
Inventor
Tsutomu Osawa
勉 大沢
Shunzo Koyakata
古館　春三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25129884A priority Critical patent/JPS61128360A/ja
Publication of JPS61128360A publication Critical patent/JPS61128360A/ja
Publication of JPH0215093B2 publication Critical patent/JPH0215093B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP25129884A 1984-11-28 1984-11-28 分散型疎結合マルチプロセサシステム制御方式 Granted JPS61128360A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25129884A JPS61128360A (ja) 1984-11-28 1984-11-28 分散型疎結合マルチプロセサシステム制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25129884A JPS61128360A (ja) 1984-11-28 1984-11-28 分散型疎結合マルチプロセサシステム制御方式

Publications (2)

Publication Number Publication Date
JPS61128360A true JPS61128360A (ja) 1986-06-16
JPH0215093B2 JPH0215093B2 (enrdf_load_stackoverflow) 1990-04-11

Family

ID=17220723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25129884A Granted JPS61128360A (ja) 1984-11-28 1984-11-28 分散型疎結合マルチプロセサシステム制御方式

Country Status (1)

Country Link
JP (1) JPS61128360A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6349963A (ja) * 1986-08-20 1988-03-02 Nippon Telegr & Teleph Corp <Ntt> プロセツサ間通信方法
JPS63271538A (ja) * 1987-04-28 1988-11-09 Nec Corp 疎結合多重システムに於けるジヨブ自動運転制御方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6349963A (ja) * 1986-08-20 1988-03-02 Nippon Telegr & Teleph Corp <Ntt> プロセツサ間通信方法
JPS63271538A (ja) * 1987-04-28 1988-11-09 Nec Corp 疎結合多重システムに於けるジヨブ自動運転制御方式

Also Published As

Publication number Publication date
JPH0215093B2 (enrdf_load_stackoverflow) 1990-04-11

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